Abstract: A display apparatus includes a first determiner configured to determine a terminal into which a video signal inputs and to determine a terminal into which a synchronizing signal type inputs, a frequency measuring unit, a switch configured to connect one of first and second input terminals to the frequency measuring unit, and a second determiner configured to determine a video signal type input into the input terminal which is connected by the switch to the frequency measuring unit on the basis of a determination result of the synchronizing signal type in the first determiner and a measurement result of the frequency in the frequency measuring unit and to determine a video signal type input into the input terminal which is not connected by the switch to the frequency measuring unit on the basis of the determination result of the synchronizing signal type in the first determiner.

Abstract: A display device including a display panel which displays a video signal is disclosed. The display device includes a panel driver configured to drives the display panel; a light source configured to provide light to the display panel; a light source driver configured to control the brightness of the light source in accordance with a pulse width modulation dimming signal in synchronization with a vertical sync signal; and a controller configured to receive the vertical sync signal, determine whether the frequency of the vertical sync signal is normal or abnormal, and provide the dimming signal (PWM pulses) to the light source driver in non-synchronization with the vertical sync signal during at least one frame, in response to the frequency of the vertical sync signal being abnormal.

Abstract: A measuring device for measuring a response speed of a display panel is provided. The measuring device includes a microcontroller and at least one photo sensor. The microcontroller provides a control command, according to which a display controller of the display panel provides test pattern to the display panel. The photo sensor senses a test frame displayed corresponding to the test pattern by the display panel, and provides a corresponding sensing signal associated with brightness and a response signal. According to the response signal, the response speed of the display panel is calculated.

Abstract: Devices and methods for dynamic dithering are provided. For example, an electronic device according to an embodiment may include image processing circuitry that operates on higher-bit-depth image data and a display panel that displays lower-bit-depth image data. To obtain the lower-bit-depth image data, the image processing circuitry may perform dynamic dithering on the higher-bit-depth image data. Such dynamic dithering may involve dithering frames of the higher-bit-depth image data based at least in part on respective rounding threshold values.

Abstract: Techniques are described that can used to synchronize the start of frames from multiple sources so that when a display is to output a frame to a next source, boundaries of current and next source are aligned. Techniques are useful to avoid visual distortions when changing from a first video source to a second video source.

Abstract: There is provided a video processing device capable of reducing the influence of a disturbance of an input vertical synchronization signal. When the synchronization signal detecting unit detects an input of the input-side vertical synchronization signal at a predetermined cycle, the synchronization signal control unit outputs the input-side vertical synchronization signal, which has been input, as an output-side vertical synchronization signal, and, when the synchronization signal detecting unit detects an input of a next input-side vertical synchronization signal before the predetermined cycle elapses after the output of the output-side vertical synchronization signal, a next input-side vertical synchronization signal input before the predetermined cycle elapses is not output as a next output-side vertical synchronization signal, and an input-side vertical synchronization signal input further next is output as the next output-side vertical synchronization signal.

Abstract: A received image displaying apparatus comprises: a wireless communication unit that wirelessly receives the frame images transmitted by the image transmitting apparatus with which the received image displaying apparatus has established a connection of wireless communication; and a displaying unit that displays the frame images, which were wirelessly received by the wireless communication unit, in an order in which the frame images were captured.

Abstract: A method and system for boosting a clock frequency for a processor in a mobile device based on user interface (UI) demand are described. In response to a user interaction through a UI in the mobile device, a vertical synchronization pulse request is made by an application and an indication of such request can be provided to a governor. The governor can adjust a clock frequency of a processor in the mobile device based on the generated indication. The processor can be a central processing unit or a graphics processing unit. The clock frequency can be boosted to a higher frequency to increase the processing capabilities of the mobile device to handle the computational requirements of the user interaction. Some time after boosting the clock frequency of the processor, the governor can return to normal operations in which the clock frequency scaling is typically based on a measured system load.

Abstract: A video signal processing circuit includes: a composite sync signal generation circuit, generating a composite sync signal from a received composite video signal; a signal-noise-ratio calculation unit, generating a SNR of the composite video signal; a timing generation unit, generating a gated window based on the SNR; and a vertical sync signal separation unit, generating a vertical sync signal from the composite sync signal based on the SNR and the gated window, and dynamically adjusting a detection criterion on the vertical sync signal.

Abstract: Provided is a video display device that quickly determines, when a video signal of unknown resolution is input from the outside, the resolution of the video signal to correctly display a video.

Abstract: A display apparatus includes a first determiner configured to determine a terminal into which a video signal inputs and to determine a terminal into which a synchronizing signal type inputs, a frequency measuring unit, a switch configured to connect one of first and second input terminals to the frequency measuring unit, and a second determiner configured to determine a video signal type input into the input terminal which is connected by the switch to the frequency measuring unit on the basis of a determination result of the synchronizing signal type in the first determiner and a measurement result of the frequency in the frequency measuring unit and to determine a video signal type input into the input terminal which is not connected by the switch to the frequency measuring unit on the basis of the determination result of the synchronizing signal type in the first determiner.

Abstract: A synchronization signal control circuit according to embodiments includes a phase difference detecting section and a vertical synchronization correction control section. When a vertical synchronization period of an input video signal is within a compensation period range between a minimum vertical synchronization period and a maximum vertical synchronization period, the synchronization signal control circuit outputs a display vertical synchronization signal used for displaying the input video signal to a display section capable of providing a display based on the input video signal. The phase difference detecting section detects a phase difference between an input vertical synchronization signal based on the input video signal and the display vertical synchronization signal. The vertical synchronization correction control section corrects the cycle period of the display vertical synchronization signal within the compensation period range so as to reduce the phase difference.

Abstract: A method for recovering pixel clocks based on an iDP interface includes selecting a prime factor closest to VA or HA from prime factors of X, and selecting a value obtained by subtracting VA from the selected prime factor, as VB, in Mvid = ( HA + HB ) × ( VA + VB ) X , where HA indicates a horizontal active period, HB indicates a horizontal blank interval, VA indicates a vertical active period, and VB indicates a vertical blank interval, fixing the selected VB value, and selecting a total of HB within one frame period and the number of lanes under a condition that Mvid has an integer value, and recovering pixel clocks by multiplying a frequency of link symbol clocks of data received via the lanes by a multiplication of Mvid/48.

Abstract: According to the present invention, the sound quality of an apparatus having HDMI outputs exclusive for both of an audio signal and a video signal can be further improved. According to the present invention, even when the calculated value of CTS obtained using a first video clock signal Vc1 generated by a decoder 204 is other than an integer, a value of a second video clock signal Vc2 and an N value are set such that the calculated value of CTS obtained using the second video clock signal Vc2 is an integer. By using the value of second video clock signal Vc2 and the N value set in this manner, an audio reproducing apparatus 103 can generate an audio clock signal Ac having reduced jitter.

Abstract: The invention discloses a sink device. The sink device comprises a buffering unit and a clock generating unit. The buffering unit receives a decoding data according to a symbol clock signal, reads the decoding data according to a pixel clock signal, and generates a water level value. The clock generating unit receives the symbol clock signal to generate the pixel clock signal and adjusts a rate of the pixel clock signal according to the water level value and/or a phase difference signal.

Abstract: According to embodiments, a color signal processing circuit includes: an A/D converter configured to convert an analog television signal into a digital signal by using a clock; a color signal demodulation circuit configured to color-demodulate the television signal converted into the digital signal by the A/D converter; a clock generation section configured to generate the clock that is used by the A/D converter; and a frequency control section configured to control the clock frequency of the clock generation section on the basis of a color subcarrier frequency of a color signal included in the analog television signal and on the basis of the vertical synchronization signal frequency of the analog television signal.

Abstract: A video signal synchronization signal generating apparatus for making a display reference synchronization signal Vb that serves as a reference of video display and has a first frequency and an input synchronization signal Vi that constitutes images and has a second frequency synchronized with each other, the apparatus including: a frequency ratio generating section configured to divide a frequency that is double the first frequency by the second frequency to calculate a frequency ratio n; a Vx generation comparator circuit section configured to generate coincidence signal Vx? having pulses that are inserted by equally dividing one period of the input synchronization signal Vi by the frequency ratio n; and a Vx generation circuit section configured to remove the alternate pulses of the coincidence signal Vx? to generate synchronization signal Vx of a same phase as the phase of the input synchronization signal Vi.

Abstract: A video horizontal synchronizer outputting a line timing signal and an indicating flag of a received video signal for use in a video signal post-processing unit, including a filter outputting a wide bandwidth filtered and a narrow bandwidth filtered signals of the received video signal, a dynamic slicer threshold generator generating a slicer threshold, a timing recovery circuit generating a phase error and the line timing signal, a phase error statistics circuit averaging the phase error to generate a average phase error, a HSYNC checker generating a matching flag indicating whether a periodic pattern appears in the narrow bandwidth filtered signal according to the line timing signal, and a finite state machine controlling the dynamic slicer threshold generator, the timing recovery circuit, the phase error statistics circuit and the HSYNC checker and generating an indicating flag when the average phase error is small enough and the matching flag is confirmed.

Abstract: A synchronizing signal control circuit includes: a phase detecting section configured to detect a phase difference between a display synchronizing signal and an input synchronizing signal; an adding section configured to add a set value for setting a synchronization compensation period and the detected phase difference; a synchronization phase correcting section configured to correct the phase of the input synchronizing signal on the basis of the output signal of the adding section; a gate signal generating section configured to generate a gate signal representing the synchronization compensation period based on the display synchronizing signal; a synchronization determining section configured to determine whether the synchronization can be effected, by detecting whether the input synchronizing signal exists within the synchronization compensation period; and a selecting section configured to perform switching to the corrected input synchronizing signal on the basis of the determination result of the synchron

Abstract: A signal generator for use in producing a video top-of-frame signal based upon an input video signal with an input video frame including one or more input video fields and having an input video frame rate for an output video signal with an output video frame having a plurality of output video frame lines, each with a plurality of output video pixels, and an output video frame rate.

Abstract: In one embodiment, a method for synchronizing a plurality of video signals received from one or more video sources is provided. The method includes providing one or more video sources and providing a codec including an internal reference oscillator. The method also includes generating a plurality of horizontal and vertical synchronization pulses based on the reference frequency of the internal reference oscillator, generating a composite synchronization pulse based on the plurality of horizontal and vertical synchronization pulses, and transmitting the composite synchronization pulse to the one or more video sources via a communication link.

Abstract: A signal synchronization device and signal synchronization method are provided. The method comprises determining whether a receiving device can receive data output from an output device synchronously and adjusting the dummy period of the signal, which will be received by the receiving device, when the data output from the output device cannot be received by the receiving device synchronously.

Abstract: An integrated video clock signal generator in which a master phase-locked loop (PLL) control circuit uses an off-chip voltage-controlled oscillator (VCO) to produce an on-chip oscillator signal in synchronization with a horizontal reference signal related to a horizontal video synchronization signal. This on-chip oscillator signal drives one or more slave PLL circuits which provide respective one or more on-chip PLL signals synchronized with the on-chip oscillator signal. In accordance with a preferred embodiment, each on-chip PLL signal is a pixel clock signal with a plurality of clock signal pulses which is synchronized with a vertical reference signal related to a vertical video synchronization signal.

Abstract: A video signal receiver including a display synchronizing signal generation device and control method are disclosed. The video signal receiver includes: a video processor converting an input analog video signal into a digital signal; a display processor scaling the video signal converted at the video processor with an output resolution; a displaying unit displaying the video signal scaled by the display processor; a detecting unit detecting whether an input vertical synchronization signal (In V-sync) and an output vertical synchronization signal of the analog video signal match; a PLL (Phase Locked Loop) adjusting a pixel clock according to a detection result of the detecting unit; and a timing generating unit generating an output horizontal synchronization signal and the output vertical synchronization signal by use of the pixel clock adjusted by the PLL, and providing the generated output horizontal and output vertical synchronization signals to the display processor and the detecting unit.

Abstract: According to an aspect of the present invention, there is provided an electronic apparatus including: a detection unit configured to detect a start of a reproducing of a motion picture to be displayed on a display unit; a change unit configured to change a refresh rate of the display unit when the start of the reproducing of the motion picture is detected, the refresh rate being changed not by changing an operating frequency of the display unit, the refresh rate being changed by changing a blanking period, the blanking period being a period during which a drawing operation of a screen on the display unit is not performed; and a control unit configured to control the display unit to display the motion picture based on the changed refresh rate.

Abstract: A system for transmitting auxiliary data within a modulated video signal from a broadcast source to a hand-held device with a slot, the system comprising the broadcast source comprises means for transmitting auxiliary data to the slotted hand-held device via the modulated video signal; an interface device electronically coupled to the hand-held device via the slot and comprises a card microcontroller, a receiver electronically coupled to the card microcontroller for receiving the modulated video signal from the broadcast source, and circuitry electronically coupled to the card microcontroller and the receiver for demodulating the modulated video signal and reproducing the auxiliary data, and transferring the auxiliary data to the hand-held device via an interface protocol, and the hand-held device with the slot comprises a microcontroller for processing the signal auxiliary data received via the interface protocol from the interface device.

Abstract: A frame-based phase-locked display controller used in a display system and method thereof are described. The frame-based phase-locked display controller for displaying a plurality of image frames in a video signal comprises a frame-based phase-locked loop and a synchronization signal generator. The frame-based phase-locked loop receives an oscillating signal and an input vertical synchronous signal to generate an output clock signal by phase-lock loop based on the frames. The synchronization signal generator, coupled to the frame-based phase-locked loop, receives the output clock signal to generate an output horizontal synchronous signal, an output vertical synchronous signal and an output display enable (DE) signal. The frame-based phase-locked loop comprises a first PLL, a frequency synthesizer, a second PLL, a fast phase detector, a phase frequency detector and an active pixel region generator.

Abstract: Apparatuses and methods are described for performing time base correction and frame rate conversion with respect to signals. An apparatus includes circuitry to synthesize an output video clock. The apparatus has circuitry that receives an input video synchronization signal. The apparatus has circuitry to change a frequency of the output video clock based on an intended number of video clock cycles per input vertical period and a period of the input video synchronization signal.

Abstract: A system for transmitting auxiliary data within a modulated video signal from a broadcast source to a hand-held device with a slot, the system comprising the broadcast source comprises means for transmitting auxiliary data to the slotted hand-held device via the modulated video signal; an interface device electronically coupled to the hand-held device via the slot and comprises a card microcontroller, a receiver electronically coupled to the card microcontroller for receiving the modulated video signal from the broadcast source, and circuitry electronically coupled to the card microcontroller and the receiver for demodulating the modulated video signal and reproducing the auxiliary data, and transferring the auxiliary data to the hand-held device via an interface protocol, and the hand-held device with the slot comprises a microcontroller for processing the signal auxiliary data received via the interface protocol from the interface device.

Abstract: A synchronization control apparatus for driving a display module in an interlacing scan mode includes: a delay circuit for delaying an input vertical sync (IVS) signal to generate a delayed signal; and a multiplexer coupled to the delay circuit for selecting one of the IVS signal and the delayed signal according to an odd/even field indication signal to generate an output vertical sync (OVS) signal.

Abstract: A method for synchronizing video signals is provided wherein a synchronization state signal is generated which is descriptive for the synchronization of an output of fields/frames with the respective input of respective fields/frames of an underlying video data screen in particular on the basis of a time difference which is given by respective counted times and/or temporal changes and/or variations thereof.

Abstract: A method for adjusting a phase of a sampling frequency of ADC is disclosed. The method includes converting an analog signal into a first digital signal according to a first phase of the sampling frequency during a first time interval; calculating a first value according to the first digital signal; converting the analog signal into a second digital signal according to a second phase of the sampling frequency during a second time interval; calculating a second value according to the second digital signal; and adjusting the phase of the sampling frequency according to the first value and the second value.

Abstract: A method and system for synchronizing video information derived from an asynchronously sampled video signals provide a mechanism for using asynchronous sampling in the front-end of digital video capture systems. A ratio between the sampling clock frequency and the source video clock frequency is computed via an all digital phase-lock loop (ADPLL) and either a video clock is generated from the ratio by another PLL, a number to clock converter or the ratio is used directly to provide digital synchronization information to downstream processing blocks. A sample rate converter (SRC) is provided in an interpolator that either acts as a sample position corrector at the same line rate as the received video, or by introducing an offset in the ADPLL, the video data can be converted to another line rate via the SRC.

Abstract: To acquire much accurate image information having no noise, without increasing load in the post-processing of the image information, a receiving apparatus 3 includes: a synchronization signal detector 34 that detects a horizontal synchronization signal and a vertical synchronization signal; an image processor 35 that performs an image generation process of each frame based on the horizontal synchronization signal and the vertical synchronization signal detected by the synchronization signal detector 34; and an image deletion controller 36a that controls to delete an image of the current frame, when a horizontal synchronization signal within one frame detected by the synchronization signal detector 34 is not continuously detected by a first predetermined number or more, or when a horizontal synchronization signal within one frame detected by the synchronization signal detector 34 is not detected by a second predetermined number or more, or when a vertical synchronization signal detected by the synchronization

Abstract: A flat display device includes, vertical synchronization lock means which generates an internal vertical synchronization signal, a window signal generating circuit which generates a window signal by use of the internal vertical synchronization signal, a detecting circuit which detects whether or not an external vertical synchronization signal is present in a period of the window signal, and a determination circuit which determines whether a preset condition that a plurality of detection signals are present in a preset period is satisfied or not and controls an output inhibition circuit to inhibit a gate signal from being output when the preset condition is not satisfied.

Abstract: The invention discloses a sink device. The sink device comprises a buffering unit and a clock generating unit. The buffering unit receives a decoding data according to a symbol clock signal, reads the decoding data according to a pixel clock signal, and generates a water level value. The clock generating unit receives the symbol clock signal to generate the pixel clock signal and adjusts a rate of the pixel clock signal according to the water level value and/or a phase difference signal.

Abstract: In a sync processor for determining safety of signals on the basis of a horizontal/vertical sync signal generated according to a data enable signal, the sync processor includes a digital horizontal/vertical signal generator, a selector, a digital horizontal/vertical signal detector, a horizontal/vertical polarity determination unit, and a horizontal/vertical frequency determination unit. The digital horizontal/vertical signal generator generates a digital horizontal/vertical sync signal from the data enable signal. The digital horizontal/vertical signal detector detects a signal received from the selector and generates a digital horizontal/vertical signal. The horizontal/vertical polarity determination unit counts the number of low and high durations of a horizontal/vertical sync signal and generates a horizontal/vertical polarity signal in response.

Abstract: The present invention provides a method for reducing analog PLL (Phase-lock loop) jitter in video ADC application. The HSync/CSync is replaced with a faked HSync signal to be inputted to PLL during vertical blank period. Therefore the analog PLL will only see the faked HSync signal of fixed period as a line-lock trigger signal, while no COAST signal is required. Also, the faked HSync is fine-tuned to match with the external HSync/CSync leading edge to minimize PLL jitter.

Abstract: There is provided a vertical frequency distinction circuit and a vertical frequency distinction method capable of reducing a chip area, and a video display apparatus having the vertical frequency distinction circuit. A vertical control pulse generating section of the vertical frequency distinction circuit generates a noise eliminating signal for disabling input of noise during a predetermined period until arrival of a vertical synchronization signal. A distinction result latch section samples the noise eliminating signal and an inversion signal of the noise eliminating signal at the timing of input of the vertical synchronization signal, to generate two output signals. An output selecting section selects either one of the two output signals of the distinction result latch section based on a mode setting signal, to output the selected signal as a distinction result signal.

Abstract: The present invention discloses a PLL (90), which may be implemented in software, hardware, or a combination of software and hardware, which comprises a sync detector (92), a loop filter (94), a vertical sync discrete time oscillator (DTO) (98), and an output logic (100) adapted to detect a vertical sync (222), wherein the loop filter (94), the vertical sync DTO (98), and the output logic (100) are coupled to the sync detector (92).

Abstract: A display synchronization signal generation apparatus and method, which make it possible to display a stable image irrespective of changes of horizontal and vertical frequencies of a received analog video signal in an analog video signal receiver. The display synchronization signal generation apparatus includes a detection unit, a change amount conversion unit, and a vertical synchronization signal generation unit. The detection unit detects an amount of change in a vertical period of an input video signal by comparing current and previous vertical periods of the input video signal. The change amount conversion unit converts the detected amount of change into the amount of change in a vertical period of a video signal to be displayed, using the current vertical period and the total number of pixels per frame. The vertical synchronization signal generation unit generates a vertical synchronization signal of the video signal to be displayed.

Abstract: An external synchronous signal circuit comprises: means for measuring a phase difference between the external frame synchronous signal (FRM_SYNC) and the frame synchronous signal (FRM) of the digital video signal; means for generating a signal (EXT_H) having the same period as that of the horizontal synchronous signal (HBK) of the digital video signal, the signal (EXT_H) having the measured phase difference with reference to the frame synchronous signal (FRM) of the digital video; and means for generating a signal (EXT_F) having the same period as that of the frame synchronous signal (FRM) of the digital video signal, the signal (EXT_F) having the measured phase difference with reference to the frame synchronous signal (FRM) of the digital video. The generated signals (EXT_F) and (EXT_H) are outputted as an external frame timing signal and an external horizontal timing signal of an external synchronous signal.

Abstract: The present invention discloses a PLL (90), which may be implemented in software, hardware, or a combination of software and hardware, which comprises a sync detector (92) adapted to output a phase error (152), a vertical sync discrete time oscillator (DTO) block (98) adapted to output a vertical sync DTO (130) based on the phase error (152), and an output logic (100) adapted to detect a vertical sync based on the vertical sync DTO (130).

Abstract: A frame signal phase adjuster comprises units for inputting a parallel clock and a reference signal (22-4 and 22-1); generating a frame signal from the reference signal (22-1), adjusting a phase of the frame signal (22-3), generating an adjusted frame signal synchronized by the parallel clock from the parallel clock and the adjusted frame signal (22-4), generating a frame reset pulse signal based on the parallel clock and the adjusted frame signal synchronized by the parallel clock (22-2), and outputting the frame reset pulse signal (22-2). The unit (22-4) adjusts the phase of the frame signal so that the frame signal is constantly HIGH or LOW throughout a setup time and a hold time.

Abstract: To match the output frame rates to the input frame rates, a display clock signal is generated that has a frequency locked to the frequency of a reference clock signal. To generate the display clock signal, the period of the vertical incoming data clock is measured using the reference clock signal. The number of pixels disposed in the output frames is subsequently divided by the measured period. A fractional-N phase-locked loop circuit is adapted to multiply the result of the division with the frequency of the reference clock signal to generate the display clock signal. The display clock signal is also locked to the reference clock signal.

Abstract: A confocal microscope apparatus has a confocal scanner for scanning a sample with shifting a focal position of a light beam in a direction perpendicular to an optical axis, a moving mechanism for moving the focal position of the light beam in an optical axis direction, a camera for picking up an image of the sample with the light beam, and a movement control unit for controlling the moving mechanism to move the focal position of the light beam by a predetermined distance in the optical axis direction for every vertical synchronizing signal of the camera in synchronization with the vertical synchronizing signal. A high-speed three-dimensional image can be displayed in such that while measuring the sample, two or more slice images in such an arrangement on a common screen that their positions relative to the sample enables to be grasped.

Abstract: The vertical sync signal generator includes: a vertical sync signal separation circuit for separating a vertical sync signal of an input luminance signal and outputting the separated signal as a first vertical sync signal; an automatic frequency control circuit for generating a second vertical sync signal having a repeat frequency corresponding with an average repeat frequency of the first vertical sync signal and outputting the generated signal; a vertical sync signal phase detection circuit for detecting whether or not the first vertical sync signal has two different periods repeated alternately and outputting the detection result as a decision signal; and a selector for receiving the first and second vertical sync signals, selecting the first vertical sync signal when the decision signal indicates that the first vertical sync signal has two different periods repeated alternately and otherwise selecting the second vertical sync signal and outputting the selected signal.

Abstract: A device for correcting the phase of a vertically distorted digital picture receives picture data and a vertical phase correction signal, and assigns lines of the digital picture to a first half picture and to a second half picture. The lines of the second half picture are phase corrected with respect to the first half picture and the first and second half pictures are displayed sequentially. The phase correction is determined in response an increment signal that describes the change of an imaging factor in the veritcal direction of the digital picture on a line-by-line basis and a picture position signal indicative of whether the first half picture or the second half picture is being output.

Abstract: The object of the invention is to provide a video switchover detection circuit that reduces the circuit scale and allows high-accuracy detection with a smaller-scale configuration. According to the invention, the video switchover detection circuit comprises a PLL circuit composed of a phase comparator, an LPF, a VCO, and a frequency divider. In the phase comparator, the phase of an external HD as an input signal obtained by shaping the pulse of a horizontal synchronization signal is compared with the phase of an internal HD as a reference signal obtained by dividing the frequency of the output pulse of the VCO in the PLL circuit. In case the phases of the signals differ from each other, an error signal is output from the phase comparator. A first counter counts the period in which the error signal is active, or the time when the phase difference persists.

Abstract: An inexpensive and simple circuit for improving an image quality of a dynamic image, with appropriate processing flexibly performed for dynamic image qualities also for a plurality of input signal sources.