Abstract: A portable digital television (DTV) comprises a processor, a channel and volume changing button arrangement, and a navigational button arrangement. Either or both button arrangements can be used in at least a bi-modal operation. In a first mode of operation, the button arrangements provide their normal functions, and in the second mode of operation, the button arrangements provide an interactive application interface to the user. Preferably, one of the two button arrangements is selected for the bi-modal operation. The selected button arrangement is associated with at least an optical element for lighting the button arrangement. The controller operates the optical element such that the selected button arrangement has one color in one mode of operation and has a different color in the other mode of operation.

Abstract: An apparatus in a video signal transmission system for measuring cable length and compensating for cable loss is described. A number of pilot signals of different frequencies are compressed into one of the three color signals during the vertical sync periods in a time-division manner. The vertical and horizontal sync signals are compressed into the other two color signals. The video signal is transmitted over a cable having at least three pairs of wires, each color signal being transmitted by one pair of wires. A pilot signal converting circuit obtains the levels of the pilot signals transmitted by the cable. A compensation control circuit averages the levels of the multiple pilot signals of different frequencies over a number of vertical sync periods, and generates compensation control signals based on the average level of the pilot signals. The compensation control signals are used to perform video signal compensation.

Abstract: According to embodiments, a color signal processing circuit includes: an A/D converter configured to convert an analog television signal into a digital signal by using a clock; a color signal demodulation circuit configured to color-demodulate the television signal converted into the digital signal by the A/D converter; a clock generation section configured to generate the clock that is used by the A/D converter; and a frequency control section configured to control the clock frequency of the clock generation section on the basis of a color subcarrier frequency of a color signal included in the analog television signal and on the basis of the vertical synchronization signal frequency of the analog television signal.

Abstract: In a receiver, a synchronization circuit (MIX2, OSC, C1, R1) provides a set of oscillator signals (OSI, OSQ) that are synchronized with a carrier of an amplitude-modulated signal. The set of oscillator signals (OSI, OSQ) comprises a quadrature oscillator signal (OSQ), which is substantially 90° phase shifted with respect to the carrier of the amplitude-modulated signal. A quadrature mixer (MIX2) mixes the quadrature oscillator signal (OSQ) with the amplitude-modulated signal so as to obtain a quadrature mixer output signal (MO2a). A phase-error corrector (PEC) adjusts the phase of the oscillator signals in response to a variation in the magnitude of an alternating current component (AC) in the quadrature mixer output signal (MO2a).

Abstract: The present invention relates to a video processing method and apparatus capable of performing a proper video process corresponding to various color systems. A decoder extracts color information from a received video signal including vertical synchronous information for a vertical scanning frequency of a picture, color information of the picture, and frequency information corresponding to the color information. A frequency evaluator evaluates the received vertical scanning frequency and the received frequency of the video signal color information on the basis of the vertical synchronous information and the frequency information of the color information.

Abstract: To provide a video signal processing apparatus capable of generating video signals that enable displaying and recording of a high-quality picture. A video signal processing apparatus according to an embodiment of the present invention includes a decoder decoding an input TS to generate a video signal having a field frequency fv of 60 Hz or a video signal having a field frequency fv of 59.94 Hz, and a converter converting the respective video signals into NTSC video signals having a color subcarrier the phase of which is inverted for each frame.

Abstract: A video signal processing circuit that uses a prescribed clock signal to process a digitized composite video signal. A clock generating means (2) generates the prescribed clock signal; a burst phase detecting means (3) detects color subcarrier phase information (p) in each line of the composite video signal; a phase difference calculation means (4) finds the phase difference between phase information (p) from the burst phase detecting means and a prescribed reference phase; a sampling phase conversion means (8) corrects the sampling phase of the composite video signal according to phase corrections (?b, ?t) obtained from the phase difference calculation means (4); a Y/C separation means (9) separates the luminance and chrominance signals from the composite video signal output from the sampling phase conversion means (8). Excellent two- or three-dimensional Y/C separation can be obtained regardless of the television broadcast system, even from a non-standard signal.

Abstract: Phase noise mitigation in an analog video receiver implemented in an integrated circuit device. A phase correction value that indicates a phase offset between a synthesized sinusoid and a reference sinusoid conveyed in a horizontal retrace region of a composite video signal is periodically generated. A phase error that will accumulate during an interval between horizontal retrace regions of the composite video signal is estimated based, at least in part, on the phase correction value, and the phase of a chroma signal component of the composite video signal is adjusted based on the estimated phase error.

Abstract: An analog-to-digital converting system for converting a composite video signal into a digital signal according to a synchronized clock. The analog-to-digital converting system includes an analog-to-digital converter (ADC), a color burst phase estimator and a phase-locked loop (PLL). The ADC converts the composite video signal to the digital signal according to the synchronized clock, wherein the synchronized clock is synchronized to a frequency of a color burst of a chrominance signal of the composite video signal. The color burst phase estimator, coupled to the ADC, estimates the phase of the color burst carried on the composite video signal. The PLL, coupled to the color burst phase estimator, generates the synchronized clock according to the phase of the color burst estimated by the color burst phase estimator.

Abstract: In a method and system for 3D comb synchronization and alignment of standard and non-standard video signals, a coarse synchronization is performed on a bottom frame, a current frame, and a top frame based on a bottom frame field count. The current frame is assigned the frame transferred immediately prior to a bottom frame whereas the top frame is assigned the frame transferred two frames. A current frame window signal and a top frame window signal may be used to lock the current frame and the top frame to a bottom frame vertical sync signal. After coarse synchronization, the video frames are finely aligned by correlating a phase difference between the subcarrier signals in each frame and modifying the phase difference until the correlation results in a specified phase locked value range. This method and system may facilitate the handling of video stream switching and non-standard data streams.

Abstract: A system and method for synchronizing sub-carriers in a signal processing system. Various aspects of the present invention may comprise method steps and structure that receive a sampled signal. Various aspects may produce a synchronization signal based on the sampled signal. Various aspects may generate and store a cropped version of the received sampled signal. Various aspects may read a cropped sampled signal from memory that corresponds to the received sampled signal. Various aspects may generate a restored sampled signal by adding samples to the cropped sampled signal read from memory. Various aspects may, based on the synchronization signal, output the restored sampled signal coarsely synchronized to the received sampled signal. Various aspects may determine a phase difference between the output restored sampled signal and the output received sub-carrier. Various aspects may adjust the phase of the restored sampled signal in response to the determined phase difference.

Abstract: When an A/D-converted composite video signal is directly outputted while a system clock frequency is switched so as to execute the determination of a signal system, a digital chroma demodulation system prevents the images displayed by the composite video signals from being distorted in accordance with a switching of the frequency of a system clock. The frequency m (=fsc×n) of the system clock is synchronized with a color burst signal and is set to fall in a predetermined range by changing a coefficient n in accordance with the system color burst signal freguency. Thus, since a composite video signal is A/D-converted in accordance with a substantially constant sampling frequency, the sampling condition such as a sampling frequency and a sampling point is not greatly changed.

Abstract: Chrominance phase error correction circuitry includes a demodulator for demodulating a received video color burst signal into first and second demodulated signals and signal generation circuitry for providing to the demodulator a demodulating signal for demodulating video color burst signal. Phase correction circuitry detects a phase error from the first and second demodulated signals and varies a phase of the demodulating signal to provide a corrected demodulating signal for demodulating a video chrominance signal with the demodulator during an active video period.

Abstract: A system and method for synchronizing signals having respective sub-carriers in a signal processing system. Various aspects of the present invention may comprise method steps and structure that receive a sampled signal with an associated sub-carrier. Various aspects may determine a phase of the sub-carrier and store an indication of such phase. Various aspects may generate and store a cropped version of the sampled signal. Various aspects may also store an indication of which samples were cropped from the sampled signal. Various aspects may produce a synchronization signal based on the sampled signal. Various aspects may read a cropped version of a sampled signal and an associated indication of phase. Various aspects may generate a restored sampled signal by adding samples to the read cropped version. Various aspects may, based on the synchronization signal and indication of phase, output the restored sampled signal aligned with a second sampled signal.

Abstract: Certain embodiments of the invention disclose a method and system for processing in a non-line locked system. The phase relationship between the sub-carrier signal on consecutive video lines in a video comb filter is determined by synchronizing the two video lines. The synchronization is achieved by aligning the color bursts signals in each of the two video lines. The phase error between the two video lines is determined through the use of a correlation operation. The phase error between consecutive video lines is used to automatically adjust the delay lines used by the video comb filter. The line delay adjustment is provided by changing the values of a variable integer delay and a fractional integer delay. Line delay adjustments reduce the artifacts that occur in the separation of luma and chroma components of a composite video signal.

Abstract: An apparatus to compensate a color carrier in an image processing system to convert an input analog image signal into a digital image signal includes a detector, a phase-locked loop unit, a difference detector, and a color signal processor. The detector detects a frequency of the color carrier in a color signal of the digital image signal. The phase-locked loop unit generates a subcarrier frequency by performing a phase-locked loop operation on a system clock signal applied to the image processing system. The difference detector detects a difference between the frequency of the color carrier and the subcarrier frequency. The color signal processor compensates for a phase deviation of the color carrier of the color signal using the subcarrier frequency generated by the phase-locked loop unit.

Abstract: A broadcast data receiver (BDR) is provided and a method of using the BDR for the production of a pseudo stable reference control for the reliable generation of composite video signals. The BDR receives video, audio and/or auxiliary data from a broadcaster can stored a part of all of the data in storage means, typically in the form of a hard disk drive. When the BDR is deriving video data from the hard disk due to the BDR being disconnected from the signal feed from the broadcaster, the BDR uses a pseudo stable reference produced by deriving one or more values from stable frequency information embedded in incoming data. The pseudo stable reference is used to control the frequency of a VCXO in the BDR, thereby allowing accurate color sub-carrier frequency generation for the generation of a final video output.

Abstract: A simulated burst gate signal and a video synchronization key are generated. A video decoder generates a horizontal sync pulse which is programmed to envelop a color burst, thereby simulating a burst gate signal. The offset to the horizontal sync pulse due to simulating a burst gate signal may be compensated at a video memory subsystem receiving the horizontal sync signal, in order to determine when active pixels are provided by the video decoder. Alternatively, counter circuitry external to the video decoder may be used to generate a simulated burst gate signal by counting the number of pixel clock cycles between the horizontal sync pulse and the color burst. Unlike a burst gate signal generated within a video decoder for use with color separation circuitry in the video decoder, a simulated burst gate signal allows for use of color separation circuitry external to the video decoder. Detecting a color burst using external color separation circuitry is thus also disclosed.

Abstract: An embodiment of the present invention provides a signal generator for generating a signal with a predetermined frequency. The signal generator includes a first comparator for generating a first error signal and a second comparator for generating a second error signal. The first and second comparators are coupled to an oscillator configured to receive the first and second error signals and generate the signal having a predetermined frequency. Another embodiment of the present invention provides a signal generator for generating a signal with a predetermined frequency. The signal generator includes a counter for generating a first count, Q_last. The counter is coupled to a ratio counter which generates a signal having a value less than or equal to Q_last. The contents of the ratio counter represent the phase of the signal having a predetermined frequency. The ratio counter outputs the signal having a predetermined frequency.

Abstract: A periodic multi-bit digital signal is synthesized having a frequency that is specified by the frequency of a periodic reference signal that is asynchronous with respect to a sampling clock of the periodic digital signal. In a digital video system, for example, a digital color subcarrier is synthesized and synchronized to a reference frequency of a crystal oscillator that is asynchronous with respect to a digital system clock for the digital video system. The periodic digital signal is generated by an adjustable digital oscillator clocked by the sampling clock. The frequency or phase of the periodic digital signal is compared to the frequency or phase of the periodic reference signal to produce an adjustment value for adjusting the periodic digital signal to synchronize the periodic digital signal with the periodic reference signal. The digital oscillator, for example, generates the periodic digital signal at the sampling rate by periodically incrementing an accumulator with the adjustment value.

Abstract: A compact, inexpensive circuit for generating several stable reference signals from several burst signals is provided.

Abstract: A digital PLL circuit employs a fixed-frequency output signal from a fixed-frequency oscillator, to provide a signal synchronized with an external reference signal. The digital PLL circuit has a counter and an adjuster. The counter counts clock periods (clock pulses) of the fixed-frequency output signal. The adjuster increments or decrements a value counted by the counter a predetermined number of times in a predetermined period according to a deviation of the fixed-frequency output signal from the reference signal. This digital PLL circuit is inexpensive because it employs no DA converter nor VCO.

Abstract: A periodic multi-bit digital signal is synthesized having a frequency that is specified by the frequency of a periodic reference signal that is asynchronous with respect to a sampling clock of the periodic digital signal. In a digital video system, for example, a digital color subcarrier is synthesized and synchronized to a reference frequency of a crystal oscillator that is asynchronous with respect to a digital system clock for the digital video system. The periodic digital signal is generated by an adjustable digital oscillator clocked by the sampling clock. The frequency or phase of the periodic digital signal is compared to the frequency or phase of the periodic reference signal to produce an adjustment value for adjusting the periodic digital signal to synchronize the periodic digital signal with the periodic reference signal. The digital oscillator, for example, generates the periodic digital signal at the sampling rate by periodically incrementing an accumulator with the adjustment value.

Abstract: A video transmission system and method including a technique for deriving clock information in a receiver from a transmitted analog video signal to decipher digital data encoded on the video signal. A phase-locked loop in the transmitter is used to phase-lock a color burst subcarrier in the video signal to a local oscillator in the phase-locked loop to phase-lock a data clock to the subcarrier. A phase-locked loop in the receiver is also used to phase-lock the subearrier of the transmitted video signal to a local oscillator in the phase-locked loop to again phase-lock a data clock to the subcarrier. By phase-locking a data clock to the subcarrier in both the transmitter and receiver, the data clock and the receiver can be synchronized to the data clock and the transmitter to provide for effective digital data recovery without the use of additional data bits for clock phase information.

Abstract: A clock signal generator and method for generating a clock signal which is synchronized with an input composite video signal. The generator comprises a synchronizing separator for separating a horizontal synchronizing signal from an input composite video signal; a burst separator for separating a color burst signal from the input composite video signal; a phase error detector for receiving the horizontal synchronizing signal, detecting a phase error and outputting a phase error signal for a previous horizontal period; a phase change detector for receiving the color burst signal, detecting a phase change of the color burst signal, and outputting a phase change signal for a present horizontal period; an adder for adding the phase error signal and the phase change signal; and a clock signal generator for receiving an output of the adding means and generating a clock signal which is synchronized with the input composite video signal.

Abstract: A phase detector provides angular phase error measurements of the color burst component of a video input signal. Burst phase errors exceeding a given angular threshold are detected and the number occurring within a given period of time are counted. From the accumulated count, a noise indicating signal is derived and applied to a video picture processor for controlling a parameter of displayed images.

Abstract: An arrangement for synchronizing a digitally generated color subcarrier signal to the color burst signal from another video signal, such as that from a video casette recorder or from a cable television signal, in a manner that allows a line locked clock to be used without causing unacceptable disturbance to the generated subcarrier signal.

Abstract: A periodic multi-bit digital signal is synthesized having a frequency that is specified by the frequency of a periodic reference signal that is asynchronous with respect to a sampling clock of the periodic digital signal. In a digital video system, for example, a digital color subcarrier is synthesized and synchronized to a reference frequency of a crystal oscillator that is asynchronous with respect to a digital system clock for the digital video system. The periodic digital signal is generated by an adjustable digital oscillator clocked by the sampling clock. The frequency or phase of the periodic digital signal is compared to the frequency or phase of the periodic reference signal to produce an adjustment value for adjusting the periodic digital signal to synchronize the periodic digital signal with the periodic reference signal. The digital oscillator, for example, generates the periodic digital signal at the sampling rate by periodically incrementing an accumulator with the adjustment value.

Abstract: A chroma lock detector circuit monitors charge pump control signals within a phase-lock loop to determine when two input signals to the phase-lock loop are locked together in phase and generates an output signal which is active when the two input signals are locked together in phase and inactive when the two input signals are not locked together in phase. The charge pump control signals are generated in response to a difference in phase between the two input signals and will become inactive once the two input signals are locked together in phase. When the charge pump control signals are inactive for a predetermined period of time, the output of the chroma lock detector circuit is activated and will remain active until the charge pump control signals are again active. A current source is enabled when either of the control signals are active. The current source builds up a first level of charge on a first capacitor during the burst period.

Abstract: A digital color burst phase switch for determining phase shift of a color burst signal in a PAL video signal includes a phase selector for selecting either a first reference clock or a second reference clock in response to a PAL switch signal. A phase delay device delays the phase of either the first reference clock or the second reference clock selected by the phase selector to generate a third reference clock. A phase comparator compares the phase of the third reference clock to the phase of the color burst signal to generate a control signal. The control signal is integrated over substantially the entire color burst signal to generate an integration value. This integration value is compared to a threshold value in a threshold device to generate a correction signal.

Abstract: A digital phase error detector for locking to a color subcarrier signal in an analog video signal. The digital phase error detector includes a digitizer responsive to a sample clock which generates a first digital data stream from the analog video signal. Filtering circuitry filters the first digital data stream to generate a second data stream by substantially eliminating DC offset of the color subcarrier signal digitized by the digitizer. A mixer mixes the second digital data stream to generate a third digital data stream representing sum and difference frequencies of a product of the color subcarrier signal and a reference clock. An accumulator accumulates this product which represents a phase error between the color subcarrier signal and the reference clock. A voltage controlled oscillator is responsive to this phase error for generating the sample clock.

Abstract: The present invention is a system for inexpensive phase coherent subcarrier generation. The subcarrier sequence has a fairly short periodicity (two lines), allowing a relatively short lookup table to hold coded values precisely representing the sampled subcarrier. A variety of modulation techniques may be employed to minimize the error between the reconstructed subcarrier sine wave and an "ideal" subcarrier sine wave. The SCH phase may be easily varied by using a different table of subcarrier sine wave values.

Abstract: The object of the present invention is to use signal decoding circuits for a first generation EDTV signal and a second generation EDTV signal in common and to suppress an increase of circuit scale.An EDTV signal decoding apparatus of the present invention is constructed with a cascade connection of a first A/D converter, a first signal processing circuit, a first D/A converter, a second A/D converter, a second signal processing circuit and a second D/A converter. The first group composed of the first A/D converter, the first signal processing circuit and the first D/A converter are driven by a clock signal synchronizing with a color burst signal. The second group composed of the second A/D converter, the second signal processing circuit and the second D/A converter are driven by a clock signal synchronizing with a horizontal sync signal.

Abstract: A digital time base corrector which can perfectly eliminate residual errors. A sync clock signal whose phase is synchronized with a time base fluctuation included in a reproduction video signal is formed in accordance with at least one of the horizontal sync signal and the color burst signal which are separated from a reproduction video signal. The sync clock signal is phase-modulated in accordance with a burst error signal indicative of the time base fluctuation of the color burst signal in a period of time other than the generating period of time of at least the color burst signal in the reproduction video signal, thereby obtaining a write clock signal of the image memory.

Abstract: Signal processors for permitting the transparent, simultaneous transmission and reception of a data signal in the video bandwidth is disclosed. The signal processor in the transmitter rasterizes the data at the horizontal scanning rate and modulates the data with a data carrier at a non-integral multiple of the horizontal scanning rate to obtain frequency interleaving. The data is transmitted during the active video portion of each video line.

Abstract: A digital oscillator including an integrator for cumulatively integrating a specified signal and a controller responsive to a control signal for maintaining the output frequency of the integrator within a limit corresponding to the amplitude of the control signal.

Abstract: A method and circuit for preventing the deterioration of picture quality in a video processor is disclosed in which, when an input color video signal is input, a clock signal for a combfilter is locked with a phase-locked loop (PLL) by a burst signal and when a monochrome video signal without the burst signal is input, the clock signal is locked by the output (quasi-burst signal) of a voltage-controlled oscillator of the PLL circuit, before the lapse of one horizontal period, so that the clock signal is constantly locked by a multiple (4 fsc) of the burst signal regardless of the presence or absence of the burst signal of the input video signal. According to a color/mono signal discriminating result, either the burst signal or the quasi-burst signal is selected as a reference signal so that the reference signal is locked to provide a clock signal having a constant phase and frequency, thereby preventing aliasing due to clock variations when the monochrome signal is input and thus improving picture quality.

Abstract: A low range chroma signal reproduced from a recording medium is converted in the frequency by a frequency converter to obtain an original carrier chroma signal, then the carrier chroma signal is passed through a comb filter for removing a crosstalk and is output further through a phase shifting circuit, a burst signal of the phase shifting output is compared in the phase with a reference signal, the phase comparing output is smoothed by a filter, is then fed to a controlling terminal of a variable oscillator to control the oscillating frequency and is fed to a controlling terminal of the above mentioned phase shifting circuit to control the phase shifting amount. In this formation, a sub-APC loop including no comb filter is superimposed on a conventional APC loop and a response can be made until a high frequency. A color irregularity in a high frequency range (high range phase fluctuation of a carrier chroma signal) which has not been able to be removed can be reduced.