Abstract: Disclosed is a video signal output circuit including: a clamp circuit; a first differential amplifying circuit; a dividing circuit; and an offset circuit which adds or subtracts a predetermined offset voltage to or from a bias voltage, a reference voltage, or a base reference voltage generated by the dividing circuit so as to supply an offset voltage added/subtracted voltage to the clamp circuit or the first differential amplifying circuit, wherein the offset circuit includes a pnp bipolar transistor and an npn bipolar transistor, and outputs a difference voltage corresponding to a difference between a base-emitter voltage of the pnp bipolar transistor and a base-emitter voltage of the npn bipolar transistor.

Abstract: In a semiconductor integrated circuit arranged to perform sag compensation for a video signal, an operational amplifier includes a non-inverted input terminal, an inverted input terminal, and an output terminal, in which a video signal is input to the non-inverted input terminal. A first resistor includes a first end connected to the inverted input terminal and a second end being grounded. The output terminal is connected to a first external terminal and the inverted input terminal is connected to a second external terminal. A second resistor includes a first end connected to the output terminal and a second end connected to the inverted input terminal. A first capacitor is disposed between the first external terminal and the second external terminal and connected in parallel to the second resistor, and the second resistor has a resistance value determined based on a capacitance value of the first capacitor.

Abstract: A display apparatus includes a signal input unit through which an image signal is input, the image signal comprising a synchronization signal and an active signal; an adjustment signal generating unit that generates an adjustment signal; a signal processing unit that receives the adjustment signal and adjusts the image signal based on the received adjustment signal; and a controller which analyzes the input signal and controls the adjustment signal generating unit to change characteristics of the adjustment signal if the adjustment signal does not lie within a blanking interval between the synchronization signal and the active signal. With this configuration, even when an image signal having a reduced blanking interval between the synchronization signal and the active signal is input, the adjustment signal can be generated within the blanking interval of the image signal, not within the active signal interval.

Abstract: TV settings such as brightness can be established by sending from a TV signals from an ambient light sensor to a network server, with the network server establishing settings such as brightness in response for a program being played on the TV.

Abstract: The invention relates to an image processing chip and related method. The image processing chip includes a pin for receiving a composite signal; a synchronization signal detecting circuit, coupled to the pin, for extracting a synchronization signal from the composite signal; a clamping circuit, coupled to the pin, for adjusting a voltage level of the composite signal according to the synchronization signal; and an analog to digital converter, coupled to the pin, for generating a video signal by sampling the composite signal.

Abstract: Average picture level (APL) of a display and, in examples, histogram information is used to dynamically adjust the display contrast, or “gamma”, using an exponential function. APL can also be used for DC transmission adjustment and black/white stretch.

Abstract: An image correction circuit capable of preventing a loss of gray levels in a luminance region at the time of the direct current level conversion of a luminance signal to improve the quality of a displayed image. The image correction circuit detects an average peak level of input image data in each image frame, and corrects the input image data to lower the luminance of input image data in an intermediate luminance region according to the average peak level while reducing the luminance of input image data at a predetermined rate in at least of a low luminance region.

Abstract: An image signal processing apparatus includes a clamp circuit that clamps an image signal having a horizontal synchronization signal, an optical black level period representing an optical black level, and an effective signal period representing an image signal for one horizontal line so as to clamp a value offset from the image signal on the basis of a first reference value during the optical black level period and to clamp the image signal on the basis of a second reference value different from the first reference value during the effective signal period, and a level computation circuit that determines the second reference value on the basis of a signal level clamped during the optical black level period.

Abstract: A Sync On Green signal detection circuit includes a clamping circuit for clamping a voltage of a video graphics signal within a default range and then outputting a clamped input signal; a first PGA (programmable gain amplifier) for receiving and amplifying the clamped input signal by a first gain to generate a first gain signal; a first low-pass filter for receiving the first gain signal and then generating a first filtered signal; a second PGA for receiving and amplifying the clamped input signal by a second gain to generate a second gain signal, wherein the second gain is different from the first gain; a second low-pass filter for receiving the second gain signal and then generating a second filtered signal; a programmable voltage shifter for receiving and adjusting the first filtered signal and then outputting a level shifted signal; and a comparator for receiving the level shifted signal and the second filtered signal and then generating a comparison signal as a SOG signal.

Abstract: A slice level adjustment unit for performing adjustment of a slice level with respect to a signal whose transmission is started at a predetermined time, includes a clock portion for measuring the current time, and performs a first adjustment of the slice level when the clock portion measures substantially the predetermined time and also performs a second adjustment when the clock portion measures a readjustment standby time past the predetermined time.

Abstract: A clamping circuit including: a subtracter for subtracting a clamping correction voltage from an input analog voltage signal; A/D converter for converting an analog voltage signal from the subtracter into a digital voltage signal of M bits; a potential difference detection circuit for detecting a potential difference between a digital voltage signal outputted from the A/D converter and a previously set clamping voltage; D/A converter for converting a digital signal of N (N<M) bits within the digital signal of M bits representing a potential difference outputted from the potential difference detection circuit into an analog signal; an adjusting voltage generation circuit for generating an adjusting voltage based on a potential difference outputted from the potential difference detection circuit and a threshold voltage set with respect to the potential difference; and an adder for adding together an output from the D/A converter and an adjusting voltage outputted from the adjusting voltage generation circuit

Abstract: A dc level control method for holding a dc level of a clamp portion in an electric signal to be a prescribed value is disclosed, wherein the method comprises the steps of: comparing a dc level of a sampling interval in said electric signal with a predetermined reference value to obtain a difference between said dc level and said reference value using an A/D converting section for dc level comparison which has a lower bit resolution than an A/D converting section for digital signal processing of said electric signal; and feeding back a clamp signal to said electric signal so that said obtained difference between said dc level and said reference value substantially becomes zero. This method is suitable for applying to a signal processing system for a solid state imaging apparatus.

Abstract: An automatic clamping analog-to-digital converter (A/D converter) is provided, which includes an A/D converter, a switch, a comparator, a bidirectional counter, and a digital-to-analog converter (D/A converter). Wherein, the A/D converter receives an analog signal from a node, and then converts the analog signal into a digital signal according to a DC offset level. The switch is coupled between the node and a fixed voltage level, and is turned on or off according to a clamping signal. The comparator outputs a compare signal according to a comparison result between the digital signal and an offset value. The bidirectional counter outputs a count, and increases or decreases the count according to the compare signal. The D/A converter converts the count into the DC offset level and provides the DC offset level to the A/D converter.

Abstract: An imaging sensor pixel array includes a semiconductor substrate, a plurality of active pixels and at least one black reference pixel. The plurality of active pixels are disposed in the semiconductor substrate for capturing an image. Each of the active pixels includes a first region for receiving light including a p-n junction for accumulating an image charge and active pixel circuitry coupled to the first region to readout the image charge. The black reference pixel is also disposed within the semiconductor substrate for generating a black level reference value. The black reference pixel includes a second region for receiving light without a p-n junction and black pixel circuitry coupled to the photodiode region without the p-n junction to readout a black level reference signal.

Abstract: A video output circuit that is operated at a low power supply voltage and capable of achieving reduced power consumption with a simple circuit configuration and a semiconductor integrated circuit incorporating the same are provided. The video signal output circuit includes a video signal input terminal 1, a clamp circuit 3 that is connected to the video signal input terminal 1, a voltage-current conversion circuit 4 that is connected to the clamp circuit 3, a current amplifier circuit 5 that is connected to the voltage-current conversion circuit 4 and a video signal output terminal 6 that is connected to the current amplifier circuit 5, wherein a resistor 8 is connected between the video signal output terminal 6 and a ground, a transmission line 9 is connected with the video signal output terminal 6, and a load resistor 10 having an equal resistance to the resistor 8 is connected between another end of the transmission line 9 and a ground. The clamp circuit 3 fixes a negative signal voltage.

Abstract: A level clamping control circuit and associated level clamping control method are provided. The level clamping control circuit includes a reference level estimator, a subtractor, a clamping computation circuit, a dithering circuit, and a digital-to-analog converter (DAC). The reference level estimator estimates a reference level of the input signal. The subtractor computes a difference between the reference level and a desired reference level to output a difference signal. The clamping computation circuit generates a first control value according to the difference signal. The dithering circuit dithers the first control value to alternately output a plurality of second control values. Finally, the DAC respectively utilizes the second control values to charge or discharge a capacitor to adjust the reference level of the input signal.

Abstract: The video signal processing circuit has a clamp circuit for clamping a composite video signal including a copy guard signal with amplitude of from white to black as well as a pseudo horizontal synchronization signal, a brilliant signal, and a synchronization signal. The circuit also has a synchronization signal separation circuit, which separates the synchronization signal from the composite video signal and a synchronization signal discrimination circuit, which identifies if the synchronization signal coming from the synchronization signal separation circuit has the same cycle as that of a horizontal synchronization signal, and which blocks the signal with the cycle shorter than the cycle of the horizontal synchronization signal, letting only the signal with the cycle of the horizontal synchronization signal pass.

Abstract: An amplifier which amplifies an input signal, wherein an amplified signal which varies with a ground voltage as a center is obtained at an output of the amplifier using a positive power supply and a negative power supply. With this configuration, an amplified signal which varies with the ground voltage as a center can be obtained at the output of the amplifier so that a direct current cutting capacitor is no longer necessary.

Abstract: A clamping circuit for restoring the DC level of video input signals. The clamping circuit comprises a coupling capacitor, a latch, a logic element, a charge switch, and a constant current source. The latch is coupled to the coupling capacitor to receive a video input signal therethrough and comprises a bias current source for generating first and second output signals in response to the AC-coupled signal and a reference voltage. The logic element receives the first and second output signals, generating a charging control signal to the charge switch. The charge switch, responsive to the charging control signal, is turned on to direct the current of the bias current source to the coupling capacitor, raising the level of the AC-coupled signal. Meanwhile, the constant current source continuously discharges the coupling capacitor slowly.

Abstract: A method for deriving a synchronisation signal (35) from a video signal comprises tracking the blanking level (107) of the video signal with first and second slice level signals (26, 27) and tracking the sync tip level (110) of the horizontal sync signal (109) of the video signal with third and fourth slice level signals (28,29) for determining the blanking level (107) and the sync tip level (110). A value for an intermediate slice level signal (30) is computed from the first, second, third and fourth slice level signals (26, 27, 28, 29) so that the value of the intermediate slice level signal (30) lies approximately halfway between the blanking level (107) and the sync tip level (110).

Abstract: A dc level control method for holding a dc level of a clamp portion in an electric signal to be a prescribed value is disclosed, wherein the method comprises the steps of: comparing a dc level of a sampling interval in said electric signal with a predetermined reference value to obtain a difference between said dc level and said reference value using an A/D converting section for dc level comparison which has a lower bit resolution than an A/D converting section for digital signal processing of said electric signal; and feeding back a clamp signal to said electric signal so that said obtained difference between said dc level and said reference value substantially becomes zero. This method is suitable for applying to a signal processing system for a solid state imaging apparatus.

Abstract: Digital dc restore methods and apparatus to restore the DC component of an analog waveform to a quantized reference value level at a given temporal point on a waveform, prior to an ADC. This may used to establish the relationship between the full scale digital value out of the ADC and the waveform being digitized. For a video signal, the Digital Value of Black, is compared with the value on the back porch of the video signal. The difference is converted to the analog domain by a DAC clocked at the Temporal Point to provide a sample and hold function. An amplifier compares the difference, mapped to one half full scale digital, to an analog common mode voltage for the ADC, removing any error due to the difference between them. Other applications include correlated double sampling of contact image sensors to remove Dark Current Offset.

Abstract: The present invention provides an on-screen display apparatus which can eliminate variations in the DC level at a time when an input chroma signal and an OSD chroma signal are switched, and prevent an erroneous display of color. The on-screen display apparatus of the present invention comprises a voltage holder which holds a voltage value at a time when the input chroma signal is a null signal, and an output switch which outputs the voltage value held by the voltage holder in an OSD period and outputs the input chroma signal other than the OSD period.

Abstract: An apparatus, system and method for clamping a video signal input to a coupling capacitor (215) for providing a clamping voltage. A charging current is applied to the capacitor (215) via an amplifier (225) having a first input (227) coupled with the capacitor output and a second input (226) coupled to a reference potential, the amplifier (225) is responsive to the capacitor output signal and the reference potential for providing the charging current to the capacitor (215). The current has a linearly varying magnitude which is proportional to a difference between the capacitor output and the reference potential.

Abstract: The invention teaches a method, means and apparatus for clamping a back porch interval of a video signal including clamping a sync-tip level of said video signal to a variable reference voltage, comparing a back-porch voltage level of the sync-tip clamped video signal to a predetermined reference voltage, generating an error signal representative of the difference between the back-porch voltage level and the predetermined reference voltage, and adjusting the variable reference voltage in response to the error signal such that the error signal is minimized.

Abstract: The keyed clamp circuit of this invention has the clamp circuit for clamping the video signal including the equalizing pulse and the vertical synchronization signal based on the clamp pulse, the synchronization signal separation circuit for separating the synchronization signal from the video signal clamped by the clamp circuit, and the clamp pulse generation circuit for generating the clamp pulse based on the synchronization signal from the synchronization signal separation circuit. The clamp pulse for the equaling pulse with a pulse width, which is shorter during the equalizing pulse period compared to the pulse width during the vertical synchronization signal period, is generated. The clamp pulse can be generated based on the equalizing pulse and the vertical synchronization signal, performing the keyed clamping on the video signal even during the blanking pulse period.

Abstract: A method and apparatus for controlling the brightness of an image processing device to improve a brightness characteristic of an image signal, by reducing a pedestal voltage range and correspondingly expanding a brightness control voltage range in a highlight mode. The brightness control method includes the operations of determining whether a highlight mode is enabled; and if the highlight mode is enabled, reducing a pedestal voltage range by a first predetermined value and expanding a brightness control voltage range by a second predetermined value. The pedestal driving voltage and the brightness control voltage can be reciprocally controlled without modifications to a circuit having limited amplification, and the brightness can be improved without saturating an image in a highlight mode.

Abstract: A clamp control circuit outputs a clamp control signal after a delay of a predetermined time if a digital video signal is detected. A sampling circuit that extracts sampling data of a pedestal level from a luminance corrected signal based on a clamp pulse at a timing of the back porch. A data averaging circuit calculates an average of the sampling data of the pedestal level. A data holding circuit holds a difference between the average and a digital signal processing reference level when the clamp control signal is output and also when the clamp control signal is not output. A level correction circuit corrects a level of the luminance signal based on the difference held by the data holding circuit and outputs the corrected luminance signal.

Abstract: An imaging device uses a solid state imaging element, during multi-field accumulation to prevent shading and oscillatory phenomena such as repeated black and white patterns. A signal is supplied from a timing signal generation circuit to switches, and controls the ON/OFF operation. During the H period of the signal, the switch is closed, and the output value of an amplifier is input to a capacitor. During the L period of the signal, the switch is opened, and the average value of the output of the amplifier is maintained in the capacitor. During the H period, the switch is open, while during the L period, the switch is in the ON state. At this time, the level of the capacitor C2 and the output of the amplifier are input to an amplifier, and their difference is amplified and supplied to a capacitor C3 via the switch.

Abstract: An input stage for a video receiver includes a variable gain amplifier, an analog-to-digital converter for sampling a video signal and a digital processing unit for processing digital samples of the video signal. An analog regulating circuit sets an input potential at an input of the variable gain amplifier. A differential architecture is used for the variable gain amplifier and the digital analog converter. A conversion circuit between an input coupling capacitor and the variable gain amplifier allows generating the video signal on two channels in antiphase, which are centered on the common mode voltage. Such differential architecture allows reducing the amplitude of analog signals, which is particularly advantageous in the case of a low voltage supply delivering a few volts. In addition, linearity of the video signal processing is enhanced.

Abstract: In order to reduce a circuit scale such as a brightness adjustment circuit or the number of pins in an IC chip, in the brightness adjustment circuit, a brightness adjusted video signal (internal video signal) output from an analog signal synthesis circuit or a D/A converter is input to one input terminal of a switch and a sample/hold circuit. The sample/hold circuit holds a voltage of a level in accordance with the pedestal level of the internal video signal at a timing in accordance with a sampling pulse in synchronization with the internal video signal. A clamp circuit clamps the pedestal level of an external video signal in accordance with a clamp pulse, using the voltage held by the sample/hold circuit as the reference voltage, and input it to the other input terminal. The output terminal of the switch is connected to an amplifier.

Abstract: A programmable gain amplifier having three separately programmable amplifiers. A programmable transconductance amplifier is followed by a programmable transimpedance amplifier, then a programmable switched capacitor amplifier. In one embodiment, this programmable gain amplifier is implemented in an analog front-end (AFE) circuit. One AFE embodiment provides a coarse pre-gain offset a black reference level sampler, and a fine post-gain offset in the programmable switched capacitor amplifier. In one embodiment, an ADC reference is sampled, and is subtracted directly from the video signal in the switched capacitor amplifier so that the zero level of the video signal is made to correspond to the zero level of the ADC.

Abstract: The object of the invention is offering an external output video signal processor, which does not need coupling capacitor or clamping circuit. A system controller outputs a video signal by which the sync. tip level and the pedestal level were fixed to a predetermined value. It was considered as an external output video signal processor which carries out direct input of the video signal output to the video signal processing circuit from the system controller, and is characterized by providing a level shift circuit which adjusts the level and is sent to said latter part processing circuit.

Abstract: An image display system includes a memory for storing at least one scanning line of an inputted video signal of the interlace scanning system, and reading means for repeating to read the video signal of one scanning line from the memory at a speed which is n (n is an integer of 2 or more) times of the writing speed of the video signal for the memory for a horizontal scanning period which is 1/n of the writing period and to stop reading for a horizontal scanning period of the remaining (n−1)/n for each scanning line of one field which is sequentially inputted and reading each scanning line so that the continuous fields interpolate the period of stopping of reading from the memory each other.

Abstract: An AGC circuit (70) amplifies a video signal according to again value output from again setting circuit (56). A clamp circuit (72) performs clamping of the direct current level of an output signal from the AGC circuit (70) at a clamp ability level according to a time constant set by a clamp time constant setting circuit (58). The clamp time constant setting circuit (58) receives input of the gain value generated by the gain setting circuit (56). A comparator circuit (120) compares the received gain value to a reference value, and, when the gain value exceeds the reference value, outputs a relatively large time constant. The clamp ability level of the clamp circuit (72) is controlled according to this time constant. In this manner, when the gain value is large, gradual clamping can be executed so as to minimize the influence of noise components superimposed on the direct current level, thereby suppressing transverse noise.

Abstract: A video signal processor reduces the deterioration of image quality due to the superposition of noise on a sync signal included in a luminance signal. A frequency discriminator outputs a first error signal if a ratio of the frequency of a frequency-modulated signal during a sync-signal interval to the frequency of a reference frequency signal is smaller than a predetermined ratio. Alternatively, the discriminator outputs a second error signal if the ratio is greater than the predetermined ratio. If the first error signal has been input to a frequency controller a preset number of times or more during an interval before the second error signal is input thereto, the controller instructs a frequency modulator to increase the frequency of the frequency-modulated signal.

Abstract: A low pass filter smooths a voltage corresponding to a least significant bit of a digital image signal outputted from an A/D convertor, and outputs the smoothed voltage to a sample-and-hold circuit. In the sample-and-hold circuit, a sample-hold-pulse is added during an optical black period, so that a voltage of the least significant bit of only a black level is extracted and outputted to a clamp level adjusting circuit. In the clamp level adjusting circuit, when the voltage inputted from the sample-and-hold circuit is higher 0 volts, a voltage, corresponding to a standard voltage from which the inputted voltage is subtracted by a differential amplifier, is outputted to a clamp circuit, and when the inputted voltage is 0 volts, the clamp voltage is pulled up by a pull-up resistance.

Abstract: An input stage for a video receiver includes a variable gain amplifier, an analog-to-digital converter for sampling a video signal and a digital processing unit for processing digital samples of the video signal. An analog regulating circuit sets an input potential at an input of the variable gain amplifier. A differential architecture is used for the variable gain amplifier and the digital analog converter. A conversion circuit between an input coupling capacitor and the variable gain amplifier allows generating the video signal on two channels in antiphase, which are centered on the common mode voltage. Such differential architecture allows reducing the amplitude of analog signals, which is particularly advantageous in the case of a low voltage supply delivering a few volts. In addition, linearity of the video signal processing is enhanced.

Abstract: An illumination intensity correcting circuit including a curve fitting circuit formed by differential amplifier circuits and a load resistor, wherein the amplification factor of the curve fitting circuit is changed before and after each breakpoint voltage, the reference voltages of the differential amplifier circuits are set so that at least two breakpoint voltages are arranged in the range of a voltage of a video signal, and the amplification factors of the differential amplifier circuits are set so that the amplification factor of the curve fitting circuit in the range of the signal voltage inside of the two breakpoint voltages is smaller than the amplification factor outside of the two breakpoint voltages.

Abstract: In order to reduce a circuit scale such as a brightness adjustment circuit or the number of pins in an IC chip, in the brightness adjustment circuit, a brightness adjusted video signal (internal video signal) output from an analog signal synthesis circuit or a D/A converter is input to one input terminal of a switch and a sample/hold circuit. The sample/hold circuit holds a voltage of a level in accordance with the pedestal level of the internal video signal at a timing in accordance with a sampling pulse in synchronization with the internal video signal. A clamp circuit clamps the pedestal level of an external video signal in accordance with a clamp pulse, using the voltage held by the sample/hold circuit as the reference voltage, and input it to the other input terminal. The output terminal of the switch is connected to an amplifier.

Abstract: A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.

Abstract: A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.

Abstract: A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.

Abstract: A video signal processing apparatus having first and second analog/digital converters for converting imputted analog luminance and chrominance component signals into digital luminance and chrominance component signal. Frequency band limiting filters, disposed on a pre-stage of the first and second analog/digital converters, limit a frequency band of the analog luminance and chrominance component signals, the chrominance component signal frequency band limiting filter having a group delay characteristic different from a group delay characteristic of the luminance component signal frequency band limiting filter by a predetermined delay time. A time adjustment circuit adjusts the timing of the digital chrominance signal to match with the digital luminance signal.

Abstract: A front end signal processing method and apparatus for processing a signal from an image sensor are provided for readily clamping a black level, improving the manufacturing yield, and reducing the power consumption. A luminance detector/digitizer receives a sensor output signal from an image sensor, detects luminance information included in the sensor output signal, and generates a digital luminance signal representative of the detected luminance information. A digital processor receives the digital luminance signal, and multiplies the digital luminance signal by a predetermined gain code to generate the multiplication result as a front end processed signal output. An optical black clamp receives the digital luminance signal from the luminance signal detector/digitizer and supplies a feedback signal produced from the digital luminance signal to the luminance signal detector/digitizer to clamp a black level of the luminance signal to a constant value.

Abstract: There is provided a device for controlling the brightness of a monitor screen to prevent the edge of the screen from appearing darker than the center of the screen by setting a black level signal scanned to the edge of the screen to be greater than a black level signal scanned to the center of the screen. The device includes a parabolic signal generator for generating a parabolic signal. A video output signal generator receives a video input signal in which an image is carried on a black level signal voltage and a brightness control voltage for controlling the brightness of the screen. The video output signal generator generates a first video output signal having a black level signal adjusted by the brightness control voltage. A signal synthesizer receives the first video output signal and the parabolic signal and generates therefrom a second video output signal in which the parabolic signal is added to the first video output signal.

Abstract: A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.

Abstract: Cut-off control circuits implementing DC-coupling and AC-coupling to CRT cathodes can employ the same preamplifier integrated circuits with few additional components. The preamplifier includes a switching unit for receiving control data, generating a control signal according to control data, and outputting the control signal internally or externally. The switching unit provides a control signal internally to an amplification circuit, when the preamplifier operates in a cut-off control circuit having a DC-coupling to a CRT. With a DC coupling the amplification circuit controls a DC bias applied to a CRT cathode. The switching unit provides a bus control signal externally to a bias circuit, when the preamplifier operates in a cut-off control circuit having an AC-coupling to a CRT.

Abstract: A video decoder circuit is provided with automatic AGC bias voltage calibration. The video decoder circuit has an input for receiving a video signal that is capacitively coupled to an analog front-end circuit. The decoder circuit includes a microprocessor-based control circuit coupled to the analog front-end circuit. The control circuit includes a bias circuit, a gain interface circuit for changing the amplitude of the video signal prior to filtering in a filter circuit, an offset circuit for changing the DC-level shift of the video signal, and a switching circuit for switching into a calibration mode by bypassing the filter circuit and connecting the gain interface circuit directly to an analog-to-digital conversion circuit of the analog front-end circuit.

Abstract: The standard brightness region is displayed with input values of zero. The comparison brightness region is displayed with an input value which is variable in the range of 0 to 255. The standard brightness and comparison brightness regions are displayed next to each other in the display. The input value is changed from zero. A first black point is determined as an input value which causes the comparison brightness region to first appear distinguishable from the black regions of the standard brightness regions. Then, the input value is changed from 255. A second black point is determined as an input value which causes the comparison brightness region to first appear indistinguishable from the black regions of the standard brightness regions. Then, a black point is calculated as an average of the first and second black points.