Abstract: Disclosed herein are related to a system and a method for synchronizing signal processing on audio channels. In one aspect, a system includes processors, each including an audio data input configured to receive audio data from multiple audio sources. In one aspect, each processor includes audio channels coupled to the audio data input, where each audio channel includes a corresponding processing chain configured to convert a sample rate of audio data from a corresponding audio source. Each processor may include a synchronization pulse generator configured to generate a corresponding synchronization pulse for each processing chain in response to a trigger pulse. The synchronization pulse generator may include a counter configured to generate an output having a phase based on a programmable initial condition of the counter, where the synchronization pulse for each processing chain is based on the counter output and a phase register value of the corresponding processing chain.

Abstract: The present invention discloses a signal skew measurement method for integrated circuit, a medium, and an electronic device. The method comprises: by a test machine, acquiring a first signal and a second signal output by an IC, respectively performing under-sampling on the first and second signals to obtain a first sampled signal and a second sampled signal; respectively performing digital conversion on the first and second sampled signals based on a preset threshold voltage to obtain a first digital signal and a second digital signal; respectively performing convolution on the first and second digital signals using a preset pulse signal to obtain a first comparison signal and a second comparison signal; and calculating a skew between the first and second comparison signals to obtain a reference skew, and determining a skew between the first and second signals according to the reference skew.

Abstract: Disclosed herein are device, method, and computer program product embodiments for synchronizing playback of audio and/or video content. An embodiment operates by a first device in concert with a second device to collectively select a preferred synchronization mechanism over a third device's default synchronization mechanism such that the third device serves as a session leader. The preferred synchronization mechanism's selection is in accordance with a predetermined prioritized synchronization list comprising the default and preferred synchronization-mechanisms and a virtual clock generated from a timing of an audio codec used for streaming the audio and/or video content. The session leader's default synchronization mechanism has a lower level of priority than the first and second devices' preferred synchronization mechanism. The preferred synchronization mechanism provides a more precise level of synchronization for playback of the audio and/or video content than the default synchronization mechanism.

Abstract: Systems and methods are disclosed for applying multi-stage multiple input single output (MISO) circuits for fast adaptation. An apparatus may comprise a first reader and a second reader configured to simultaneously read from a single track of a data storage medium, a MISO circuit. The MISO circuit may include a first stage filter having a first number of taps and configured to filter signal samples received from the first reader and the second reader and produce first filtered samples. The MISO circuit may also include a second stage filter having a second number of taps greater than the first number, and be configured to receive the first filtered samples corresponding to the first reader and the second reader from the first filter stage, filter the first filtered samples to produce second filtered samples, and combine the second filtered samples to produce a combined sample output.

Abstract: Referenceless clock and data recovery circuits are described that operate to align the clock/data strobe with each data eye to achieve a low bit error rate. The appropriate frequency and phase to be used is determined by an edge counter based frequency error detector and a phase error detector.

Abstract: A skew compensation apparatus and method. In an optical system that uses optical signals, skew may be generated as the optical signals are processed from an input optical signal to at least two electrical signals representative of the phase-differentiated optical signals. A compensation of the skew is provided by including an optical delay line in the path of the optical signal that does not suffer the skew (e.g., that serves as the time base for the skew measurement). The optical delay line introduces a delay Tskew equal to the delay suffered by the optical signal that is not taken as the time base. The two signals are thereby corrected for skew.

Abstract: A transport monitoring control device includes a transport unit configured to transport a recording medium while nipping the recording medium, a driving unit configured to drive the transport unit, a detector configured to detect a waveform related to a load of the driving unit when the recording medium enters the transport unit or is discharged from the transport unit, and a determining unit configured to determine whether the recording medium is skewed with respect to the transport unit, based on a waveform width at a height obtained by multiplying a peak value of the waveform by a predetermined coefficient.

Abstract: Systems, methods, and apparatuses are described for deskewing between multiple lane groups of deskewed data streams. Multiple distinct and deskewed lane groups can be aligned by utilizing an inter-group synchronized set of counters. The counters supply a way to measure the time delta (counter difference) in clocks between the multiple streams. Using this delta, one or more streams can be stalled to align the multiple streams. The counter values are communicated between the multiple groups in a way that they align to set data stream markers. These fixed markers and the breaking up of the counters in relation to the periodicity of the markers allows for a robust way to compare the multiple streams and calculate an accurate time delta.

Abstract: An environmentally-friendly vehicle sound generator control apparatus. The apparatus includes a sound playback unit including a sound comparison unit for comparing a frequency band-specific reference sound level data with an extracted plurality of frequency band-specific sound data for each frequency band in response to a comparison control signal of a control unit, a sound control unit for controlling a pitch or a volume of a plurality of frequency band-specific sample sound source data to form a plurality of frequency band-specific sample control sound source data if the extracted plurality of frequency band-specific sound data is smaller than the frequency band-specific reference sound level data, and a sound mixing unit for mixing the plurality of frequency band-specific sample control sound source data and transferring the mixed plurality of frequency band-specific sample control sound source data to the sound output unit so that a pedestrian's vehicle recognition sound can be outputted.

Abstract: A time code display device includes a time code extraction unit that extracts a left image time code from a left image signal that constitutes a stereoscopic image and a right image time code from a right image signal that constitutes the stereoscopic image; a time code comparison unit that compares the left image time code with the right image time code and outputs a comparison result including information on agreement or disagreement between the left and right image time codes; and a display determination unit that determines to display the left and right image time codes in the same manner when the comparison result indicates agreement therebetween, determines to display the left and right image time codes in different manners when the comparison result indicates disagreement therebetween, and displays the left and right image time codes on a display unit.

Abstract: One embodiment relates to a method of determining an arrival time of a data packet which has data striped across a plurality of lanes of a multi-lane link. Word arrival times for a subset of the words of the data packet are determined, each word arrival time corresponding to an arrival time of a word of the data packet at an individual lane of the multi-lane link. The arrival time of the data packet is determined using the word arrival times for the subset of words. Another embodiment relates to a method of determining an arrival time of a data packet which uses a measure of average fullness for a set of the FIFO buffers. Other embodiments and features are also disclosed.

Abstract: A data storage system identifies analog-to-digital conversion samples with amplitude below a certain threshold. Remaining samples are grouped according to phase into one or more quadrants. A multi-coordinate with overlapping quadrants is used to further differentiate sample points. The system then computes an average phase for zero phase start estimation.

Abstract: One embodiment relates to a method of determining an arrival time of a data packet which has data striped across a plurality of lanes of a multi-lane link. Word arrival times for the words of the data packet are determined, each word arrival time corresponding to an arrival time of a word of the data packet at an individual lane of the multi-lane link. The arrival time of the data packet is determined using a predetermined function of the word arrival times. Another embodiment relates to a receiver circuit that determines an arrival time of a data packet which has data striped across a plurality of lanes of a multi-lane link. Other embodiments and features are also disclosed.

Abstract: Inter-track interference cancelation is disclosed, including: receiving an input sequence of samples associated with a track on magnetic storage; using a processor to generate inter-track interference (ITI) data associated with a first side track including by performing a correlation between the input sequence of samples and a sequence of data associated with the first side track.

Abstract: A disk drive is disclosed comprising a head actuated over a disk, wherein data is written to the disk comprising a first periodic pattern, a payload, and a second periodic pattern. The data is first read from the disk to generate a first read signal, and the first read signal is sampled asynchronously to generate first asynchronous signal samples. The first asynchronous signal samples representing the first periodic pattern are processed to measure a first phase, and the first asynchronous signal samples representing the second periodic pattern are processed to measure a second phase. A first phase error is generated based on a difference between the first phase and the second phase. The first asynchronous signal samples representing the payload are adjusted in response to the first phase error to generate first adjusted asynchronous signal samples.

Abstract: Systems, methods, apparatus, and techniques are provided for controlling synchronization of a write clock. A frequency offset is estimated based, at least partially, on a location of the servo synchronization marker to produce the frequency offset estimate. A phase correction value and a frequency correction value associated with the write clock are obtained, and a data clock timing control signal is produced based on the frequency offset estimate, the phase correction value, and the frequency correction value. The data clock timing control signal is applied to a phase interpolator to modify a phase of the write clock.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to data processing using distortion-correction loops with saturation-based assistance.

Abstract: An assembly and method to determine adjacent track coherence is disclosed. The assembly includes coherence circuitry configured to receive phase and frequency offsets from timing recovery circuitry and determine an inter-track phase and frequency coherence between the encoded data on a first track and the encoded data on a second track adjacent to the first track utilizing the frequency and phase offsets from the timing recovery circuitry for the output signals corresponding to the first and second tracks.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide clock generation systems that include: a first clock multiplier circuit, a second clock multiplier circuit, a modulus accumulator circuit, and a data clock phase control circuit. The first clock multiplier circuit is operable to multiply a reference clock by a first multiplier to yield a first domain clock, and the second clock multiplier circuit is operable to multiply the reference clock by a second multiplier to yield a second domain clock. The modulus accumulator circuit is operable to yield a value indicating a fractional amount of the second domain clock that an edge of the second domain clock is offset from a trigger signal. The data clock phase control circuit is operable to phase shift the second domain clock by a phase amount corresponding to the fractional amount.

Abstract: A disk drive is disclosed comprising a head actuated over a disk comprising a sector including a periodic pattern and sector data. The sector is read with the head to generate a read signal which is sampled at a sampling frequency with a signal sampler to generate signal samples. The signal samples representing the periodic pattern are processed to measure a frequency induced phase error based on k? where k represents a signal sample index and ? is a fraction of 2?. The signal samples representing the sector data are processed to generate a data phase error. The data phase error is adjusted in response to the frequency induced phase error to generate an adjusted data phase error, and the signal sampler is controlled in response to the adjusted data phase error.

Abstract: Apparatus and methods are disclosed for decoding data stored on a data storage medium. A disclosed decoding method and decoder include a radial incoherence (RI) detector that increases the probability of detecting RI and improves the decoding performance in terms of the bit error rate of the decoded signal. RI is detected by comparing an input signal to the decoder against a RI threshold value and generating a RI-type signal. The RI detector may include a filter for filtering out noise and error in the RI-type signal, an adaptive threshold unit that adjusts the RI threshold value based upon the RI-type signal, a transition-based threshold unit that adjusts the RI threshold value based upon each transition in the input signal, or a path-based threshold unit that adjusts the RI threshold value based upon a best surviving path corresponding to the input signal, in combination or alone.

Abstract: According to an aspect of the present disclosure, a method includes: receiving a plurality of groups of one or more phase signals, each group of phase signals having a different phase relative to other groups of one or more phase signals; generating a plurality of interpolated phase shifted signals based on the plurality of groups of one or more phase signals, wherein the plurality of interpolated phase shifted signals do not have an associated common mode component; receiving data bits and precompensating each data bit in accordance with a given interpolated phase shifted signal; and selecting a precompensated data bit for output.

Abstract: Inter-track interference cancelation is disclosed, including: receiving an input sequence of samples associated with a track on magnetic storage; using a processor to generate inter-track interference (ITI) data associated with a first side track including by performing a correlation between the input sequence of samples and a sequence of data associated with the first side track.

Abstract: Various embodiments of the present invention provide systems and methods for locating a reference pattern on a storage medium. For example, various embodiments of the present invention provide systems for locating a reference pattern on a storage medium. Such systems include a sliding window phase calculator circuit, a delay circuit and a mark detector circuit.

Abstract: A receiving device may be configured to derive an oversampled dibit pulse response estimate using symbols sampled at substantially the read channel symbol rate of the receiving device. The receiving device may include a data acquisition circuit configured to digitize data derived from a memory medium, as well as a dibit pulse estimation circuit configured to estimate the oversampled dibit pulse response using symbols sampled at the read channel rate of the receiving device.

Abstract: A receiving device may be configured to derive an oversampled dibit pulse response estimate using symbols sampled at substantially the read channel symbol rate of the receiving device. The receiving device may include a data acquisition circuit configured to digitize data derived from a memory medium, a symbol timing loop and read circuit, as well as a dibit pulse estimation circuit configured to estimate the oversampled dibit pulse response using symbols sampled at the read channel rate of the receiving device without disturbing the symbol timing loop and read circuit.

Abstract: A method of writing data to and reading data from a storage medium includes cycle slip detection and correction. An LDPC matrix includes a first area for cycle slip detection and correction. The first area satisfies a set of conditions such that a cycle slip at a particular position creates a pattern of parity check errors indicative of the position and polarity of the cycle slip. Writing user data to the storage medium includes encoding the user data with parity data according to the LDPC matrix. Reading the user data and the parity data from the storage medium includes decoding the user data and the parity data according to the LDPC matrix. Decoding includes, upon detecting a pattern of parity check errors indicative of the position and polarity of a detected cycle slip, correcting the detected cycle slip.

Abstract: A device is provided that, in one implementation, includes interpolators to generate interpolated phase shifted signals, and a precompensation circuit to provide precompensated versions of data bits in accordance with the interpolated phase shifted signals. Each of the interpolators is assigned a bit pattern different from that assigned to remaining ones of the interpolators.

Abstract: Apparatus and methods are disclosed for decoding data stored on a data storage medium. A disclosed decoding method and decoder include a radial incoherence (RI) detector that increases the probability of detecting RI and improves the decoding performance in terms of the bit error rate of the decoded signal. RI is detected by comparing an input signal to the decoder against a RI threshold value and generating a RI-type signal. The RI detector may include a filter for filtering out noise and error in the RI-type signal, an adaptive threshold unit that adjusts the RI threshold value based upon the RI-type signal, a transition-based threshold unit that adjusts the RI threshold value based upon each transition in the input signal, or a path-based threshold unit that adjusts the RI threshold value based upon a best surviving path corresponding to the input signal, in combination or alone.

Abstract: According to one embodiment, a magnetic disk drive includes a magnetic disk to be subjected to perpendicular recording, a first pole core including a main pole configured to record signals on the magnetic disk, a first coil wound around the first pole core, a second pole core magnetically independent of the first pole core, tip ends of which are arranged on both sides of the main pole, a second coil wound around the second pole core, a read unit including an element configured to read data recorded on the magnetic disk, and a correction unit configured to correct a current phase difference between the first and second coils.

Abstract: Signal correction is performed by determining an offset error based at least in part on a first portion of a signal within a first amplitude range. The offset error is associated with error due to offset in the signal. An signal error, associated with error due to offset and magneto-resistive asymmetry (MRA) in the signal, is determined based at least in part on a second portion of the signal within a second amplitude range; the second amplitude range does not overlap with the first amplitude range. An MRA error is determined by removing the offset error from the signal error and the MRA error is removed from the signal.

Abstract: Apparatus and methods are disclosed for decoding data stored on a data storage medium. A disclosed decoding method and decoder include a radial incoherence (RI) detector that increases the probability of detecting RI and improves the decoding performance in terms of the bit error rate of the decoded signal. RI is detected by comparing an input signal to the decoder against a RI threshold value and generating a RI-type signal. The RI detector may include a filter for filtering out noise and error in the RI-type signal, an adaptive threshold unit that adjusts the RI threshold value based upon the RI-type signal, a transition-based threshold unit that adjusts the RI threshold value based upon each transition in the input signal, or a path-based threshold unit that adjusts the RI threshold value based upon a best surviving path corresponding to the input signal, in combination or alone.

Abstract: A method and apparatus for adapting an FIR equalizer in a hard disk drive read channel which determines again direction and/or a phase direction of an FIR response c of the FIR equalizer, and calculates a constraint so that the update does not change the FIR response in its gain and/or phase direction.

Abstract: A circuit for a high-density data recording channel includes a first data detector, a second data detector, one or more multiplexers and a sequence identifier. The first data detector generates a first data detector output, and the second data detector generates a second data detector output. The multiplexers change between a first mode and a second mode to alternately receive the first data detector output and the second data detector output. The sequence identifier receives a data sequence including at least one of a first data sequence, such as VFO data, and a second data sequence, such as random data. The second data sequence includes a greater number of signal levels than the first data sequence. The sequence identifier changes the multiplexers between the first mode and the second mode based on whether the data sequence is the first data sequence or the second data sequence. The data sequence includes a plurality of timing stages.

Abstract: A signal processing apparatus has a plurality of baseline wander correcting units, provided in a processing path in which a predetermined processing is performed on an input signal. At least one of the plurality of baseline wander correcting units includes a correction permission control unit that controls permission or rejection of correction, and baseline wander in the input signal is corrected sequentially by each of the plurality of baseline wander correcting units, based on a control of the correction permission control unit. The baseline wander correcting unit corrects the baseline wander by determining whether or not the baseline correction is to be effected or not, so that the wander of baseline can be efficiently corrected.

Abstract: A method includes estimating a phase difference between components of a position signal in a servo position estimation system, and correcting the phase difference of the components of the position signal to provide a phase-compensated position signal.

Abstract: Phase-error combination for a multi-channel data detection system with a phase locked loop for each channel, comprises receiving phase error information with respect to each channel; combination logic configured to combine the received phase error information and generate a combined phase error; and a phase-error output configured to apply the combined phase error to at least one channel phase locked loop. Additionally, error signal combination comprises receiving error information of a signal relevant to a phase locked loop with respect to each channel; combination logic configured to combine the received error signal information and generate a combined error signal, weighting the received error signal information from each channel, for example with reliability information. An error compensation output is configured to apply the combined, weighted error signal to at least one channel phase locked loop.

Abstract: Frequency error combination for a multi-channel data detection system with a phase locked loop for each channel, comprises receiving frequency error information with respect to each channel; combination logic configured to combine the received frequency error information and generate a combined phase error, weighting the received frequency error information from each channel; and a frequency error output configured to apply the combined frequency error to at least one channel phase locked loop.

Abstract: Phase-error combination methods for a multi-channel data detection system with a phase locked loop for each channel, comprises receiving phase error information with respect to each channel; combining the received phase error information and generating a combined phase error; and applying the combined phase error to at least one channel phase locked loop. Error signal combination comprises receiving error information of a signal relevant to a phase locked loop with respect to each channel; combining the received error signal information and generating a combined error signal, weighting the received error signal information from each channel, for example with reliability information. The combined, weighted error signal is applied to at least one channel phase locked loop.

Abstract: Frequency error combination for a multi-channel data detection system with a phase locked loop for each channel, comprises receiving frequency error information of a signal relevant to a phase locked loop with respect to each channel; combining the received error signal information and generating a combined error signal, weighting the received error signal information from each channel, for example with reliability information. The combined frequency error signal is applied to at least one channel phase locked loop.

Abstract: A method to correct a phase of a data sector due to rotational slip of a disk includes measuring a difference in the phase of a servo sector between a plurality of disks and adjusting an amount of cylinder skew of a logical data sector between the plurality of disks based on the measured difference in the phase of a servo sector between the plurality of disks.

Abstract: A magnetic recording and reproducing apparatus is disclosed which includes: a recording device configured to record with a write head a plurality of tracks constituting a unit of signal processing for data detection, to magnetic recording media; a reproduction device configured to reproduce with a read head a plurality of reproduction signals concurrently from the plurality of tracks on the magnetic recording media in different positional relations to the tracks, the reproduction signals being arranged into that one unit for signal processing thereby generating the track-specific reproduction signals; and a phase alignment device configured to align phases of record signals between adjacent tracks among the plurality of tracks recorded by the recording device to the magnetic recording media.

Abstract: There is provided an information reproduction apparatus that can suppress degradations in the qualities of reproduced data and timing from due to interpolation errors when performing interpolation timing recovery, and that can avoid degradation in the stability of the system due to an increase in the timing recovery loop delay. An information reproduction apparatus (100) for reproducing data and timing from an analog signal including data information and timing information is provided with an expected value generator (106) for outputting plural expected values, and a maximum likelihood detector (107) for outputting data that corresponds to a sequence of the highest likelihood with an output sequence of an A/D converter among the plural expected value sequences, at the timing of a second clock.

Abstract: A random access memory (RAM) in a programmable logic device (PLD) supports error correction as well as a configurable data width. The number of bits in a user data word varies by the selected configuration of the RAM, while the number of bits in the error correction code (ECC) is unvarying, and is based on the total width of the memory. In some embodiments, separate ports are provided for the user data and the ECC data. Thus, ECC data can be written to an ECC portion of the RAM array at a given RAM address, while at the same time user data is written to or read from a configurable user data portion of the RAM array at the same RAM address. In other embodiments, a single memory access port is used for both user data and ECC data.

Abstract: A method for testing the integrity of a memory with defective sections under a plurality of operating environments includes testing the memory with defective sections under a plurality of operating environments, recording results of each operating environment test, and comparing the results of the tests. If the results of are the same, the memory with defective sections is declared to have integrity. If not, the memory with defective sections is declared to not have integrity.

Abstract: An auto-calibration method is applied to a delay circuit, which includes a plurality of delay chains. If the number of accumulative errors of a designated delay chain as a current delay path is larger than a threshold value, the delay circuit scans all the delay chains and records their accumulative error numbers during a unit of time; otherwise, the current delay path is maintained. Afterwards, the number of accumulative errors is compared between all the delay chains to find out which one of the delay chains has a minimum accumulative error number, and the delay chain with a minimum accumulative error number is designated as a new current delay path.

Abstract: In a magnetic data processing apparatus, an input part successively inputs magnetic data from a magnetic sensor. A first generation part stores samples of the magnetic data in accordance with a first sampling rule, and generates first offset update data based on the stored samples of the magnetic data when a distribution of the stored samples of the magnetic data indicates a first feature. A second generation part stores samples of the magnetic data in accordance with a second sampling rule, and generates second offset update data based on the stored samples of the magnetic data when a distribution of the stored samples of the magnetic data indicates a second feature. An update part updates an offset value of the magnetic data based on the first offset update data when the same is generated, and updates the offset value of the magnetic data based on the second offset update data when the same is generated.

Abstract: A device and method are provided for testing the timing of an output signal from a circuit. The output signal can be sent from a circuit contained within a portion of an integrated circuit, and represents a response to a test pattern or stimuli applied to that circuit. The output signal is compared to an expected output signal to determine skew of that signal relative to the clocking of the circuit. Testing the output signal involves placing a characterization path within the functional path of the output signal, between the circuits being tested and an output terminal that can receive a measurement device. By placing the characterization path into the functional path, the output signal sees only a single load gate terminal of, for example, a logic gate. The reduced loading not only positively impacts the normal operation of the output signal, but also beneficially minimizes the possibility of any inaccuracies in the characterization testing.

Abstract: A device comprises a memory array in which a plurality of codewords is stored. Each codeword comprises an error correction code and a data block that comprises a plurality of units of data. The device further comprises an error code correction module coupled to the memory array. When multiple units of data are to be read from the device for an address, a codeword stored in a location associated with the address is fetched from the memory array, the error code correction module decodes the codeword and corrects any errors in the data block for that codeword, and the multiple units of data are read from the corrected data block.

Abstract: A random access memory (RAM) in a programmable logic device (PLD) supports error correction as well as a configurable data width. The number of bits in a user data word varies by the selected configuration of the RAM, while the number of bits in the error correction code (ECC) is unvarying, and is based on the total width of the memory. In some embodiments, separate ports are provided for the user data and the ECC data. Thus, ECC data can be written to an ECC portion of the RAM array at a given RAM address, while at the same time user data is written to or read from a configurable user data portion of the RAM array at the same RAM address. In other embodiments, a single memory access port is used for both user data and ECC data.