Abstract: According to one embodiment, a magnetic disk device includes a disk including a first track including a first parity sector and a second track including a second parity sector, a head that writes data to the disk and reads data from the disk, and a controller that writes, to the first parity sector, a third parity sector obtained by XORing a first sector group included in each of the first track and the second track, and writes, to the second parity sector, a fourth parity sector obtained by XORing a second sector group different from the first sector group, included in each of the first track and the second track.

Abstract: Disclosed is a fault signal recovery system including a data processor configured to generate a signal subset U* by removing, from a signal set U for a plurality of tags, some tags including a fault signal, and a first learning signal subset X* by removing tags disposed at positions corresponding to the some tags from a learning signal set X containing only tags of normal signals, a modeling unit configured to generate feature information F extractable from the first learning signal subset X* and recovery information P on a plurality of recovery models usable for restoring the fault signal, and a recovery unit configured to estimate and recover normal signals for the some tags based on the signal subset U*, the first learning signal subset X*, the feature information F, the recovery information P on the plurality of recovery models, and similarity Z.

Abstract: A data storage device is disclosed comprising a first head actuated over a first disk surface, the first head comprising a plurality of elements including a first element. During a first write operation of the first head, a first bias signal having a first polarity is applied to the first element, and a write interval of the first write operation is measured. During a non-write mode of the first head, a second bias signal having a second polarity opposite the first polarity is applied to the first element during a reverse bias interval that is based on the write interval of the first write operation.

Abstract: A circuit arrangement for determining in parallel of at least two byte error position signals for identifying at least one byte error in a binary sequence comprising a plurality of bytes, wherein the binary sequence in the error-free case is a code word of an error code, the circuit arrangement is configured such that each of the at least two byte error position signals is determinable using components of an error syndrome of the error code such that the components indicate whether or not a byte of the binary sequence that is associated with the byte error position signal is erroneous.

Abstract: A computerized method is described that is adapted to compare extracted features of a received object under analysis with one or more features associated with each known malicious object of a plurality of known malicious objects accessible to the one or more servers. Responsive to determining that the extracted features satisfy a prescribed level of correlation with the one or more features of a first known malicious object of the plurality of known malicious objects, identifying the received object as a malicious object. Also, responsive to determining that the extracted features fail to satisfy the prescribed level of correlation, conducting a second analysis that includes a comparison of the extracted features to the one or more features associated with each of the plurality of known malicious objects being of a type of malware other than malware targeting a specific entity.

Abstract: A signal receiving circuit includes a buffer, a sampling circuit, and an equalizer. The buffer generates first and second amplified signals by amplifying a currently-inputted received signal in synchronization with an amplification clock signal. The sampling circuit generates an output signal by sampling the first and second amplified signals in synchronization with a sampling clock signal. The equalizer changes voltage levels of the first and second amplified signals based on third and fourth amplified signals which are generated from a previously-inputted received signal in synchronization with the amplification clock signal.

Abstract: A system includes, according to one embodiment, a magnetic head having a plurality of write transducers configured to store data to tracks of a sequential access medium and a plurality of read transducers. Each read transducer is configured to read data from the sequential access medium after being written thereto by a corresponding write transducer. A first of the read transducers is aligned with a first of the write transducers, wherein the output of the first read transducer is produced during read-while-write. The system also includes a controller and logic integrated with and/or executable by the controller. The logic is configured to read, using the plurality of read transducers, encoded data from a plurality of tracks of the sequential access medium simultaneously.

Abstract: One example of a printhead assembly includes a housing including sidewalls, nozzles to eject ink drops, a collapsible container, and a sensor assembly. The collapsible container is within the housing to supply ink to the nozzles. The collapsible container includes flexible sidewalls and a spring assembly between the flexible sidewalls. The sensor assembly is coupled to the housing and includes a sensor to provide a sensor signal indicating the amount of ink within the collapsible container.

Abstract: A non-transitory computer-readable recording medium having stored therein a coding program that causes a computer to execute a process. The process includes coding a numerical value to be coded, into a numeric code of base-2n representation; and generating code data that have been added with an instantaneous code indicating the number of digits of the base-2n representation of the numerical value to be coded, wherein “n” is a natural number equal to or greater than 1.

Abstract: In one embodiment, a system includes a magnetic head having a plurality of write transducers and a plurality of read transducers. Each read transducer is configured to read data from a sequential access medium after being written thereto by a corresponding write transducer. The system also includes a controller and logic integrated with and/or executable by the controller. The logic is configured to read, using the plurality of read transducers, encoded data from a plurality of tracks of the sequential access medium simultaneously. The logic is also configured to determine that one or more tracks of the sequential access medium are dead within a sliding window. Moreover, the logic is configured to rewrite a set of encoded data from the one or more dead tracks to live tracks in a rewrite area of the sequential access medium. Other systems, methods, and computer program products are described according to more embodiments.

Abstract: A frequency divider unit has a digital frequency divider configured to divide by an odd integer, and a dual-edge-triggered one-shot coupled to double frequency of an output of the digital frequency divider. The frequency divider unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, and 3.5. In embodiments, the frequency divider unit relies on circuit delays to determine an output pulsewidth, and in other embodiments the output pulsewidth is determined from a clock signal. In embodiments, the unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 as well as many integer ratios including 2, 4, 6, and 8. In embodiments, the digital frequency divider is configurable to provide a 50% duty cycle to the one-shot.

Abstract: The present invention relates to an electromagnetic acoustic transducer excitation system comprising a tone burst generator, the tone burst generator comprising: an oscillator device configured to produce a radio frequency signal; an analog switch configured to produce an output based on the radio frequency signal produced by the oscillator device and a control signal; a pre-amplifier configured to amplify the output of the analog switch and produce a tone burst output signal; and a control module configured to produce the control signal for providing to the analog switch.

Abstract: In one implementation, a data storage system includes a memory array having memory devices in a crossbar configuration, and a memory controller for controlling data storage in the memory array. The memory controller includes an encoder to generate a 2-dimensional encoded bit pattern that encodes an input data. Each run-length of 0's and each run-length of 1's in each row or each column of the encoded bit pattern are at least of a predefined lower limit. The predefined lower limit is at least two. The memory controller includes a write controller to write the encoded bit pattern into the memory devices of the memory array, such that a number of consecutive memory devices in each row or each column of the memory array having a same state is based on the encoded bit pattern.

Abstract: In one embodiment, a system includes a controller and logic integrated with and/or executable by the controller. The logic is configured to cause data to be written to a first write section of a magnetic medium as a plurality of first codeword sets, and cause at least some of the data to be written to a rewrite section of the magnetic medium as one or more rewritten codeword sets. A length of at least one rewritten row stored to the rewrite section of the magnetic medium is greater than either a length of another rewritten row in the same rewritten codeword set and/or a length of at least one row in a codeword set stored to the first write section of the magnetic medium.

Abstract: According to one embodiment, a magnetic disk device includes a disk, a head including a main pole configured to apply a recording magnetic field to the disk, and side shields provided in a first direction with respect to the main pole and possessing a magnetic field in the magnetization direction of the first direction, and a controller configured to output a recording current in which a magnitude of a first electric current and a magnitude of a second electric current opposite to the first electric current in direction of the current are different from each other to the head according to the magnetic field of the side shields.

Abstract: Technology for an apparatus is described. The apparatus can include a plurality of cache memories and a cache controller. The cache controller can allocate a cache entry to store data across the plurality of cache memories. The cache entry can include a value in a metadata field indicating an interleave policy. The cache controller can selectively assign the interleave policy to be applied based on a type of data stored in the plurality of cache memories.

Abstract: In at least one embodiment, an optical data storage tape including a plurality of tracks is provided. The plurality of tracks include a first track having a plurality of first informational fields configured to store one of first positional information indicative of a location on an optical tape and a first predetermined sequence of data. The plurality of tracks further include a second track located adjacent to the first track and having a plurality of second informational fields configured to store one of second positional information indicative of the location on the optical tape and a second predetermined sequence of data. The first positional information is located adjacent to the second predetermined sequence of data on the optical tape to minimize cross track interference during a read operation.

Abstract: The present invention describes a method and system for simultaneous transmission of data to coherent and non-coherent receivers. The method at the transmitter includes retrieving a base ternary sequence having a pre-defined length, obtaining one or more ternary sequences corresponding to data to be transmitted and transmitting the obtained one or more ternary sequences by the transmitter. The method steps at the receiver includes receiving one or more ternary sequences corresponding to the data transmitted, demodulating each of the received ternary sequences by correlating with all cyclic shifts of the base ternary sequence by the receiver if the receiver is a coherent receiver, demodulating each of the received ternary sequences by correlating with all cyclic shifts of the absolute of the base ternary sequence by the receiver if the receiver is a non-coherent receiver and detecting the transmitted data based on the cyclic shifts corresponding to maximum correlation values.

Abstract: The invention relates to estimating tempo information directly from a bitstream encoding audio information, preferably music. Said tempo information is derived from at least one periodicity derived from a detection of at least two onsets included in the audio information. Such onsets are detected via a detection of long to short block transitions (in the bitstream) or/and via a detection of a changing bit allocation (change of cost) regarding encoding/transmitting the exponents of transform coefficients encoded in the bitstream.

Abstract: A heat generating component of a slider is energized at a predetermined frequency. The heat generating component changes a spacing between a medium and the slider. A temperature response proximate a media-facing surface of the slider is measured while the heating element is energized. Based on the measured temperature response, a determination is made as to whether the media-facing surface is contaminated. In response to determining that the media-facing surface is contaminated, remedial action is taken.

Abstract: Systems and methods are provided for encoding forwarded error for data bus width conversion. Input data and input forwarded error information are received. System input parity information is computed based on the input data and the input forwarded error information. Output data based on the input data and system output parity information based on the system input parity information are provided, and it is determined whether to indicate a forwarded error output based on the output data and the system output parity information.

Abstract: A single carrier modulation scheme suitable for use in high frequency communication systems is provided that achieves improved residual frequency error and phase noise estimation. At a transmitter, cyclically orthogonal constant amplitude pilot signals are inserted at the beginning (or end) of a plurality of SCBT blocks of a block coded data stream. At a receiver, a phase rotation of the received data stream is determined to remove a residual frequency error or to estimate the phase noise.

Abstract: A status encoder generates a checksum that encodes a status condition together with the checksum of an associated message. A receiver determines an inverse transformation that when applied to the received status-encoded checksum recovers the parity information associated with the codeword. The status condition can then be recovered based on the selection of the inverse transformation that correctly recovers the parity information from the status-encoded checksum. Beneficially, the status condition can be encoded without requiring additional signal lines or lengthening the codeword relative to conventional error correction devices.

Abstract: An apparatus for controlling a feedback loop includes a digital finite impulse response filter configured to equalize digital samples to yield equalized data, a data detector circuit configured to detect values of the equalized data to yield detected data, a pattern detection circuit configured to detect at least one pattern in the detected data, an expected value comparison circuit configured to compare the digital samples corresponding to the at least one pattern with an expected value, and a feedback loop adaptation circuit configured to control a feedback loop based in part on whether the at least one pattern is detected by the pattern detection circuit and on an output of the expected value comparison circuit.

Abstract: Embodiments of an apparatus and method for encoding data are disclosed that may allow for reduced simultaneous switching output noise. The apparatus may include a row decode circuit, a column decode circuit, and a memory array. The row decode circuit and column decode circuits may be configured to decode a first portion and a second portion, respectively, of a given data word of a first plurality of data words, where each data word may include N data bits, and where N is an integer greater than one. The memory array may be configured to store a second plurality of data words where each data word may include M data bits, and where M is an integer greater than N. The memory array may be further configured to retrieve a given data word of the second plurality of data words dependent upon the decoded first and second portions.

Abstract: A decision circuit includes: a first decision block to distinguish a first bit of bits using an amplitude of an analog signal as a discrimination point, the analog signal being an amplitude shift keyed signal; a superposition block to acquire an absolute value of a difference of the analog signal in respect to an amplitude center value of the analog signal by superposing divided analog signals; an inversion block to control inverting of the signal based on a first distinction result of the first decision block; a second decision block to distinguish a second bit of the bits based on an amplitude of an output signal from the inversion block and the discrimination point; and an output buffer to output the first distinction result and a second distinction result of the second decision block in synchronization with a clock.

Abstract: A method and system for attaching a title key to encrypted content for synchronized transmission to, or storage by, a recipient is provided. Specifically, under the present invention, an elementary media stream is parceled into content units that each include a content packet and a header. The content packets are encrypted with one or more title keys. Once the content packets have been encrypted, the title keys are themselves encrypted with a key encrypting key. The encrypted title keys are then attached to the corresponding encrypted content packets for synchronized transmission to a recipient.

Abstract: A system for transferring real-time video data over a network comprises a video source, a video encoder for encoding and compressing video data supplied by the video source and a first network interface controller for transmitting compressed video data on the network. Furthermore a second network interface controller for receiving compressed video data from the network, a video decoder for decoding the video data received by the second network interface controller, and an image processor for processing and/or displaying the decoded video data from the video decoder are provided. The network controllers are configured for transmitting and receiving data in a continuous data stream which is synchronized with a clock signal and in a format which prescribes a pulse sequence of individual bit groups of which at least one is used for video data.

Abstract: A system comprises a writer to form a plurality of color mits on a base material, wherein at least one of the color mits may represent computer-readable instructions comprising data other than pixel-image data. The plurality of color mits may include a first color mit and a second color mit, wherein the first color mit represents information data, and the second color mit represents that the first color mit contains a particular type of information data. The system also may include a reader to read colors of the plurality of color mits on the base material. The system may comprise a device to map at least one of the color mits to computer-readable instructios. The system may further comprise a processor configured to transmit signals using a colored light.

Abstract: According to one embodiment, a system for selecting an optimum tape layout to store data on a tape medium may include a processor and logic integrated with and/or executable by the processor, the logic being configured to: select a family of data set layouts based on parameters associated with at least a tape drive and the tape medium, compute a set of all minimum distances for the selected family of data set layouts, calculate a first performance metric associated with each possible set of parameters, select a best first performance metric from all calculated first performance metrics and store a set of parameters associated with the best first performance metric, and select a data set layout algorithm which utilizes the set of parameters associated with the best first performance metric, wherein the data set layout algorithm and a rewrite layout algorithm combine to form an optimum tape layout.

Abstract: In one embodiment, a system for integrating data and header protection includes a processor and logic integrated with and/or executable by the processor, the logic being configured to receive a data array organized in rows and columns, each row of the data array comprising two or more interleaved C1 codewords (CWI), and modify one or more rows of the data array to include a header and error correction code (ECC) parity to form one or more modified rows, wherein each modified row includes two or more interleaved codewords, at least one codeword being a C1? codeword which includes ECC parity, wherein each header comprises a CWI Designation (CWID) which indicates a location of the CWI within the data array, and wherein none of the CWIDs are split across multiple C1? codewords in a single modified row. Other systems, methods, and computer program products are presented in additional embodiments.

Abstract: Technologies are described herein for implementing a universal modulation coding mechanism for a data channel. A user data sequence comprising a first number of bits is received. The user data sequence is encoded into a codeword sequence comprising a second number of bits utilizing a modulation encoder. The modulation encoder may encode the user data sequence based on a set of Markov state transition probabilities. The modulation encoder may implement a data de-compressor algorithm from a lossless data compression scheme. The codeword sequence is output to the data channel. The codeword sequence is subsequently received from the data channel, and the user data sequence is decoded from the codeword sequence utilizing a modulation decoder. The modulation decoder may decode the user data sequence based on the same set of Markov states transition probabilities. The modulation de-coder may implement the data compressor algorithm from the lossless data compression scheme.

Abstract: A storage system includes a storage medium operable to maintain a data set, a read/write head assembly operable to write the data set to the storage medium and to read the data set from the storage medium, a multi-level encoder operable to encode the data set at a plurality of different code rates before it is written to the storage medium, and a multi-level decoder operable to decode the data set retrieved from the storage medium and to apply decoded values encoded at a lower code rate when decoding values encoded at a higher code rate.

Abstract: According to one embodiment, a system for selecting an optimum tape layout to store data on a tape medium may include a processor and logic integrated with and/or executable by the processor, the logic being configured to: select a family of data set layouts based on parameters associated with at least a tape drive and the tape medium, compute a set of all minimum distances for the selected family of data set layouts, calculate a first performance metric associated with each possible set of parameters, select a best first performance metric from all calculated first performance metrics and store a set of parameters associated with the best first performance metric, and select a data set layout algorithm which utilizes the set of parameters associated with the best first performance metric, wherein the data set layout algorithm and a rewrite layout algorithm combine to form an optimum tape layout.

Abstract: An interleave address generation circuit includes a plurality of linear feedback shift registers operable to generate addresses for permuting a data block in a first domain to a data block in a second domain on a subword basis. The interleave address generation circuit is operable to generate the lane addresses for each subword and the linear feedback registers configured to generate circulant addresses and sub-circulant address to map bits in each subword in the data block in the first domain to a corresponding subword in the second domain.

Abstract: Systems and method relating generally to improving usage of storage area on a disk drive, and more particularly to systems and methods for applying encoding based upon the nature of a particular region of a disk platter on the disk drive.

Abstract: A method for producing N-bit output words of RLL-encoded data having both a global constraint Go and an interleave constraint Io on bits of a first value includes receiving N-bit input words of RLL-encoded data having both a global constraint Gi and an interleave constraint Ii on bits of like value; and producing the output words from respective input words by sliding-window encoding of each input word to replace predetermined bit-sequences with respective substitute sequences such that Go<Gi; wherein each substitute sequence is unique and violates a run-length limit associated with the interleave constraint Ii such that Io>Ii.

Abstract: Methods and apparatus are provided for improved detection of servo sector data in a magnetic recording system using single bit error correction. Servo sector data is processed by detecting the servo sector data; determining whether a single bit error occurred in the detected servo sector data; and flipping a bit value of an individual bit in the detected servo sector data having a lowest amplitude sample among the samples of the detected servo sector data when a single bit error is detected in the detected servo sector data. The servo sector data comprises, for example, a servo address mark, Gray data, an RRO address mark and/or RRO data. For example, the bit value can be flipped by changing a binary value of one to a binary value of zero and changing a binary value of zero to a binary value of one.

Abstract: According to one embodiment, in a disk storage apparatus, a cancel controller cancels interference on a read target track from adjacent tracks from equalization waveform data obtained by applying waveform equalization processing to a read signal of the read target track based on an interference amount between adjacent tracks. An ITI controller determines whether or not an interference amount for a next read target track exceeds a prescribed value based on the interference amount corresponding to the read target track, and stores, when the interference amount exceeds the prescribed value, the equalization waveform data for the read target track in the memory as cancel data used to cancel interference on the next read target track.

Abstract: A data storage device includes a storage medium on which data is stored in overlapping tracks, and a medium controller that directs storage of data on, and reading of data from, the storage medium, including encoding data being stored and decoding data being read. The decoding includes, when reading a first track, cancelling interference from a second track that overlaps the first track. The data storage device also includes a host controller in communication with the medium controller. The host controller includes memory that stores data decoded, and data to be written, by the medium controller. Communication between the medium controller and the host controller includes signals derived from data on said first and second tracks for facilitating the cancelling. A method of operating a data storage device includes, when reading a first track, facilitating the cancelling by communicating signals derived from the data on the first and second tracks.

Abstract: Methods and apparatus are provided for detecting a sync mark in a storage system, such as a hard disk drive. A sync mark is detected in a storage system by obtaining one or more branch metrics from a data detector in the storage system; generating one or more sync mark metrics using the one or more branch metrics from the data detector; and identifying the sync mark based on the sync mark metrics. An input data set is optionally compared with a plurality of portions of a sync mark pattern to yield corresponding comparison values and the comparison values can be summed to obtain at least one result. A sync mark found signal is asserted based upon the at least one result.

Abstract: A hard disk drive or other storage device comprises a storage medium, a write head configured to write data to the storage medium, and control circuitry coupled to the write head. The control circuitry comprises a write driver configured to generate a write signal comprising a write pulse, and reflection compensation circuitry coupled to or otherwise associated with the write driver and configured to provide one or more reflection compensation pulses in the write pulse.

Abstract: Techniques are provided for automatic gain control loop adaptation in circuitry for processing such data signals. In one example, an apparatus comprises read channel circuitry and signal processing circuitry associated with the read channel circuitry. The signal processing circuitry comprises an amplifier, a detector operatively coupled to the amplifier, and a feedback path operatively coupled between the detector and the amplifier. The amplifier is configured to receive and amplify an input signal received by the read channel circuitry. The detector is configured to detect a data pattern from the amplified input signal. The feedback path is configured to provide a feedback signal to the amplifier to adjust a gain of the amplifier, and to generate the feedback signal in accordance with a value selected to improve detection of the data pattern by increasing an amplitude of the data pattern around a given frequency.

Abstract: A shingled magnetic recording hard disk drive that uses writeable cache tracks in the inter-band gaps between the annular data bands minimizes the effect of far track erasure (FTE) in the boundary regions of annular data bands caused by writing to the cache tracks. Based on the relative FTE effect for all the tracks in a range of tracks of the cache track being written, a count increment (CI) table or a cumulative count increment (CCI) table is maintained. For every writing to a cache track, a count for each track in an adjacent boundary region, or a cumulative count for each adjacent boundary region, is increased. When the count value for a track, or the cumulative count for a boundary region, reaches a predetermined threshold the data is read from that band and rewritten to the same band.

Abstract: Disclosed are servo pattern writing methods and apparatuses for performing the same. In one example, a method may include providing a plurality of disks having reference servo patterns written thereon; writing align patterns aligned with each other in a horizontal direction of the disk surface, on the plurality of disks, using a reference servo pattern of one of the plurality of disks; and writing a final servo pattern on each disk, using the align pattern written on each disk.

Abstract: Systems and methods relating generally to processing information, and more particularly without limitation to systems and methods for encoding data sets.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the disk, and control circuitry coupled to or otherwise associated with the read/write head. The control circuitry comprises a write driver configured to generate a write signal for data to be written to the storage disk, and a multiple-slope transition controller associated with the write driver and configured to control a data transition in the write signal such that the data transition comprises at least two different segments each having a different slope, with the transition controller comprising separate slope control mechanisms for each of the segments. By way of example, the data transition may comprise a dual-slope transition having first and second segments arranged sequentially between a start point and an end point of the data transition.

Abstract: A data processing device for transmitting a first data includes a data generator configured to provide the first data, a cyclic redundancy check (CRC) generator configured to generate a CRC information having at least one bit whose binary value is modified in response to a toggle information, and a data transmitter configured to combine the CRC information and the first data as a combined data and output the combined data in serial. A data processing method for transmitting a first data includes a step of generating a first data, a step of generating cyclic redundancy check (CRC) information having at least one bit whose binary value is modified in response to a toggle information, and a step of generating a combined data by combining the generated CRC information and the first data as a combined data and outputting the combined data in serial.

Abstract: According to one embodiment, a magnetic recording apparatus configured to record information onto a magnetic recording medium by a shingled write recording method, the magnetic recording apparatus includes: a recording head configured to cover a plurality of dot arrays and an end portion of which is situated at one dot array of a recording target; an actuator configured to move the recording head by one array after the recording to one dot array by the recording head; and a controller configured to perform recording compensation of the magnetic dot based on prestored recording data of a peripheral dot of a magnetic dot when input user data is recorded to the magnetic dot.

Abstract: An interleave address generation circuit includes a plurality of linear feedback shift registers operable to generate addresses for permuting a data block in a first domain to a data block in a second domain on a subword basis. The interleave address generation circuit is operable to generate the lane addresses for each subword and the linear feedback registers configured to generate circulant addresses and sub-circulant address to map bits in each subword in the data block in the first domain to a corresponding subword in the second domain.