Abstract: Embodiments of the present disclosure generally relate to a magnetic media drive employing a magnetic recording device. The magnetic recording device comprises a trailing gap disposed adjacent to a first surface of a main pole, a first side gap disposed adjacent to a second surface of the main pole, a second side gap disposed adjacent to a third surface of the main pole, and a leading gap disposed adjacent to a fourth surface of the main pole. A side shield surrounds the main pole and comprises a heavy metal first layer and a magnetic second layer. The first layer surrounds the first, second, and third surfaces of the main pole, or the second, third, and fourth surfaces of the main pole. The second layer surrounds the second and third surfaces of the main pole, and may further surround the fourth surface of the main pole.

Abstract: Systems and methods are disclosed for dynamically adjusting parameters used during a read operation to reduce stress on a read head. In certain embodiments, an apparatus may comprise a read head configured to read data stored to a data storage medium, and a control circuit that controls a parameter of the read head influencing the read head's ability to accurately read data. The control circuit may be configured to extend the working lifespan of the read head by monitoring a read performance of the read head, and adjusting the parameter to reduce the read performance when the read performance is greater than a first threshold.

Abstract: In an embodiment, a storage device is provided. A device controller with a memory is coupled with the storage device. The memory stores an application with instructions that direct the controller to receive a storage device policy. The instructions further direct the controller to store content from a storage request in accordance with the storage device policy, and record storage information, including at least a content identifier, to the memory. Subsequent to storing the content, the instructions further direct the controller to retrieve the content according to the storage information received in a storage request. According to an implementation, the instructions further provide instruction to refuse a delete request in accordance to the storage information. According to an implementation, the instructions provide direction to store the storage information at a remote location.

Abstract: A magnetic recording medium is provided and includes a substrate; and a magnetic layer provided over the substrate, wherein (wmax?wmin)/wmin?400 [ppm] . . . (1) where wmax and wmin are respectively maximum and minimum of average values of width corresponding to samples of magnetic recording medium measured after the samples are stored for two hours under storage conditions (a loading tension in the longitudinal direction of the magnetic recording medium, a temperature and a relative humidity) for each of the samples, and a width of a sample of the magnetic recording medium at 25° C. and 50% relative humidity and without loading is ½ inch, magnetic recording medium has Young's modulus of less than 8.0 GPa in a longitudinal direction, and 4.0?TB/(TA?TB) . . . (2) where TA is average thickness of magnetic recording medium and TB is average thickness of substrate.

Abstract: A microcomputer input/output circuit is provided with a microcomputer, a power supply, a power supply resistor that is connected at one end to the power supply and alternately connected at an another end to grounded external resistors via a switch, a power supply voltage monitoring unit capable of monitoring a power supply voltage, a divided voltage value monitoring unit capable of monitoring a divided voltage value obtained through voltage division by the power supply resistor and a selected one of the external resistors and an external resistor specification means that specifies the external resistor selected by the switch depending on which divided voltage value range corresponding to each of the external resistors the divided voltage value is included, and the external resistor specification means A changes the divided voltage value ranges based on the power supply voltage acquired by the power supply voltage monitoring unit.

Abstract: Systems and methods are disclosed for magnetoresistive asymmetry (MRA) compensation using a digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing analog offset compensation to constrain an extremum of the analog signal to adjust a dynamic range based on an input range of an analog-to-digital converter (ADC), rather than to modify the analog signal to have a zero mean. The method may further comprise converting the analog signal to a digital sample sequence via the ADC; performing, via a digital MRA compensation circuit, digital MRA compensation on the digital sample sequence; receiving, via a digital backend (DBE) subsystem, the digital sample sequence prior to digital MRA compensation; and generating, via a DBE, a bit sequence corresponding to the analog signal based on an output of the DBE subsystem and an output of the digital MRA compensation circuit.

Abstract: A data processing device includes decoder circuits, a checker circuit, and a control circuit. The decoder circuits set groups of first sampling points and groups of second sampling points according to an initial transition edge of a first signal, and perform a parallel decoding on the first signal according to the groups of first sampling points and the groups of second sampling points, in order to generate a second signal and a third signal. The checker circuit checks the second signal and the third signal, in order to generate a check result. The control circuit selects at least one of the decoder circuits according to the check result for receiving subsequent data.

Abstract: A method for monitoring working states of hard disks of a system of hard disks in a hard disk module includes a hard disk controller and a complex programmable logic device (CPLD). The hard disk controller and CPLD communicate with the hard disk module. The CPLD receives output signals from the hard disk controller and determines whether rise and fall changes in a clock signal of each output signal are steady. When a level change of the clock signal of one output signal is steady, the CPLD decodes the one output signal. When a level change of the clock signal of one output signal is not steady, the CPLD will stop decoding the one output signal. A related method is also provided.

Abstract: The presently disclosed technology teaches integrating disc drive electronics into a transducer head. Decreased electrical transit times and data processing times can be achieved by placing the electronics on or within the transducer head because electrical connections may be made physically shorter than in conventional systems. The electronics may include one or more of a control system circuit, a write driver, and/or a data buffer. The control system circuit generates a modified clock signal that has a fixed relation to phase and frequency of a bit-detected reference signal that corresponds to positions of patterned bits on the disc. The write driver writes outgoing data bits received from an external connection to off-head electronics directly to the writer synchronized with the modified clock signal. The data buffer stores and converts digital data bits sent from the off-head electronics to an analog signal that is synchronized with the modified clock signal.

Abstract: A method for improving a detection of beaconing activity includes receiving input data into a computer-implemented processing procedure at least one listing of at least one of time series data and candidate periods of potential beaconing activity. The input data is processed, to detect candidates of potential beaconing activity. By further evaluating the time series data using techniques used for evaluating an analog signal, the performance of detecting of potential beaconing activity is improved to eliminate false positive indications of beaconing activity and/or to provide indication of multiple interleaved periodicities of beaconing.

Abstract: An apparatus comprises a slider having an air bearing surface (ABS), a leading edge, and a trailing edge opposing the leading edge. A writer having a write pole is situated at or near the ABS. A near-field transducer (NFT) is situated at or near the ABS and between the write pole and the leading edge of the slider. An optical waveguide is configured to couple light from a laser source to the NFT. A contact sensor is situated between the write pole and the trailing edge. The contact sensor comprises a first ABS section situated at or near the ABS, a second ABS section situated at or near the ABS and spaced apart from the first ABS in a cross-track direction by a gap, and a distal section extending away from the ABS and connecting the first ABS section with the second ABS section.

Abstract: A preamplifier has a pre-compensation circuit that optimizes the write current in a low current range of less than 30 mA. The pre-compensation circuit maintains the peak current with a high overshoot current amplitude for achieving an optimized areal density capability to equalize the erase widths for the bit lengths of the encoded data with bit lengths greater than three clock time periods with encoded data with a bit length of the two clock time period. Alternately, the pre-compensation circuit has an overshoot generator that determines the optimum amplitude of the overshoot current for the bit-lengths for the encoded data. An overshoot data synchronizer is connected to a read current preamplifier to receive a pseudorandom read data signal that is applied to the overshoot generator to enable the different overshoot current amplitude depending on the bit length of the encoded data. The pre-compensated data current is transferred to the write head.

Abstract: Cloud-based orchestration may be leveraged to create flexible storage solutions that use continuous adaptation to tailor themselves to their target application workloads that made provide efficiencies in performance, cost, or scalability over conventional designs.

Abstract: A sensing circuit of nonvolatile memory device includes a precharge current generator, an adjusting transistor, and an adaptive control voltage generator. The precharge current generator connected to a sensing node and generates a precharge current provided to a bit-line of the nonvolatile memory device, in response to a precharge signal. The adjusting transistor, connected between the sensing node and a first node, adjusts an amount of the precharge current provided to the bit-line in response to a first control voltage. The adaptive control voltage generator generates a control current proportional to an operating temperature, in response to the precharge signal and a second control voltage and boosts a level of the first control voltage in proportion to the operating temperature. The second control voltage is inversely proportional to the operating temperature.

Abstract: An active noise cancellation (ANC) system including a selectable decimation rate decimator that receives an oversampled digital input and has an input that selects the decimation rate, a filter that receives an output of the decimator, and a selectable interpolation rate interpolator that receives an output of the filter and has an input that selects the interpolation rate. The selectable decimation rate decimator and the selectable interpolation rate interpolator operate to provide a selectable sample rate for the filter based on the selected decimation and interpolation rates. The filter may be an anti-noise filter, feedback filter, and/or a filter that models an acoustic transfer function of the ANC system. Rate selection may be static, or dynamically controlled based on battery or ambient noise level. A ratio of the decimation rate and the interpolation rate is fixed independent of the dynamically controlled decimation and interpolation rates.

Abstract: Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage.

Abstract: In an embodiment, a storage device is provided. A device controller with a memory is coupled with the storage device. The memory stores an application with instructions that direct the controller to receive a storage device policy. The instructions further direct the controller to store content from a storage request in accordance with the storage device policy, and record storage information, including at least a content identifier, to the memory. Subsequent to storing the content, the instructions further direct the controller to retrieve the content according to the storage information received in a storage request. According to an implementation, the instructions further provide instruction to refuse a delete request in accordance to the storage information. According to an implementation, the instructions provide direction to store the storage information at a remote location.

Abstract: A bias circuit comprises a closed loop gain stage arranged to determine a difference between a first current in a first branch circuit and a second current in a second branch circuit, where the first branch circuit and second branch circuit are coupled to respective terminals of a magnetic resistor (MR). A first set of current mirrors is arranged to provide a source current to the first terminal of the MR and the second set of current mirrors is arranged to provide a sink current to the second terminal of the MR. The first set of current mirrors and a second set of current mirrors are balanced to reduce a difference in setting time between the source current and sink current. The source current and sink current further reduce the difference between the first current and the second current to provide a constant voltage bias to the MR based on a voltage of a voltage source.

Abstract: A power supply controller having a shortened reset time due to a small hiccup voltage includes an electrical circuit providing a repeated voltage hiccup of a supply voltage of the controller of a switched-mode power supply (SMPS) when the controller enters a latched state. A plurality of comparators each have an input coupled with the controller supply voltage. A multiplexer and two latches are included, each coupled with one or more comparator outputs, and a restart controller is coupled with an output of one of the latches. The restart controller in various implementations toggles a switch to activate and deactivate a current sink to create the supply voltage hiccup. In other implementations, the switch is excluded and the restart controller toggles a voltage startup transistor to couple and decouple a voltage source with the supply voltage to create the voltage hiccup.

Abstract: A disk apparatus includes a disk, a head, a circuit board, and an abnormality detection circuit. The head includes a plurality of loads, including at least a first load and a second load, associated with writing or reading of data to or from the disk, and a plurality of head terminals corresponding to and connected to the plurality of loads, respectively. The circuit board includes board terminals corresponding to and connected to the plurality of head terminals, respectively, and a preamplifier that applies a voltage to the loads via the plurality of board terminals during writing or reading of the data to or from the disk. The abnormality detection circuit detects a short-circuit between a first board terminal, which is the board terminal connected to the head terminal of the first load, and a second board terminal, which is the board terminal connected to the head terminal of the second load.

Abstract: In embodiments, an apparatus for serial communication includes a transceiver, to receive a precoding request from a downlink receiver across a serial communication link, and to transmit data bits to the downlink receiver over the serial communication link. In embodiments, the apparatus further includes a precoder, coupled to the transceiver, to: receive scrambled data bits of a subset of the data bits to be transmitted, from a coupled scrambler, and, in response to the request from the downlink receiver, precode the scrambled data bits, and output the precoded scrambled data bits to the transceiver, for transmission to the downlink receiver across the serial communication link together with other unscrambled data bits.

Abstract: Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval.

Abstract: A method of operating a storage device includes reading data from a storage medium using a detector, processing signals from the detector through a plurality of processing circuits, each respective processing circuit in the plurality of processing circuits being optimized for a different state of a channel condition and providing a respective output metric, selecting a processing circuit from the plurality of processing circuits by comparing the respective output metrics from each processing circuit in a predetermined manner, and designating as output of the detector output of the processing circuit that is selected. The output metrics may be branch metrics or path metrics, and the channel condition may be fly-height or phase shift. The storage device includes a storage medium, and a read channel including a detector, and processing circuits that process signals from the detector. Each respective processing circuit is optimized for a different state of a channel condition.

Abstract: An apparatus may include a circuit configured to generate, by an analog to digital converter (ADC), one or more ADC samples based on an input signal. The circuit may be further configured to generate a first estimated signal using a first channel pulse response estimation with a gain constraint based on the one or more ADC samples and generate a second estimated signal using a second channel pulse response estimation with a phase constraint based on the one or more ADC samples.

Abstract: Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage.

Abstract: An apparatus may include a circuit configured to process at least one input signal using a set of channel parameters. The circuit may adapt, using a regularized adaptation algorithm, a first set of channel parameters for use by the circuit as the set of channel parameters in processing the at least one input signal, the regularized adaptation algorithm penalizing deviations by the first set of channel parameters from a corresponding predetermined second set of channel parameters. The circuit may then perform the processing of the at least one input signal using the first set of channel parameters as the set of channel parameters.

Abstract: Apparatus and method for reducing the effects of thermal asperities on a rotatable data recording surface. A data transducer writes user data to a first set of tracks at a first fly height above the recording surface. A compensation circuit detects a thermal asperity (TA) on the recording surface, and establishes a guard band as a second set of tracks that are co-radial with the TA. The second set of tracks are deallocated and removed from service. The compensation circuit further defines a reserve band as a third set of tracks immediately adjacent the guard band, and selects an increased, second fly height that allows the data transducer to write data to the reserve band without contacting the TA. The second set of tracks may have a greater track pitch than the first set of tracks to compensate for the greater fly height.

Abstract: A pattern is pre-written using a pre-erase or pre-conditioning magnetic field applied within at least part of a target track of a hard disk via a first write transducer prior to the target track being written. Subsequent to the pre-writing, target user data is written to the part of the target track.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first stage that receives an enable signal and an input clock signal and provides a first intermediate signal based on the enable signal and the input clock signal. The integrated circuit may include a second stage that receives the first intermediate signal and the input clock signal and provides a second intermediate signal based on a ternary logic response to the first intermediate signal and the input clock signal. The integrated circuit may include a third stage that receives the second intermediate signal and the input clock signal and provides an output clock signal based on the second intermediate signal and the input clock signal.

Abstract: Systems and methods achieving scalable and efficient connectivity in neural algorithms by re-calculating network connectivity in an event-driven way are disclosed. The disclosed solution eliminates the storing of a massive amount of data relating to connectivity used in traditional methods. In one embodiment, a deterministic LFSR is used to quickly, efficiently, and cheaply re-calculate these connections on the fly. An alternative embodiment caches some or all of the LFSR seed values in memory to avoid sequencing the LFSR through all states needed to compute targets for a particular active neuron. Additionally, connections may be calculated in a way that generates neural networks with connections that are uniformly or normally (Gaussian) distributed.

Abstract: An apparatus may include a preamplifier configured to be connected to a plurality of magnetic read/write heads, wherein each of the magnetic read/write heads includes a read sensor to read data from a disc and a write element to write data to the disc. The preamplifier may include a first set of registers configured to indicate a first head of the plurality of magnetic read/write heads that is selected for reading data, a second set of registers configured to indicate a second head of the plurality of magnetic read/write heads that is selected for reading data, an input line configured to receive a control signal to activate reading data from the first head substantially simultaneously with reading data from the second head, a first output to provide data from the first head, and a second output to provide data from the second head.

Abstract: A power supply controller having a shortened reset time due to a small hiccup voltage includes an electrical circuit providing a repeated voltage hiccup of a supply voltage of the controller of a switched-mode power supply (SMPS) when the controller enters a latched state. A plurality of comparators each have an input coupled with the controller supply voltage. A multiplexer and two latches are included, each coupled with one or more comparator outputs, and a restart controller is coupled with an output of one of the latches. The restart controller in various implementations toggles a switch to activate and deactivate a current sink to create the supply voltage hiccup. In other implementations, the switch is excluded and the restart controller toggles a voltage startup transistor to couple and decouple a voltage source with the supply voltage to create the voltage hiccup.

Abstract: A disk apparatus includes a disk, a head, a circuit board, and an abnormality detection circuit. The head includes a plurality of loads, including at least a first load and a second load, associated with writing or reading of data to or from the disk, and a plurality of head terminals corresponding to and connected to the plurality of loads, respectively. The circuit board includes board terminals corresponding to and connected to the plurality of head terminals, respectively, and a preamplifier that applies a voltage to the loads via the plurality of board terminals during writing or reading of the data to or from the disk. The abnormality detection circuit detects a short-circuit between a first board terminal, which is the board terminal connected to the head terminal of the first load, and a second board terminal, which is the board terminal connected to the head terminal of the second load.

Abstract: Systems and methods for monitoring a regulated voltage output for current consumption are disclosed. An analog component senses the current at the regulated voltage output and converts the sensed current into a digital representation, which is indicative of the sensed current. A digital component inputs and analyzes the digital representation to determine whether to generate an interrupt. The interrupt is indicative to an electronic device, which is using the regulated voltage, to modify its operation. For example, the digital component may analyze the digital representation by counting a number of system clock cycles during a part of the digital representation. The counted number of clock cycles may be compared with a threshold, which may be predetermined or dynamically selected, to determine whether to generate an interrupt. Thus, the sensed current from the regulated voltage output may be used to determine whether to modify operation of the electronic device.

Abstract: In certain embodiments, an apparatus may comprise a first output driver connected to a first output via a first trace and a second output driver connected to a second output via a second trace. The first output driver may be configured to output a first drive signal to the first output to drive the first output and the first drive signal may cause first induced noise in the second trace. Further, the second output driver may be configured to output a second drive signal based on the first drive signal where the second drive signal may reduce the magnitude of the first induced noise at the second output.

Abstract: A method for redundantly storing data includes receiving data at a storage controller, partitioning the data into a plurality of data blocks, generating a first error correction code associated with a first page within the plurality of data blocks, and generating a first redundancy code associated with at least two data blocks within the plurality of data block. The first redundancy code provides additional error recovery if the first error correction code fail. The method further includes storing the plurality of data blocks, the first error correction code, and the first redundancy code across a plurality of solid state storage devices.

Abstract: An apparatus, system, and method are provided for at least mitigating a signal reflection. Included is a filter configured to receive a data signal for transmission, and filter the data signal to generate a filtered data signal. Also included is a gain regulator in electrical communication with the filter. The gain regulator is configured to receive the filtered data signal for adjusting a gain of the filtered data signal to generate a gain regulator output signal for use in at least mitigating a signal reflection. Further, a controller is provided in electrical communication with the filter and the gain regulator. The controller is configured to receive the filtered data signal, and process the filtered data signal to generate at least one controller output signal for use in controlling the filter and the gain regulator.

Abstract: A microcontroller uses a combination of several synchronized PWM outputs to generate a low distortion sine wave by summing the PWM outputs and filtering the summed signal. The sine wave is used as a guard voltage. The unknown impedance is measured by impinging the guard voltage on the sense electrode by a transistor connected in common base configuration and then transferring the sense current through the common base connected transistor to a transimpedance amplifier made out of a second transistor connected in common emitter configuration. The output voltage at the collector of the second transistor is measured by an ADC input of the microcontroller. The microcontroller translates the ADC output values into the unknown impedance to be measured by doing a software demodulation of the ADC output values. A reference impedance can be connected in parallel to the unknown impeder to eliminate gain errors of the signal sensing circuit.

Abstract: Systems and techniques relating to voltage signal peak level detection used in sensor devices, namely in Fly-Height Sensors (FHS) devices include, according to an aspect, an integrated chip device comprising: peak detection circuitry configured to receive a voltage signal and output a peak voltage signal associated with a peak voltage level of the voltage signal, wherein the peak detection circuitry comprises: a linear loop section configured to store the peak voltage level and hold additional voltage levels of the voltage signal at an output terminal of an amplifier to a value greater than zero; and a feedback loop section configured to reduce a leakage current within the peak detection circuitry and generate a guard voltage signal usable to reduce a feedback voltage and prevent the feedback voltage from successively re-entering into the feedback loop section.

Abstract: A memory device includes a normal cell array, a parity cell array, and a plurality of normal write drivers suitable for writing normal write data in the normal cell array. The memory device also includes a plurality of parity write drivers suitable for writing parity write data corresponding to the normal write data, in the parity cell array, and an error injection circuit suitable for injecting error write data to at least one among the plurality of the normal write drivers and the plurality of the parity write drivers to exactly analyze an error of the memory device.

Abstract: One or more magnetic recording disks are coupled to a spindle motor, each of the disks having opposing recording surfaces. Two or more actuators are moveable independently over at least a first recording surface of the one or more disks. A first actuator of the two or more actuators comprises a first write head and a first read head. A second actuator of the two or more actuators comprises at least a second read head and may include a second write head. A controller is coupled to the two or more actuators and configured to write data to a track on the first recording surface using the first write head, and perform a read operation on the data written to the track using the second read head. The controller is also configured to verify that the data was successfully written to the track in response to the read operation. The read operation can be performed within less than one revolution of the first recording surface after the write operation.

Abstract: A fault tolerant voltage regulator may include a plurality of operational transconductance amplifiers. The plurality of operational transconductance amplifiers may be configured according to a unity-gain configuration. The plurality of operational transconductance amplifiers may be configured to couple in parallel to a load. The plurality of operational transconductance amplifiers may be configured to load share a load current associated with the load approximately equally among the plurality of operational transconductance amplifiers.

Abstract: According to one embodiment, a magnetic recording and reproducing device which has a magnetic recording medium, a magnetic head, and a recording current output unit. Magnetic data is recorded on the magnetic recording medium. The magnetic head records the magnetic data on the magnetic recording medium. The recording current output unit supplies a recording current to the magnetic head so as to magnetize the magnetic head. A waveform of the recording current has a first slope for a first period to record data of first information continuously and a second slope for a following second period to switch the data to data of second information and to record the data of the second information. The first slope and the second slope are different from each other.

Abstract: According to one embodiment, a magnetic disk device includes a disk, a head configured to write data to the disk, and an integrated circuit configured to acquire a detection signal indicative of a first pattern of a first frequency of write data, change a first current of a second pattern of a write current corresponding to the first pattern on the basis of the detection signal, detect a third pattern of a second frequency which is greater than the first frequency from the write data, change a second current of a fourth pattern of the write current corresponding to the third pattern, and output the write current with the changed first current and the changed second current to the head.

Abstract: An apparatus may include a circuit configured to generate, by an analog to digital converter (ADC), one or more ADC samples based on an input signal. The circuit may be further configured to generate a first estimated signal using a first channel pulse response estimation with a gain constraint based on the one or more ADC samples and generate a second estimated signal using a second channel pulse response estimation with a phase constraint based on the one or more ADC samples.

Abstract: A data storage device is disclosed comprising a disk, a head for accessing the disk, and a sensor for generating an alternating sensor signal. The sensor is disconnected from an input of a sensing circuit and while the sensor is disconnected an alternating calibration signal is injected into the input of the sensing circuit, wherein the alternating calibration signal comprises a predetermined offset and amplitude. A response of the sensing circuit to the alternating calibration signal is evaluated to detect at least one of an offset and a gain of the sensing circuit.

Abstract: A display may have a substrate layer to which a display driver integrated circuit and flexible printed circuit are bonded. The display driver integrated circuit may be provided with switches and control circuitry for controlling the operation of the switches during bond resistance measurements. Test equipment may apply currents to pads in the display driver integrated circuit through contacts in the flexible printed circuit while controlling the switching circuitry. Based on these measurements and the measurement of trace resistances in a dummy flexible printed circuit, the test equipment may determine bond resistances for bonds between the display driver integrated circuit and the display substrate and between the flexible printed circuit and the display substrate. Displays may have master and slave display driver integrated circuits that share coarse reference voltages produced by the master from raw power supply voltages.

Abstract: The present invention relates to a display, a timing controller and a column driver IC, and more particularly to a display, timing controller and column driver integrated circuit using clock embedded multi-level signaling. The present invention provides a timing controller including a transmitter for transmitting a transmission signal wherein a transmission clock signal is embedded therein between a transmission data signal to have a signal magnitude different from that of the transmission data signal. The present invention also provides a column driver integrated circuit including a receiving unit for separating a clock signal from a received signal using a magnitude of the received signal, and for performing a sampling of a received data signal from the received signal using the separated clock signal.

Abstract: Systems and techniques include a method including: receiving a data request for first data stored at a storage device; reading second data from discrete units of storage of the storage device, the second data comprising the first data read from two or more of the discrete units of storage, error correction code redundancies read from the two or more of the discrete units of storage, and parity data read from at least one of the discrete units of storage; detecting, based on the error correction code redundancies, an error in a first portion of the first data stored in one of the two or more of the discrete units of storage; and recovering the first portion of the first data using the parity data and a second portion of the first data read from one or more remaining ones of the two or more of the discrete units of storage.

Abstract: Techniques for storing data on a tape using a heterogeneous data storage technique are described herein. A logical partition from a logical model of a data storage tape is associated with a set of data. If a current location of the data storage tape corresponds to the logical partition of the set of data, a first data transfer operation associated with the set of data is performed using the data storage tape. The data transfer operation is monitored and changes to the data transfer rate of the data transfer operation are used to update the logical extent of the tape and to update the logical model. If the current location of the data storage tape does not correspond to the logical partition of the set of data, the data set is staged for later storage.