For Electrical Irregularities Patents (Class 361/275.1)
  • Patent number: 11935696
    Abstract: A capacitor includes a capacitor module including a capacitor device, a first busbar electrically connected with a thermally-sprayed surface of the capacitor device and having a first lead terminal on an exposed side, a second busbar electrically connected with the other thermally-sprayed surface of the capacitor device and having a second lead terminal on an exposed side, and an insulating sheet disposed between the first busbar and the second busbar to insulate an overlap region; a plastic case having a 3D space formed by four sides and a bottom to accommodate the capacitor module and having an open top; a metallic external wall is formed outside one side of the four sides or the bottom of the plastic case; and a filler permeating in a gel or fluid state into the space between the capacitor module and inner walls of the plastic case.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: March 19, 2024
    Assignee: NUINTEK CO LTD
    Inventors: Dae-Jin Park, Ying-Won Jeon, Jin-A Park, Hyeon-Jin Kim, Taek-Hyeon Lee
  • Patent number: 11749463
    Abstract: A capacitor is provided having a plurality of first conductive columnar portions that each have a nanosized outer diameter. Moreover, each of a plurality of second conductive columnar portions also have a nanosized outer diameter. A conductive portion is disposed on a first dielectric layer and faces at least a part of each of the plurality of first conductive columnar portions with the first dielectric layer interposed therebetween. The conductive portion is also disposed on a second dielectric layer and faces at least a part of each of the plurality of second conductive columnar portions with the second dielectric layer interposed therebetween. A tip of each of the second conductive columnar portions is located closer to a first support portion than a tip of each of the first conductive columnar portions.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: September 5, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasuhiro Shimizu, Masaki Nagata
  • Patent number: 11670453
    Abstract: An electrical component having a layered structure including first and second electrodes each having first and second electrode portions located in a plane and at least partially embedded in a dielectric body, each of the first and second electrode portions separated by a gap and substantially isolated by the dielectric, the first electrode substantially parallel to and at least partially overlapping the second electrode, wherein the first and second electrodes are electrically isolated and separated by the dielectric body.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: June 6, 2023
    Assignee: Knowles UK Limited
    Inventors: Angela Ellmore, James Cockburn
  • Patent number: 11566495
    Abstract: A downhole tool may include a high-voltage power supply disposed within a housing to transform input power to the downhole tool from a first voltage to a second voltage greater than the first voltage. The high-voltage power supply may include an array of capacitors, which may include multiple rows of capacitors. The rows of capacitors may be parallel with a symmetric cross section as viewed from an end of the array of capacitors. The high-voltage power supply may also include diodes electrically coupled to the array of capacitors.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: January 31, 2023
    Assignee: SCHLUMBERGER TECHNOLOGY CORPORATION
    Inventors: Jani Reijonen, Giovana Stefan, Austin Jones, Matthieu Simon, Anthony Durkowski, Marc-Andre de Looz, Justin Mlcak
  • Patent number: 11476705
    Abstract: A power harvesting device is provided that may supply low voltage power to operate devices in remote locations. The power harvesting device may be connected to a medium to high voltage power line. First and second capacitors divide the voltage to a lower voltage sufficient to power a device, such as a monitoring device. The power harvesting device and monitoring device may be connected to an electric tower with the power harvesting device being connected to a power line supported by the tower.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: October 18, 2022
    Assignee: ABB SCHWEIZ AG
    Inventors: Nirmal Paudel, Vivek Siddharth, David Raschka, Ronald D. Pate
  • Patent number: 10971304
    Abstract: An electronic component includes a body; external electrodes respectively disposed on opposing surfaces of the body in a first direction thereof; and a pair of metal frames connected to the external electrodes, respectively, in which each of the metal frames includes a support portion bonded to the external electrodes, and a mounting portion extending in the first direction from a lower end of the support portion and spaced apart from the body and the external electrodes, and a length of the mounting portion in a second direction perpendicular to the first direction is greater than a length of the body in the second direction.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Beom Joon Cho, Sang Soo Park, Jae Young Na, Woo Chui Shin
  • Patent number: 10720675
    Abstract: A system and method for prolonging a useful lifetime of an energy storage. The method includes: determining, based on a first set of test storage data of the test energy storage, a first set of test configuration parameters comprising a first maximum charge level for the test energy storage, wherein the first set of test configuration parameters corresponds to a first estimated useful life; determining, based on a second set of test storage data of the test energy storage, a second set of test configuration parameters comprising a second maximum charge level for the test energy storage, wherein the second set of test configuration parameters corresponds to a second estimated useful life; and sending, to a controller of the test energy storage, reconfiguration instructions, wherein the reconfiguration instructions are based on the second set of test configuration parameters, wherein the second estimated useful life is longer than the first estimated useful life.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: July 21, 2020
    Assignee: Nova Lumos Ltd.
    Inventors: Ilan Ravid, Nir Marom, David Vortman, Nir Nitzani, Rafael Boneh
  • Patent number: 10418177
    Abstract: A capacitor comprises a first winding member, where the first winding member comprises a first dielectric layer and a first conductive layer. A second winding member comprises a second dielectric layer and second conductive layer. The first winding member is interleaved, partially or entirely, with the second winding layer. A dielectric package is adapted to at least radially contain or border the first winding member and the second winding member. A first metallic member has a generally planar, radially extending surface for electrically and mechanically contacting an upper portion the first conductive layer. A second metallic member has a generally planar, radially extending surface for electrically and mechanically contacting a lower portion of the second conductive layer.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: September 17, 2019
    Assignee: DEERE & COMPANY
    Inventors: Christopher J. Schmit, Neal D. Clements, Andrew D. Wieland
  • Patent number: 9941051
    Abstract: The present disclosure provides a coiled capacitor comprising a coil formed by a flexible multilayered tape, and a first terminating electrode (a first contact layer) and a second terminating electrode (a second contact layer) which are located on butts of the coil. The flexible multilayered tape contains the following sequence of layers: first metal layer, a layer of a plastic, second metal layer, a layer of energy storage material. The first metal layer forms ohmic contact with the first terminating electrode (the first contact layer) and the second metal layer (the second contact layer) forms ohmic contact with the second terminating electrode.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: April 10, 2018
    Assignee: CAPACTOR SCIENCES INCORPORATED
    Inventors: Matthew R. Robinson, Paul Furuta, Pavel Ivan Lazarev
  • Patent number: 9831035
    Abstract: A capacitor comprises a first winding member, where the first winding member comprises a first dielectric layer and a first conductive layer. A second winding member comprises a second dielectric layer and second conductive layer. The first winding member is interleaved, partially or entirely, with the second winding layer. A dielectric package is adapted to at least radially contain or border the first winding member and the second winding member. A first metallic member has a generally planar, radially extending surface for electrically and mechanically contacting an upper portion the first conductive layer. A second metallic member has a generally planar, radially extending surface for electrically and mechanically contacting a lower portion of the second conductive layer.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: November 28, 2017
    Assignee: DEERE & COMPANY
    Inventors: Christopher J. Schmit, Neal D. Clements, Andrew D. Wieland
  • Patent number: 9728339
    Abstract: Methods and apparatus are provided for a high voltage capacitor having a plurality of capacitor units connected in electrical series in a stacked configuration. An insulator element can be positioned between two adjacent capacitor units of the high voltage capacitor for providing separation between the adjacent capacitor units, where the insulator element has a first thickness at a first end of the insulator element and a second smaller thickness at a second end of the insulator element. The insulator element can have a wedge-shaped cross section.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: August 8, 2017
    Assignee: Mexwell Technologies, Inc.
    Inventors: Dominique Guillet, Etienne Savary, Joseph Bulliard, Patrick Gaillard
  • Patent number: 9691550
    Abstract: A multi-layer capacitor has dielectric layers and electrode layers arranged therebetween. The multi-layer capacitor has a number of segments that are connected to one another. At least one relief region is provided between the segments. The invention furthermore provides a method for producing such a multi-layer capacitor.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: June 27, 2017
    Assignee: EPCOS AG
    Inventors: Michael Schossmann, Günter Engel, Stefan Obermair, Bernhard Döllgast, Markus Koini, Jürgen Konrad
  • Patent number: 9343238
    Abstract: A capacitor provides a plurality of selectable capacitance values, by selective connection of six concentrically wound capacitor sections of a capacitive element each having a capacitance value. The capacitor sections each have a respective section element terminal at a first end of the capacitive element and the capacitor sections have a common element terminal at a second end of the capacitive element. A pressure interrupter cover assembly is sealingly secured to the open end a case for the element and has a deformable cover with a centrally mounted common cover terminal and a plurality of section cover terminals mounted at spaced apart locations. A conductor frangibly connects the common element terminal of the capacitive element to the common cover terminal and conductors respectively frangibly connect the capacitor section terminals to the section cover terminals.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: May 17, 2016
    Assignee: American Radionic Company, Inc.
    Inventor: Robert M. Stockman
  • Patent number: 9224563
    Abstract: A main body of an electronic part is formed in a rectangular pillared shape having a first and a second axial end surface. A first electrode is formed on the first axial end surface electrically and mechanically connected to a first wiring pattern formed on a board surface of a printed board. A second electrode is formed on the second axial end surface, to which one end of a fuse terminal is electrically connected. The other end of the fuse terminal is connected to a second wiring pattern of the printed board or a wiring member which is formed as an independent member from the printed board. A cut-off portion is formed in a connecting portion of the fuse terminal.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: December 29, 2015
    Assignees: DENSO CORPORATION, Murata Manufacturing Co., Ltd.
    Inventors: Toru Itabashi, Yuki Mikami, Ryoichi Shiraishi, Akihiro Yanagisawa, Shigeki Nishiyama
  • Publication number: 20150075854
    Abstract: A multilayer electronic component is disclosed with a body having a thickness (T) and a width (W) satisfying the equation T/W>1.0, an upper portion of the body including a first and second internal electrodes with an average width of M1 and a lower portion of the body including a first and second internal electrodes with an average width of M2 satisfying M1>M2.
    Type: Application
    Filed: July 1, 2014
    Publication date: March 19, 2015
    Inventors: Tae Youl YOU, Dae Bok OH
  • Patent number: 8908350
    Abstract: A device including a first electrical conductor, a second electrical conductor, dielectric material connecting the first and second conductors to each other, and an output or ground terminal section. The first electrical conductor has a first terminal section and a first plate section. The second electrical conductor includes a second terminal section and a second plate section. The second terminal section is connected to a first end of the second plate section. The second plate section includes a coil shaped section. The output terminal section is connected to an opposite second end of the second plate section. The dielectric material connects the first and second plate sections to each other.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: December 9, 2014
    Assignee: Core Wireless Licensing S.A.R.L.
    Inventors: Matti Naskali, Samuli Wallius, Lassi Yla-Soininmaki
  • Publication number: 20140232485
    Abstract: A discharge capacitor for use in electronic circuits is described. The discharge capacitor has first internal electrodes in electrical contact with a first external termination and second internal electrodes parallel to and interleaved with the first internal electrodes wherein the second internal electrodes are in electrical contact with a second external termination. A dielectric is between the first internal electrodes and adjacent second internal electrodes. A first discharge gap is between at least one first internal electrode of said first internal electrodes and said second external termination.
    Type: Application
    Filed: April 28, 2014
    Publication date: August 21, 2014
    Applicant: Kemet Electronics Corporation
    Inventors: John Bultitude, Mark R. Laps, Lonnie G. Jones
  • Publication number: 20140104745
    Abstract: A method of fabricating a metal-insulator-metal (MIM) capacitor is disclosed, wherein after capacitor trenches have been formed in a dielectric layer by dry etching, a wet etching process is further applied to the dielectric layer to etch the one or more capacitor trenches. By taking advantage of an isotropic characteristic of the wet etching process, the corners of the one or more capacitor trenches are rounded after the wet etching. Accordingly, a lower electrode, an insulator and an upper electrode formed thereafter over the dielectric layer and the surfaces of the one or more capacitor trenches will also have similar rounded corners at corresponding positions. Such design may substantially reduce the risk of occurrence of point discharge in the resulting MIM capacitor and hence may improve the operational reliability of the capacitor.
    Type: Application
    Filed: December 28, 2012
    Publication date: April 17, 2014
    Applicant: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventor: Chunsheng ZHENG
  • Publication number: 20130208395
    Abstract: An improved overvoltage protection component is provided. The overvoltage protection component has a first internal electrode contained within a dielectric material. The first internal electrode is electrically connected to a first termination and a second internal electrode contained within the ceramic dielectric material is electrically connected to a second termination.
    Type: Application
    Filed: July 5, 2012
    Publication date: August 15, 2013
    Applicant: KEMET ELECTRONICS CORPORATION
    Inventors: John Bultitude, Lonnie G. Jones, Jeffrey W. Bell
  • Publication number: 20130148255
    Abstract: A ceramic short circuit resistant capacitor that is bendable and/or shapeable to provide a multiple layer capacitor that is extremely compact and amenable to desirable geometries. The capacitor that exhibits a benign failure mode in which a multitude of discrete failure events result in a gradual loss of capacitance. Each event is a localized event in which localized heating causes an adjacent portion of one or both of the electrodes to vaporize, physically cleaning away electrode material from the failure site. A first metal electrode, a second metal electrode, and a ceramic dielectric layer between the electrodes are thin enough to be formed in a serpentine-arrangement with gaps between the first electrode and the second electrode that allow venting of vaporized electrode material in the event of a benign failure.
    Type: Application
    Filed: January 29, 2013
    Publication date: June 13, 2013
    Applicant: DELPHI TECHNOLOGIES, INC.
    Inventor: DELPHI TECHNOLOGIES, INC.
  • Patent number: 8208239
    Abstract: A capacitor exhibiting a benign failure mode has a first electrode layer, a first ceramic dielectric layer deposited on a surface of the first electrode, and a second electrode layer disposed on the ceramic dielectric layer, wherein selected areas of the ceramic dielectric layer have additional dielectric material of sufficient thickness to exhibit a higher dielectric breakdown voltage than the remaining majority of the dielectric layer. The added thickness of the dielectric layer in selected areas allows lead connections to be made at the selected areas of greater dielectric thickness while substantially eliminating a risk of dielectric breakdown and failure at the lead connections, whereby the benign failure mode is preserved.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: June 26, 2012
    Assignee: Delphi Technologies, Inc.
    Inventors: John D. Myers, Ralph S. Taylor
  • Patent number: 8116061
    Abstract: A solid electrolytic capacitor that can be miniaturized while maintaining the function for breaking current when excessive short-circuit current flows to a capacitor element. The solid electrolytic capacitor includes an anode body, a dielectric layer formed on the anode body, a conductive polymer layer formed on the dielectric layer, and a cathode layer formed on the conductive polymer layer. The conductive polymer layer contains thermally expandable graphite.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: February 14, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Taeko Ota, Masayuki Fujita, Takashi Umemoto, Hiroshi Nonoue
  • Publication number: 20110317318
    Abstract: Ferroic circuit elements that include a set of conductive structures that are at least partially embedded within a ferroic medium are disclosed. The ferroic medium may be a voltage switched dielectric material that includes ferroic particles in accordance with various embodiments. A ferroic circuit element may be at least partially embedded within a substrate in accordance with embodiments of the current invention as an embedded ferroic circuit element. An embedded ferroic circuit element that is an inductor in accordance with embodiments of the current invention may be denoted as an embedded ferroic inductor. An embedded ferroic circuit element that is a capacitor in accordance with embodiments of the current invention may be denoted as an embedded ferroic capacitor.
    Type: Application
    Filed: May 24, 2011
    Publication date: December 29, 2011
    Inventors: Robert Fleming, Bhret Graydon, Daniel Vasquez, Junjun Wu, Farhad Razavi
  • Publication number: 20100296223
    Abstract: A capacitor exhibiting a benign failure mode has a first electrode layer, a first ceramic dielectric layer deposited on a surface of the first electrode, and a second electrode layer disposed on the ceramic dielectric layer, wherein selected areas of the ceramic dielectric layer have additional dielectric material of sufficient thickness to exhibit a higher dielectric breakdown voltage than the remaining majority of the dielectric layer. The added thickness of the dielectric layer in selected areas allows lead connections to be made at the selected areas of greater dielectric thickness while substantially eliminating a risk of dielectric breakdown and failure at the lead connections, whereby the benign failure mode is preserved.
    Type: Application
    Filed: May 20, 2009
    Publication date: November 25, 2010
    Applicant: DELPHI TECHNOLOGIES, INC.
    Inventors: JOHN D. MYERS, RALPH S. TAYLOR
  • Publication number: 20090279226
    Abstract: A method for forming a capacitor includes providing a metal-containing bottom electrode, forming a capacitor insulator over the metal-containing bottom electrode, forming a metal-containing top electrode over the capacitor insulator, and forming a dielectric-containing field modification layer over the capacitor insulator and at least partially surrounding the metal-containing top electrode. Forming the dielectric-containing field modification layer may include oxidizing a sidewall of the metal-containing field modification layer. A barrier layer may be formed over the capacitor insulator prior to forming the metal-containing top electrode.
    Type: Application
    Filed: April 28, 2009
    Publication date: November 12, 2009
    Applicant: Freescale Semiconductor, Inc
    Inventors: Douglas R. Roberts, Eric D. Luckowski, Shahid Rauf, Peter L.G. Ventzek
  • Publication number: 20090154054
    Abstract: A capacitor includes a dielectric material that is formed of anodic metal oxide; a pair of substantially comb-shaped surface electrodes formed on the same principal surface of the dielectric material; and plural substantially columnar internal electrodes whose one ends are connected to the respective comb-shaped portions of the pair of the surface electrodes and whose other ends extend in the thickness direction of the dielectric material.
    Type: Application
    Filed: June 13, 2008
    Publication date: June 18, 2009
    Applicant: TAIYO YUDEN CO., LTD.
    Inventors: Hidetoshi Masuda, Kenji Kawano
  • Publication number: 20080290381
    Abstract: A conductive shield plane electrically isolating the photodiode regions from metal interconnect lines in an imager sensor device.
    Type: Application
    Filed: May 24, 2007
    Publication date: November 27, 2008
    Inventors: Ray Alan Mentzer, Brian Misek
  • Patent number: 7227238
    Abstract: An integrated fuse has regions of different doping located within a fuse neck. The integrated fuse includes a polysilicon layer and a silicide layer. The polysilicon layer includes first and second regions having different types of dopants. In one example, the first region has an N-type dopant and the second region has a P-type dopant. The polysilicon layer can also include a third region in between the first and second regions, which also has a different dopant. During a fusing event, a distribution of temperature peaks around the regions of different dopants. By locating regions of different dopants within the fuse neck, agglomeration of the silicide layer starts reliably within the fuse neck (for example, at or near the center of the fuse neck) and proceeds toward the contact regions. An improved post fuse resistance distribution and an increased minimum resistance value in the post fuse resistance distribution is realized compared to conventional polysilicon fuses.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: June 5, 2007
    Assignee: Broadcom Corporation
    Inventors: Akira Ito, Henry K. Chen
  • Patent number: 7099141
    Abstract: A short-resistant capacitor comprises an electrically conductive planar support substrate having a first thickness, a ceramic film deposited over the support substrate, thereby defining a ceramic surface; and a metallic film deposited over the ceramic surface, said film having a second thickness which is less than the first thickness and which is between 0.01 and 0.1 microns.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: August 29, 2006
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventors: David Y. Kaufman, Sanjib Saha
  • Patent number: 6882015
    Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: April 19, 2005
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, John A. Bracchitta, William J. Cote, Tak H. Ning, Wilbur D. Pricer
  • Patent number: 6770948
    Abstract: An integrated fuse has regions of different doping located within a fuse neck. The integrated fuse includes a polysilicon layer and a silicide layer. The polysilicon layer includes first and second regions having different types of dopants. In one example, the first region has an N-type dopant and the second region has a P-type dopant. The polysilicon layer can also include a third region in between the first and second regions, which also has a different dopant. During a fusing event, a distribution of temperature peaks around the regions of different dopants. By locating regions of different dopants within the fuse neck, agglomeration of the silicide layer starts reliably within the fuse neck (for example, at or near the center of the fuse neck) and proceeds toward the contact regions. An improved post fuse resistance distribution and an increased minimum resistance value in the post fuse resistance distribution is realized compared to conventional polysilicon fuses.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: August 3, 2004
    Assignee: Broadcom Corporation
    Inventors: Akira Ito, Henry Kuoshun Chen
  • Patent number: 6563188
    Abstract: A semiconductor device of the present invention is provided with a first metal wire formed above a semiconductor substrate with an interlayer insulating film intervened, a fuse formed on interlayer insulating film so as to be spaced at a distance away from first metal wire, an insulating film which covers first metal wire and which has an opening above fuse, a second metal wire formed on insulating film, a first passivation film which covers second metal wire and fuse, and a second passivation film formed on first passivation film, made of a material different from that of first passivation film and having an opening above fuse.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: May 13, 2003
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventor: Hiroyuki Nagatani
  • Patent number: 6531757
    Abstract: A semiconductor device with a fuse box includes at least two gate electrodes 8, 9 and a fuse member 6. The two gate electrodes 8, 9 are formed on at least one insulating film 13 on a semiconductor substrate 100. The fuse member 6 is formed on the insulating film 13 on the semiconductor substrate 100. The two gate electrodes 8, 9 are electrically connected each other by the fuse member 6. In addition, the insulating film 13 and a field region 2 constituted by a semiconductor region are arranged adjacent to each other in a frame-like guard ring 1. The guard ring 1 is constituted by a semiconductor region formed on the semiconductor substrate 100.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: March 11, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Shigeru Shiratake
  • Publication number: 20030043532
    Abstract: A cylindrical electric double-layer capacitor includes a cylindrical sealed vessel housing an electrode roll and an electrolyte solution. The electrode roll is formed of a rolled superposed assembly comprising band-shaped positive and negative poles and two band-shaped separators sandwiching one of the band-shaped positive and negative poles. Each of the band-shaped positive and negative poles includes a band-shaped collector and a pair of polarizing electrodes formed in a laminated manner on opposite surfaces of the band-shaped collector. In a state in which the electrode roll has been accommodated in the sealed vessel along with the electrolyte solution, an outer diameter D1 of the electrode roll and an inner diameter D2 of the sealed vessel are brought into a relationship of D1=D2 by at least one of swelling of the polarizing electrodes caused by the electrolyte solution and expansion of the polarizing electrodes caused by an electrical charge.
    Type: Application
    Filed: July 9, 2002
    Publication date: March 6, 2003
    Applicant: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Minoru Noguchi, Naohiko Oki, Eisuke Komazawa, Takahiro Takeshita, Yasuhiro Matsumoto
  • Patent number: 6212055
    Abstract: A self-healing power capacitor has (a) at least one capacitor unit, each capacitor unit has at least one winding, the windings of each capacitor unit are provided with a first and a second connection electrode and surrounded by an encapsulation material and housed in a first casing (b) at least one protection element for each capacitor winding, the protection element has a membrane provided for activating, upon a pressure exerted on the membrane by a gas produced by a short-circuit within the windings, a current interruption element, the protection element is mounted in a second casing, which is mounted inside the first casing, the second casing has one side formed by the membrane and is separated by a narrow gap from an end-face of the windings.
    Type: Grant
    Filed: April 2, 1999
    Date of Patent: April 3, 2001
    Assignee: Asea Brown Boveri Jumet S.A. (ABB)
    Inventors: Thomas Lovkvist, Henri Bonhomme, Cipriano Monni