Wire Patents (Class 361/308.3)
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Patent number: 10971309Abstract: A capacitor includes: a capacitor element; an insulation coated lead wire connected to an electrode of a capacitor element; and a resin covering the capacitor element and the insulation coated lead wire in a state that one end of the insulation coated lead wire is exposed from the resin. The insulation coated lead wire includes: a stranded wire in which a plurality of conductive wires are twisted with each other; and an insulator covering the stranded wire. An exposed part of the stranded wire is connected to the electrode of the capacitor element. The exposed part is a part exposed from the insulator at another end of the insulation coated lead wire. The exposed part is entirely covered with solder.Type: GrantFiled: March 15, 2019Date of Patent: April 6, 2021Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hirokazu Buto, Masahito Sano, Toshiharu Saito
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Isolating device for electrically isolating a plurality of power-storage assemblies from one another
Patent number: 9818988Abstract: One subject of the invention is an isolating device (10) for electrically isolating a plurality of power-storage assemblies (102) placed side-by-side in a power-storage module (100) from one another, the device comprising a sheet (11) made of an electrically insulating material lying in a main plane (P), the device also comprising at least one tongue (12A-12E; 14A-14E, 16A-16E, 18A-18D, 20A, 20D, 22A-22D) integral with the sheet (11) and capable of protruding from the main plane (P) of the sheet by extending essentially perpendicularly to said main plane of the sheet. Another subject of the invention is a module comprising at least one of these devices.Type: GrantFiled: March 11, 2013Date of Patent: November 14, 2017Assignee: BLUE SOLUTIONSInventors: Anne-Claire Juventin, Laurent Le Gall -
Patent number: 8830654Abstract: An electronic component includes an electronic component body and metal terminals. The electronic component body includes a base member and external electrodes. The base member includes two opposed end surfaces, two opposed side surfaces, and two opposed principal surfaces. The external electrodes are disposed on the end surfaces of the base member. The metal terminals are connected to the external electrodes by bonding with solder. A relationship of about 21?Vc/Vh?about 320 is satisfied where Vc is a volume of the electronic component body and Vh is a volume of the solder provided at one of the pairs of the external electrodes and the metal terminals.Type: GrantFiled: March 15, 2012Date of Patent: September 9, 2014Assignee: Murata Manufacturing Co., Ltd.Inventors: Masayoshi Haruki, Yoshio Takeuchi
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Patent number: 8618420Abstract: In some embodiments, a printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further comprises a plurality of conductive tracks attached to at least one surface of the substrate. The PCB further comprises a multi-layer coating deposited on the at least one surface of the substrate. The multi-layer coating (i) covers at least a portion of the plurality of conductive tracks and (ii) comprises at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical component connected by a solder joint to at least one conductive track, wherein the solder joint is soldered through the multi-layer coating such that the solder joint abuts the multi-layer coating.Type: GrantFiled: February 18, 2011Date of Patent: December 31, 2013Assignee: Semblant Global LimitedInventors: Mark Robson Humphries, Frank Ferdinandi, Rodney Edward Smith
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Patent number: 7781683Abstract: An electrode assembly includes an electrode electrically connected to a capacitor with a wire. An assembly carrier may be used to hold and secure at least the wire and capacitor during assembly. A method of assembly for attaching a wire to a capacitor and an electrode may include an assembly carrier for housing and securing the wire, capacitor, and electrode during assembly.Type: GrantFiled: February 7, 2008Date of Patent: August 24, 2010Assignee: Boston Scientific Neuromodulation CorporationInventors: Matthew I. Haller, Tom Xiahoai He, Jay Daulton
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Patent number: 7663861Abstract: An MIM capacitance element (capacitance lower electrode, capacitance insulation film and capacitance upper electrode) is provided on a first insulation film on a semiconductor substrate. An interlayer insulation film is provided so as to cover the MIM capacitance element and flattened. The interlayer insulation film is provided with a first connection plug connected to the capacitance upper electrode, a first wiring layer, and a second wiring layer. A second insulation film is provided on the interlayer insulation film. The second insulation film is provided with first and second openings. A wiring pull-out portion which connects the first connection plug and the second wiring layer to each other is provided on the second insulation film.Type: GrantFiled: December 10, 2008Date of Patent: February 16, 2010Assignee: Panasonic CorporationInventor: Shinji Nishiura
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Publication number: 20090059470Abstract: According to the configuration and the manufacturing method of forming a moisture proof agent on both surfaces of a circuit substrate after soldering a capacitor connection pin in a vertical direction to the circuit substrate, and electrically connecting the capacitor so as to be in a perpendicular direction to the length direction of the capacitor connection pin at the upper space of the circuit substrate, the possibility of the moisture proof agent attaching to the capacitor is eliminated, the productivity enhances since the moisture proof agent can be easily formed on both surfaces of the circuit substrate, and a capacitor unit of miniaturized and low height configuration is realized since the capacitor is mounted in the horizontal direction in the upper space with respect to the circuit substrate.Type: ApplicationFiled: March 13, 2007Publication date: March 5, 2009Applicant: MATUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kazuki Morita, Tatehiko Inoue, Shusaku Kawasaki, Toshiyuki Kitagawa, Tooru Ninomiya
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Patent number: 7215531Abstract: An apparatus is provided for packaging a laminated capacitor made to have a low ESL value and is used for a decoupling capacitor to be connected to a power supply circuit for a MPU chip providing a MPU. The laminated capacitor is accommodated within a cavity provided on a wiring board. The capacitor includes a plurality of first external terminal electrodes connected to first internal electrodes via a plurality of first feedthrough conductors and a plurality of second external terminal electrodes connected to second internal electrodes via a plurality of second feedthrough conductors. The first external terminal electrodes provided on a first major surface of a capacitor body are connected to via-hole conductors at the hot side for the power source within a substrate, and the second external terminal electrodes provided on first and second major surfaces are connected to grounding via-hole conductors and a mother board within the substrate.Type: GrantFiled: January 8, 2004Date of Patent: May 8, 2007Assignee: Murata Manufacturing Co., Ltd.Inventors: Yasuyuki Naito, Masaaki Taniguchi, Yoichi Kuroda, Haruo Hori, Takanori Kondo
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Patent number: 7212395Abstract: According to some embodiments, a capacitor includes a first external capacitor plane including a first at least one terminal of a first polarity, and a first internal capacitor plane including a second at least one terminal of the first polarity. The second at least one terminal of the first polarity may be electrically coupled to the first at least one terminal of the first polarity, and a total area of the second at least one terminal of the first polarity may be less than a total area of the first at least one terminal of the first polarity.Type: GrantFiled: December 28, 2004Date of Patent: May 1, 2007Assignee: Intel CorporationInventors: Yuan-Liang Li, David G. Figueroa, Farzaneh Yahyaei-moayyed, Dong Zhong
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Patent number: 6836400Abstract: A method for fabrication of ceramic tantalum nitride and improved structures based thereon is disclosed. According to the disclosed method, an ionized metal plasma (“IMP”) tool is used to create a plasma containing tantalum ions where the plasma is sustained by a mixture of nitrogen and argon gases. The percentage of nitrogen partial flow in the mixture of gases is adjusted so as to result in a layer of tantalum nitride with a nitrogen content of at least 30%. With a nitrogen content of at least 30%, the tantalum nitride becomes ceramic. The ceramic tantalum nitride presents a number of advantages. For example, the fabrication of ceramic tantalum nitride can be easily incorporated into fabrication of semiconductor chips using copper as the interconnect metal. Also, ceramic tantalum nitride can be used as an effective etch stop layer.Type: GrantFiled: January 16, 2001Date of Patent: December 28, 2004Assignee: Newport Fab, LLCInventors: Hadi Abdul-Ridha, David T. Young, Maureen R. Brongo
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Patent number: 6765782Abstract: A capacitor includes a capacitive element, which is formed by a plurality of metallic electrodes or films and has contact terminals, and a thermo shrinkable cover applied directly on the capacitive element. A method for manufacturing the capacitor includes a step where a thermo shrinkable tube is applied directly on the capacitive element and in a following step the thermo shrinkable tube is heated to shrink it onto the capacitor element to from the cover.Type: GrantFiled: November 14, 2002Date of Patent: July 20, 2004Assignee: EPCOS do Brazil LTDAInventor: Gilvan Schabbach
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Patent number: 6556420Abstract: An apparatus is provided for packaging a laminated capacitor made to have a low ESL value and is used for a decoupling capacitor to be connected to a power supply circuit for a MPU chip providing a MPU. The laminated capacitor is accommodated within a cavity provided on a wiring board. The capacitor includes a plurality of first external terminal electrodes connected to first internal electrodes via a plurality of first feedthrough conductors and a plurality of second external terminal electrodes connected to second internal electrodes via a plurality of second feedthrough conductors. The first external terminal electrodes provided on a first major surface of a capacitor body are connected to via-hole conductors at the hot side for the power source within a substrate, and the second external terminal electrodes provided on first and second major surfaces are connected to grounding via-hole conductors and a mother board within the substrate.Type: GrantFiled: May 31, 2000Date of Patent: April 29, 2003Assignee: Murata Manufacturing Co., Ltd.Inventors: Yasuyuki Naito, Masaaki Taniguchi, Yoichi Kuroda, Haruo Hori, Takanori Kondo
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Patent number: 6421224Abstract: The invention discloses a micro-structure capacitor formed by joining the metal layer of a multi-porous micro-structure. A substrate is used as an etching stop layer when producing the capacitor. Therefore, pores with low aspect ratio and uniform size are formed on the surface of the substrate. The efficiency of the subsequent thin film coating process is increased. The porous three-dimensional structure increases the capacitance. Micro-structures are stacked up so the capacitor produced features small size and high capacitance.Type: GrantFiled: October 23, 2001Date of Patent: July 16, 2002Assignee: Industrial Technology Research InstituteInventors: Hung-Yi Lin, Hung-Yin Tsai, Jung-Yen Huang, Chin-Hon Fan
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Patent number: 6331931Abstract: An radio frequency (RF)/microwave power amplification circuit is disclosed herein having improved power and frequency characteristics. The RF power circuit is characterized by having the output capacitance of the device resonate with a shunt inductance that is physically closer to the device than provided in conventional RF power circuits. This is realized by mounting a direct current (DC) bypass capacitor directly on the same metalized pad that the device terminal is mounted on. By doing this, the inductance associated with a wire bond connection from the device to the capacitor is eliminated or at least reduced. Also disclosed is a dual cell power circuit that consists of matching the impedance characteristics of the active cells to each other by adjusting the circuit parameters in which the active devices interact with.Type: GrantFiled: October 3, 2000Date of Patent: December 18, 2001Assignee: Integra Technologies, Inc.Inventors: John H. Titizian, Jeffrey A. Burger, Young H. Kim
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Patent number: 6319292Abstract: A capacitor includes a porous pellet formed from compressed conductive particles. The pellet has a lead receiving external surface. The conductive particles at the lead receiving surface are fused together to create a fused layer on the external surface of the pellet. A lead wire has one of its ends welded to the fused layer on the surface of the pellet. The fused layer is formed by exposing it to high temperatures, preferably by use of a laser beam.Type: GrantFiled: June 5, 2000Date of Patent: November 20, 2001Assignee: Vishay Sprague, Inc.Inventors: Yuri L. Pozdeev-Freeman, Boris Levi, Semion Akselrod