Abstract: A power converter such as an inverter or chopper using self-turn-off type semiconductor devices supplies power to an inductive load and free wheel diodes are provided so that the current flowing through this load circulates not through the power supply but through the free wheel diodes. When it is detected that the load current exceeds a predetermined value, the self-turn-off-type semiconductors which are conductive are turned off. At this time, the self-turn-off-type semiconductors which are turned on and immediately thereafter cause the recovery current to flow in the free wheel diodes are turned off not immediately but after the recovery current disappears.

Abstract: An inverter using gate turn-off thyristors (GTOs) is controlled by means of pulse width modulation (PWM) to control the speed of an induction motor. If the current flowing through the induction motor becomes an overcurrent which can still be cut off by the GTOs, a gate off signal is supplied to respective GTOs to interrupt the overcurrent. If any one of arms respectively corresponding to phases is short-circuited, a gate on signal is supplied to all GTOs to distribute the short circuit current among the arms, and the main circuit is interrupted by a high-speed breaker. At this time, a simultaneous gate on signal is given priority. If the simultaneous gate on signal is present, a simultaneous gate off signal is disabled. Owing to this configuration, destruction of the GTOs due to consecutive guard operation can be prevented.

Abstract: A DC-AC converter comprises a bridge of electronic switches having a load connected in one diagonal and the constant voltage source connected to the other diagonal. The two switches of each bridge branch are connected to one another by at least one resistor, the load being connected to one end of the resistor.

Abstract: A series inverter, high voltage capacitor charging circuit includes current sensors for sensing the current through each SCR in the circuit. The sensed current is used to vary the gating frequency of the SCRs and to preclude firing of an SCR until the other is in a stable off condition. The gating of each SCR is delayed by an amount of time determined by a control capacitor charging circuit. That charging circuit is inhibited as long as one of the SCRs is conducting and once the load voltage has reached a predetermined level. The time constant of that charging circuit can be changed as the desired level is approached of if insufficient reverse bias is applied to an SCR for quick turn-off of the SCR. Resolution of the system can be increased by a shunt regulator which shorts the output transformer. The circuit can be disabled if the high voltage capacitor does not reach its set level within a given time.

Abstract: A high-frequency high-voltage power supply in which a high-frequency high-voltage is generated with the aid of L-C oscillation without a high-frequency primary power supply or a high-frequency high-voltage converter. The negative output terminal of a first D.C. high-voltage power supply and the positive output terminal of a second D.C. high-voltage power supply are connected together and to one of the high-frequency high-voltage output terminals. Tank capacitors are connected between the positive and negative output terminals of the power supplies, respectively. One end of a first combination of a first thyristor and a first rectifier connected in anti-parallel relationship is connected to the positive output terminal of the first power supply with the anode of the first thyristor connected to the positive output terminal.

Abstract: A scheme for determining the operational state of a control turn-off semiconductor, of the type having an anode, a cathode and control electrode to which signals are applied to control the conductive state of the semiconductor, utilizes the extant voltage at the control electrode to determine the actual conductive state of the semiconductor. A first signal representing the desired operational state of the semiconductor and a second signal representing the actual operation of the state of the semiconductor and appropriately combined in one embodiment to generate an indication of the operational state of the control turn-off semiconductor. A further embodiment, employed in a series connection of two such control turn-off semiconductors beteen dc buses, uses the second signals in a cross-coupled arrangement between the two semiconductors to inhibit the application of control signals to a first semiconductor if the second semiconductor is conductive.

Abstract: A power conversion device such as an inverter using as bridge arm elements self-extinguishing-type switching elements for converting D-C input power into A-C load power. Snubbers, each including a capacitor and a diode in series, are connected in parallel with the switching elements. A discharging circuit, having a diode is connected across the diodes of the snubbers, and a power source feedback circuit, including a current transformer, are employed to return the current discharged from the snubbers to the input power source, thereby enhancing conversion efficiency.

Abstract: A switching time correction circuit for electronic inverters controls the operation of power pole switches by delaying the application of each transition point in a reference pattern signal to the output switches. The length of the delay is reduced for transition points in the reference signal which correspond to negative power transitions in the power pole switch and the amount of delay time reduction is proportional to the output current of the respective power pole switch. By inserting a variable delay between the reference signal and the power switch, transition points in the output voltage are each delayed by a fixed time with respect to transition points in the reference waveform pattern.

Abstract: Energy trapped in the snubbers connected to a dc-ac power converter is more efficiently restored to the dc source by means of an energy recovery transformer with a reset circuit branch for improving the reset of the transformer following a period of energy recovery. The reset circuit branch damps out oscillations between the recovery transformer and the overcharged shunt capacitive snubber and may also be used to dissipate the magnetizing current of the energy recovery transformer.

Abstract: An inverter device using semiconductor current control elements is disclosed in which a parallel circuit of a current limiting circuit composed of a reactor and a voltage spike absorbing circuit composed of a series circuit of a constant voltage element and a diode is connected in series with each of the semiconductor current control elements to prevent excess current flow through the latter.

Abstract: In a current type GTO inverter, commutation surge voltage is inevitably generated from an inductive load whenever each GTO is turned off. The commutation surge voltage thus generated is once stored in a capacitor through a diode surge voltage rectifier and then restored or regenerated to the DC source terminals of the GTO bridge-connected inverter through a pair of other GOTS turned on only when the capacitor voltage exceeds a predetermined value beyond the DC source voltage. After energy restoration, magnetic energy stored in a reactor is recharged in the same capacitor. The necessary elements are a capacitor, two GTOs, two diodes and a DC reactor, thus simplifying the circuit configuration and reducing the cost. Additionally, since no vibration circuits to turn off thyristors for restoring the energy charged in the capacitor to the GTO bridge-connected inverter are required, the circuit operation is stable at higher frequency range, in particular.

Abstract: A polyphase SCR inverter (10) having N switching poles, each comprised of two SCR switches (1A, 1B; 2A, 2B . . . NA, NB) and two diodes (D1B; D1B; D2A, D2B . . . DNA, DNB) in series opposition with saturable reactors (L1A, L1B; L2A, L2B . . . LNA, LNB) connecting the junctions between the SCR switches and diodes to an output terminal (1, 2 . . . 3) is commutated with only one GTO thyristor (16) connected between the common negative terminal of a dc source and a tap of a series inductor (14) connected to the positive terminal of the dc source. A clamp winding (22) and diode (24) are provided, as is a snubber (18) which may have its capacitance (c) sized for maximum load current divided into a plurality of capacitors (C.sub.1, C.sub.2 . . . C.sub.N), each in series with an SCR switch S.sub.1, S.sub.2 . . . S.sub.N). The total capacitance may be selected by activating selected switches as a function of load current.

Abstract: A power converter typically used for operating electrical machines and provided with protective measures to protect against overvoltages which can otherwise occur in the process of switching off the inductive loads represented by the electrical machines. To that end, the converter includes plural bridge circuits having a.c. voltage terminals and d.c. voltage terminals, wherein the a.c. voltage terminals are phasewise parallel-connected and coupled to each other via at least one capacitor and wherein the d.c. voltage terminals are coupled to each other via at least one intermediate circuit reactor. The bridge circuits include bridge arms having GTO thyristors that can be switched off, and the plural bridges are driven out of phase with respect to one another. In this way, the converter supplies an alternating current which is relatively near-sinusoidal and exhibits a low harmonics content to the electrical machine.

Abstract: A gate control circuit for current-type inverter apparatus having an inverter formed of self-extinction devices connected in a bridge form, comprises a logic circuit, pulse stretchers and gate amplifiers. When a frequency command signal is applied to the logic circuit, the logic circuit generates pulse signals for turning on or off the self-extinction devices, and the pulse signals are delayed for predetermined time in their trailing edges in response to the leading edges of the signals by the pulse stretchers so as to be extended, are amplified by the gate amplifiers, and then are supplied to the gates of the self-extinction devices.

Abstract: A multiple inverter has an input shut-off circuit receiving a DC energy input and providing two DC outputs; two unit inverters coupled to the input shut-off circuit, each including switching elements, for respectively converting the DC outputs into two AC outputs; and a control circuit coupled to the unit inverters for detecting an accidental overcurrent due to a shoot-through of the switching elements, and turning off the unit inverters. The input shut-off circuit includes circuit elements for interrupting a current path of the DC energy input when the control circuit detects the accidental or faulty overcurrent.

Abstract: A thyristor apparatus employing light-triggered thyristors comprises forward voltage detecting circuits (15) and a thyristor number detecting circuit (17). The forward voltage detecting circuits (15) detect forward voltages applied to light-triggered thyristors (13) to provide detected signals. The thyristor number detecting circuit (17) is responsive to the detected signals to cause light-triggered thyristors in a thyristor arm (U) to be turned on simultaneously in the case where the number of the light-triggered thyristors being supplied with forward voltages is one or more but not more than a predetermined number. Accordingly, if and when an overvoltage is applied to the thyristor arm (U), overvoltage suppressing elements (14) are prevented from being damaged even if partial commutation failure occurs in the light-triggered thyristors.

Abstract: A method of and apparatus for controlling an inverter of a load commutation type, the inverter having arms each having a thyristor in which pulses are produced and distributed to the gates of the thyristors for performing, under normal circumstances, constant margin time control or constant margin angle control. The voltage across the load is detected and its magnitude is compared with a predetermined level. When the magnitude exceeds the predetermined level, a pulse is produced and delivered through the distributor to the gates of the thyristors.

Abstract: A series inverter, high voltage capacitor charging circuit includes current sensors for sensing the current through each SCR in the circuit. The sensed current is used to vary the gating frequency of the SCRs and to preclude firing of an SCR until the other is in a stable off condition. The gating of each SCR is delayed by an amount of time determined by a control capacitor charging circuit. That charging circuit is inhibited as long as one of the SCRs is conducting and once the load voltage has reached a predetermined level. The time constant of that charging circuit can be changed as the desired level is approached.

Abstract: A series inverter, high voltage capacitor charging circuit includes a current sensor for sensing the current through the load circuit. The sensed current is used to vary the gating frequency of SCRs and to preclude firing of an SCR pair until another SCR pair is in a stable off condition. The gating of each SCR pair is delayed by an amount of time determined by a control capacitor charging circuit. That charging circuit is inhibited as long as one of the SCRs is conducting and once the load voltage has reached a predetermined level. The time constant of that charging circuit is longer if insufficient reverse bias is applied to an SCR for quick turn-off of the SCR. The current sensing thresholds of common base transistors depend on whether forward or reflective current is being sensed. A series capacitor in the load circuit is discharged prior to a first cycle of current flow from the dc supply.

Abstract: An energy converter comprising a series-resonant bridge circuit (1) containing at least two thyristors (6, 7), first and second respective diodes (8, 9) connected antiparallel thereto, a high-frequency output transformer (23), and an energy buffer (2). A control circuit (20) is incorporated for generating trigger pulses for the appropriate thyristors in response to the energy of the buffer (2). The energy converter comprises means for ensuring that the diode, antiparallel connected to the last-conducting thyristor, starts to draw current immediately after this thyristor is blocked. The control circuit also generates signals indicative of the presence of current flowing through the diodes (8, 9), which signals control the supply of the trigger pulses to the thyristors (6, 7).

Abstract: A no-break power supply apparatus includes a plurality of CVCFs, each CVCF having a bridge circuit having an arm including inverters, a parallel circuit having the GTO thyristor and a diode connected in reverse polarity in parallel with the GTO thyristor, a fuse connected in series with the parallel circuit, and a fuse melting detector connected across the fuse, and protecting circuits controlled for supplying a predetermined ON gate signal/OFF gate signal in accordance with the fuse melting detection signal detected when an accident occurs to the gate of each GTO thyristor.

Abstract: An inverter circuit having a bridge circuit comprising a plurality of switching elements connected in the form of a bridge for converting, into alternating current, a DC voltage produced by a DC voltage generating unit and which is received through a first switching circuit. The inverter circuit includes a pair of diodes and a spike absorbing capacitor which constitute a series network wherein the diodes are connected so as to be forward biased with respect to the DC voltage and the spike absorbing capacitor is connected between the diodes. The series network is connected in parallel with the bridge circuit and is connected to the DC voltage generating unit through the first switching circuit. The spike absorbing capacitor is connected in parallel with a smoothing capacitor of the DC voltage generating unit.

Abstract: A system for forming addressing signals for addressing respective converter switches of a frequency converter; the frequency converter being of the type which is provided with DC input terminals for receiving electrical energy which is conducted to phase output terminals when the converter switches are operated in response to the addressing signals. Each of the combinations of converter switches is associated with a discrete space vector, and a load voltage vector is determined. In operation, two of the discrete space vectors which are adjacent to the voltage space vector are addressed for respective dwell times which correspond to the components of the voltage space vector as impressed upon the adjacent discrete space vectors. Either prior to or after the addressing of the adjacent discrete space vectors within a switching cycle, a short circuit state is addressed. In one embodiment, the order in which the adjacent discrete space vectors are addressed is reversed for each subsequent switching cycle.

Abstract: A pulse width modulation inverter loaded with a three-phase AC motor is halted when a logical condition exists that a halt signal has been given and all of pulse width modulation signals applied to either three positive side or three negative side main thyristors in a three-phase bridge connection constituting the inverter are in their high level states.

Abstract: A system, for use with a controlled current inverter to prevent malfunction of inverter action resulting from an insufficient capacitor voltage to effect commutation of an inverter bridge controlled rectifier, provides that the capacitor voltage is sensed and, if it is of insufficient value to effect rectifier commutation, the application of gating signals to the next to be rendered conductive controlled rectifier is inhibited. In order to achieve initial inverter operation, the inverter current is also sensed and the inhibit function is rendered ineffective until such time as the current reaches a predetermined value.

Abstract: An improved D-C to A-C inverter circuit is provided including push-pull sequentially activated thyristor switches connected across a center-tapped D-C voltage source with a saturable reactor connected in series between each thyristor and the center-tap return branch and at least one saturable reactor connected in the center-tap return branch to effectively reduce peak operating voltages.

Abstract: A short-circuit protection device for a DC control element has at least one transistor which is addressed by timing pulses obtained by comparison of a triangular voltage with a control voltage. Each such transistor is provided with a separate overcurrent protection device which, after a short circuit, blocks the associated transistor until the beginning of a new switching-on pulse. The control voltage assumes values which are above the maximum value of the triangular voltage.In the event of a short circuit, the transistor concerned is switched off very fast, but is switched on again by the next succeeding switching-on pulse and a determination is made as to whether the short circuit is still present.

Abstract: An adjustable-frequency three phase motor control system (2, CSI, M) is provided with a spike voltage clamp (SVC) to control the magnitude of voltage spikes generated during commutation of the current source inverter (CSI) thereby to protect the low voltage power devices (12a-c, 14a-c, SCRl-6) from damage. This spike voltage clamp comprises a rectifier bridge (32) connected to the output terminals (01, 02, 03) of the inverter (3) a storage capacitor (C) connected across the rectifier bridge output terminals, and a spike voltage dissipating resistor (Ra, Rb) and a gate turn-off thyristor (GTO) connected in series across the capacitor. A clamp control circuit (CC) precharges the storage capacitor and senses an increasing voltage thereon in response to voltage spikes across the motor terminals and gates the thyristor (GTO) to allow the resistor to dissipate a portion of the energy of the voltage spikes thereby limiting the magnitude of the voltage spikes.

Abstract: A fault protection system for a balanced thyristor capacitor/inverter half-bridge which generates a high frequency oscillating voltage from full-wave rectified line voltage is disclosed. Following the detection of thyristor over-current and the removal of transformer-coupled, alternating, gated drive signals from the thyristors by means of logic and control circuitry, the natural ringing of a charged resonant circuit coupled across the inverter half-bridge causes thyristor commutation and inverter shutdown. The resonant circuit and inverter half-bridge are isolated from the line voltage source during the fault recovery cycle by means of an inductance, the size of which is selected to greatly exceed the total inductance in the inverter bridge-resonant circuit system to avoid saturation until the power thyristors have been given sufficient time to turn off.

Abstract: A control circuit for driving an induction motor wherein an AC voltage is converted into a direct current by a rectifying circuit and the direct current is converted into a signal having a variable voltage and frequency by a transistor inverter connected in parallel with a smoothing capacitor, and a regenerative circuit is connected in parallel with the inverter, and a circuit is provided for comparing the terminal voltage V.sub.C of the smoothing capacitor and a reference voltage V.sub.r when braking is to take place is disclosed. When condition V.sub.C .gtoreq.V.sub.r exists, the transistor inverter is disabled but the regenerative circuit is allowed to operate; when the condition V.sub.C <V.sub.r exists, the transistor inverter is operated in the regenerative braking mode.

Abstract: An arrangement for generating DC magnetic fields of alternating polarity for the magnetic-inductive flow measurement by means of a field coil which is connected via alternately controlled switching members to a DC voltage source, wherein during the reversal time following the change-over of the switching members a capacitor is connected to the field coil to form a resonant circuit separate from the DC voltage source and the capacitance C of the capacitor in dependence upon the desired reversal time .DELTA.t has substantially the value ##EQU1## wherein L is the inductance and R the ohmic resistance of the field coil.

Abstract: Shortcircuit in an arm including a series connection of GTO's and reactors of an inverter is detected by sensing a voltage across the reactor. In one method, the shortcircuit in the arm is detected when voltages are coincidently applied to a P-line arm reactor and an N-line arm reactor for a predetermined time period. In another method, it is detected when an integrated value of a voltage across at least one of the reactors exceeds a predetermined level.

Abstract: The inverter may be single phase with one inverter leg or N-phase with N inverter legs for connection across a DC source. Each leg includes a pair of series connected thyristors with a terminal between the thyristors for connection to a load. In addition, each thyristor has a diode connected in reverse polarity across it. A commutation circuit which includes an inductor in series with the inverter legs and a capacitor in parallel with the inductor and the inverter legs, provides a commutation pulse to turn off the thyristors in each leg. A further isolating inductor is connected at the DC power input to the inverter, and a reverse polarity feedback diode may be connected across it.

Abstract: A plurality of SCR diamond bridge circuits are coupled in series to generate frequencies higher than the individual operating frequencies of the SCR's. The series chain of diamond circuits is preferably coupled in parallel with the series combination of a DC blocking capacitor and an inductive load. The chain is provided with current from a substantially ripple-free constant current source, and the firing times of individual SCR's can be controlled to minimize the di/dt in each SCR.

Abstract: The converter protection device has a number of controlled semiconductor elements. A control unit is connected to the semiconductor elements of the converter for forming firing pulses for the controlled semiconductor elements. Reference blocking intervals for the semiconductor elements are set and actual blocking intervals of the semiconductor elements are set and controlled. A comparator receives and compares the reference and actual blocking intervals. There are also provided a read-only memory for storing the reference blocking intervals, an event counter for counting disturbances detected by comparison of the reference and actual blocking intervals, a memory stage being connected to the event counter and being set if the event counter reaches a predetermined count, and a time-base device connected to the event counter and memory stage for resetting the event counter if the memory stage is not set at the end of a predetermined base time.

Abstract: A series inverter, high voltage capacitor charging circuit includes current sensors for sensing the current through each SCR in the circuit. The sensed current is used to vary the gating frequency of the SCRs and to preclude firing of an SCR until the other is in a stable off condition. The gating of each SCR is delayed by an amount of time determined by a control capacitor charging circuit. That charging circuit is inhibited as long as one of the SCRs is conducting and once the load voltage has reached a predetermined level. The time constant of that charging circuit can be changed as the desired level is approached.

Abstract: A power line control circuit receives audio-frequency signals from a pulsed inverter that is transformer-coupled to the power line. A filter circuit is connected between the inverter and the coupling transformer primary circuit to transmit the audio signals and prevent power line frequencies from reaching the inverter. A magnitude-measuring circuit determines when output current from the inverter exceeds a certain value and controls an intervening circuit to reverse, briefly, the state of conductivity of the inverter.

Abstract: A fault detector for detecting shoot-through conditions in series connected solid state rectifiers (326, 329) of a power inverter (314) is disclosed. A capacitor (311) discharges when a shoot-through occurs and the discharge current is detected by a current transformer (315). An SCR (317) is gated on by the detector to short circuit the DC bus (327, 328) and prevent damage to the solid state rectifiers (326, 329).

Abstract: A rectifier controller for controlling bridge connected silicon control rectifiers (SCRs) (1 to 6) of a three-phase rectifier which is used to supply a direct current (DC) voltage to an inverter (314) used for injecting pulse coded audio frequency signals on a power line. The controller supplies gate control signals to the SCRs (1 to 6) of the rectifier bridge in accordance with the envelope of the three-phase supply voltages and provides for protection of the inverter (314) when shoot-through conditions occur in the inverter (314) and provides for output DC voltage adjustment by controlling the firing time of the rectifier bridge SCRs.

Abstract: A circuit for commutating a thyristor (21) by shunting its current for a minimum interval, thereby removing sustaining voltage to said thyristor, then subsequently restoring voltage to said thyristor at a predetermined rate, utilizes a series combination of a commutation electronic switch (22) and an isolated dc voltage supply (23) connected in parallel with the thyristor. The voltage supply is arranged with a polarity that permits the current flowing through the thyristor in one direction to be bypassed through the series combination while the commutation switch is turned on and to reverse bias the thyristor when the commutation switch is fully on. A dv/dt control circuit (24) limits the rate of rise of voltage across the commutation switch (22) as it is turned off in response to a command input signal.

Abstract: A d.c. motor whose armature is supplied from an a.c. power source through an a.c./d.c. thyristor converter and is subject to damaging commutator flash-over, as from loss of a.c. voltage during regeneration is provided with a protective circuit which includes a normally charged capacitor and a diverter resistor which are connectable across the converter and motor armature, respectively, by SCR means in response to a fault condition such as either predetermined high output current from the converter (i.e., indicative of high armature current) or excess a.c. input current to the converter. Connection of the capacitor across the converter and its discharge instantaneously and forcibly but temporarily blocks current flow from the converter thyristors to the motor armature.

Abstract: An adjustable speed pumping system includes a plurality of pumps respectively driven by variable speed A.C. motors each having a power recovery circuit. Each power recovery circuit includes a series connected rectifier bridge, an inductive reactor and an inverter coupled to the secondary winding of the motor which has an A.C. source connected to the primary winding. A fault clearing mechanism is included in each circuit and includes solid state switches in the bridge actuated by a current level sensor coupled to the inverter output. The power recovery circuit also includes current foldback circuitry and secondary gating circuitry coupled to thyristors in the inverter. The power recovery circuits can be connected in parallel with a single motor and the system includes circuitry for sensing the highest amplitude current in the parallel circuits and controlling all circuits with this current.

Abstract: There are arranged an oscillator for generating a first pulse signal on which the AC output frequency of the inverter is based, a delay circuit for generating a second pulse signal delayed for a predetermined period of time from the first pulse signal, and a ring counter for generating responsive to the second pulse signal a phase reference signal corresponding in phase to the AC output of the inverter. An ON pulse is generated responsive to the second pulse and the phase reference signal and an OFF pulse responsive to the first pulse and the phase reference signal. A negative bias signal is generated following the OFF pulse. At the time of operation stop the negative bias signal following the ON and OFF pulses is applied to GTO thyristors simultaneously.

Abstract: A substantially zero rotation and substantially zero torque detector and method for an AC electric motor drive system includes an AC electric motor producing a rotation in response to an outgoing signal, e.g., drive current, of variable magnitude and frequency. An actual rotation signal is generated and is proportional to the rotation of the AC electric motor or to the frequency of the outgoing signal. A rotation reference signal proportional to a desired level of rotation is established. A rotation difference signal representative of any difference between the rotation reference signal and the actual rotational signal is generated. A torque command signal is provided as a function of the rotation difference signal and is used to produce a frequency control signal and a current control signal. Alternatively, the torque command signal is generated proportional to a desired level of torque when the drive system utilizes a desired torque level as opposed to a desired rotation level.

Abstract: At least one smoothing reactor is connected to the positive terminal of a DC source. A first interphase reactor has its one end connected to the other end of the smoothing reactor. A second interphase reactor is connected to the negative terminal of the DC source. Each of the first and second interphase reactors has first and second terminals at the other end thereof. Connected between the first terminals of the first and second interphase reactors is a first inverter comprising three main valves on each side of the positive and negative terminals, i.e., a total of six main valves each having a control gate and forming a first three-phase bridge. Also connected between the second terminals of the first and second interphase reactors is a second inverter comprising three main valves arranged on each side of the positive and negative terminals, i.e., a total of six main valves each having a control gate and forming a second three-phase bridge.

Abstract: An inverter system including a controlled direct current (d.c.) power source for providing a variable d.c. voltage to a variable output frequency inverter circuit by way of a suitable d.c. link, includes suitable circuitry for detecting a commutation fault or shoot-through condition within the inverter circuit and for taking appropriate remedial action to correct such condition. The shoot-through condition is determined as a function of the d.c. input current to the inverter circuit, the output alternating current (a.c.) of the inverter circuit and the extant condition of the load. In the particular embodiment of the invention illustrated, the load is an a.c. motor and the load condition sensed is whether the motor is in the running or idle mode of operation.

Abstract: A missed commutation detection circuit for use with a power inverter circuit which employs optically isolated gates to provide signals indicative of the state of a pair of SCR power switching devices. The gates are connected to combine the signals via a NOR logic arrangement to generate a missed commutation control signal whenever both of the SCR's are concurrently in a conductive or unblocked condition. The commutation control signal thus generated feeds a one-shot multivibrator which generates an isolation signal for a preselected time period. The isolation signal opens a normally closed current isolation switch connected intermediate the DC input bus and the inverter SCR's which cuts off current to the SCR's permitting them to return to their blocking state. After the duration of the isolation signal from the one shot, the isolation switch is again closed and the circuit is permitted to attempt normal operation.

Abstract: An inverter for diagnostic X-ray equipment, comprising a thyristor bridge with an input diagonal connected in series with two commutating inductances across a DC power supply, is provided with a start-stop circuit which includes an ancillary thyristor connected in series with a diode and a current-limiting impedance across one of the bridge arms. On start-up, the ancillary thyristor is triggered simultaneously with the diagonally opposite bridge thyristor in order to connect the current-limiting impedance in series with the AC output diagonal of the bridge during the first half-period; for a quick cutoff, the ancillary thyristor and the associated bridge thyristor are turned on together whereby two previously charged quenching capacitors, one of them included in the start-stop circuit, are discharged through the commutating inductance in series with the associated bridge arm to terminate conduction in another bridge arm fed through the same commutating inductance.

Abstract: A circuit and method is disclosed for detecting the presence of charges of appropriate magnitude and polarity on commutating capacitors of an inverter that converts a DC output current to a drive current of variable magnitude and frequency for driving an AC electric motor producing controllable rotation and torque. The presence of charges of appropriate magnitude and polarity is detected by measuring the voltages across the conduction controlled rectifying devices in the inverter. In addition, the existence of conduction controlled rectifying devices in the conducting state is determined by measuring the magnitude of the DC output current. An output signal is generated when the charges of appropriate magnitude and polarity are detected, which output signal is effective to allow the inverter to generate normal drive current.

Abstract: An inverter system including a controlled direct current (d.c.) power source for providing a variable d.c. voltage to a variable output frequency inverter circuit by way of a suitable d.c. link, includes suitable circuitry for detecting a commutation fault or shoot-through condition within the inverter circuit and for taking appropriate remedial action to correct such condition. The shoot-through condition is determined as a function of the d.c. input current to the inverter circuit and the output alternating current (a.c.) of the inverter circuit. This determination is achieved by comparing signals representing the two currents at a fixed ratio, other than unity (e.g, at a fixed percentage of one to the other) so that the actual margin increases as the currents increase. Preferably a bias is also included in the comparison function so that a minimum differential is always required before a shoot-through determination is made.