Abstract: An integrated circuit with magnetic memory has a silicon transistor layer, at least one magnetic memory layer, and a metal routing layer. The silicon transistor layer is arranged to generate several logic operation functions. The magnetic memory layer is arranged to store the data required by the logic operation functions. The metal routing layer has several conducting lines to transmit the data between the silicon transistor layer and the magnetic memory layer.

Abstract: A magnetoresistive random access memory (MRAM) device includes a memory cell corresponding to one read bit line, one read word line, one write word line, and two or more write bit lines. The memory cell includes a first memory unit and a second memory unit each corresponding to a respective write bit line. Each of the first and second memory units comprises: a free magnetic region having a first easy axis, a pinned magnetic region having a second easy axis, and a tunneling barrier between the free magnetic region and the pinned magnetic region.

Abstract: A magnetic tunnel junction device includes a magnetically programmable free magnetic layer. The free magnetic layer includes a lamination of at least two ferromagnetic layers and at least one intermediate layer interposed between the at least two ferromagnetic layers.

Abstract: A magnetic memory has a first, a second and a third magnetic transistor. The first magnetic transistor has a first magnetic section and a second magnetic section, wherein the first magnetic section couples to a high voltage end. The second magnetic transistor has a third magnetic section and a fourth magnetic section, wherein the third magnetic section couples to a low voltage end, and the fourth magnetic section couples to the second magnetic section of the first magnetic transistor. The third magnetic transistor has a fifth magnetic section and a sixth magnetic section, wherein the fifth magnetic section couples with the second magnetic section and the fourth magnetic section together, and the sixth magnetic section couples to an input/output end.

Abstract: Flags are formed to respectively correspond to memory cell groups each including volatile memory cells. Each flag indicates as a set state that the memory cells store data in a second memory mode. In a changing operation of changing from a first memory mode in which data is independently retained by each memory cell to a second memory mode in which same data are retained in the memory cells of each memory cell group, each flag is reset in response to the first access to the corresponding memory cell group. Therefore, only the first access is made in the second memory mode in each memory cell group. The memory cells are accessed in a mode according to the flag in the changing operation, thereby allowing a system managing the semiconductor memory to freely access the memory cells even during the changing operation. Consequently, a practical changing time can be eliminated.

Abstract: Various apparatuses and methods are shown in which an integrated circuit includes a dual-polarity non-volatile memory cell and a test circuit. The test circuit has a bias voltage generator and a first switch. The bias voltage generator couples to the dual-polarity non-volatile memory cell via the first switch.

Abstract: A memory has an array made up of transistors that have two charge storage regions between the channel and control gate. Each bit is made up of two charge storage regions that are from different transistors. A bit is written by first erasing all of the storage locations and then writing one of the charge storage locations that make up the bit. A pair of charge storage locations, one erased and the other programmed, is identified for each bit. The logic state of the bit is read by comparing the charge stored in the two charge storage locations that make up the bit. This comparison is achieved by generating signals representative of the charge present in the two charge storage locations. These signals are then coupled to a sense amplifier that functions as a comparator. This avoids many problems that accompany comparisons to a fixed reference.

Abstract: Extensible/retractable and storable portable memory device including a main body and a sheath. The main body has an adapter at one end. One end of the sheath is formed with an opening for fitting the adapter end of the main body. The other end of the sheath is formed with a through hole through which the adapter can outward protrude. Two sides of the sheath are formed with inward projecting stop boards. The middle portions of two sides of the main body are respectively formed with two lateral projecting blocks. The stop boards stop the lateral projecting blocks from outward sliding so that the main body is restricted to relatively slide within the sheath to extend the adapter out of the sheath or retract the adapter therein and locate the adapter in a predetermined position. Therefore, the memory device can be easily used and carried.

Abstract: An alpha particle striking the cell of a DRAM bit can destroy stored charge, resulting in a single bit soft error. A DRAM architecture is described that circumvents this problem by storing every DRAM bit redundantly in two cells. If a stored charge is represented by a logic 1, then when reading a DRAM bit, if either of it's cells is storing charge then the bit is a logic 1. Only if both cells of a bit have no charge is the bit a logic 0.

Abstract: A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a nonconducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two bit EEPROM device. The nonconducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. A left and a right bit are stored in physically different areas of the charge trapping layer, near left and right regions of the memory cell, respectively.

Abstract: A magnetic random access memory device (10) has a plurality of pairs of memory cells (21a,21b), a column decoder (31), a row decoder (32), and a comparator (60). The pair of memory cells (21a,21b) is designated by column decoder (31) and row decoder (32) in response to a memory address. Complementary bits ("0" and "1") are stored in the pair of memory cells (21a,21b). When the state in the pair of memory cell (21a,21b) is read, both bits in the pair of memory cells (21a,21b) are compared to produce an output at one read cycle time to a bit line (70). This memory device omits a conventional auto-zeroing step so that a high speed MRAM device can be attained.

Abstract: Anticorrosion magneto-optical recording medium is disclosed. The magneto-optical recording medium comprises a recording layer formed of an amorphous alloy of transition metal and rare-earth metal such as Tb--Fe or Tb--FeCo. On the recording layer, there are provided a transition metal layer such as FeCoCr alloy layer and a rare-earth metal layer such as Tb, in this order. Selective oxidation of rare-earth metal in the recording layer is effectively avoided by the existance of the layers.

Abstract: A fault-tolerant random access memory for use in fault-tolerant computers. It comprises a plurality of memory chips each comprising a plurality of on-line testable and correctable memory cells disposed in rows and columns for holding individually addressable binary bits and provision for error detection incorporated into each memory cell for outputting an error signal whenever a transient error occurs therein. Each of the memory cells comprises a pair memory sub-cells for simultaneously receiving and holding a common binary data bit written to the memory cell and the error detection provision comprises comparator logic for continuously sensing and comparing the contents of the memory sub-cells to one another and for outputting the error signal whenever the contents do not match. In accordance with one feature of the invention, the memory systematically searches for an error in response to an error signal and corrects the error found by the search.

Abstract: The sense voltages of an NDRO core memory including two cores per memory bit are increased by using a "soft write" technique wherein one of the two ferrite cores of each memory bit is written into by a smaller write current than the other. This results in a steeper slope toward the knee of the lower part of the hysteresis characteristic of the first core. The steeper slope results in a larger induced voltage for the first core. This increases the difference between the induced voltages of the two cores, thereby increasing the sense voltage to be detected by the sense circuitry.