Abstract: Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TS V to at least one of a test input and a test evaluation circuit.

Abstract: A memory device includes a stack of circuit layers, each circuit layer having formed thereon a memory circuit configured to store data and a redundant resources circuit configured to provide redundant circuitry to correct defective circuitry on at least one memory circuit formed on at least one layer in the stack. The redundant resources circuit includes a partial bank of redundant memory cells, wherein an aggregation of the partial bank of redundant memory cells in each of the circuit layers of the stack includes at least one full bank of redundant memory cells and wherein the redundant resources circuit is configured to replace at least one defective bank of memory cells formed on any of the circuit layers in the stack with at least a portion of the partial bank of redundant memory cells formed on any of the circuit layers in the stack.

Abstract: A thermally assisted magnetoresistive random access memory cell, a corresponding array, and a method for fabricating the array. An example cell includes a first metal layer, a second metal layer, an interlayer, a first magnetic stack, and a first non-magnetic via. The first metal layer includes a pad and a first metal line, with the pad not in direct contact with the first metal line. The second metal layer includes a second metal line and a metal strap. The second metal line is perpendicular to the first metal line and not in contact with the metal strap. The interlayer is located between the first and second metal layers. The first metal line is not in direct contact with the interlayer. The first magnetic stack is in direct contact with the interlayer and the metal strap. The first non-magnetic via is in direct contact with the pad and the metal strap.

Abstract: An integrated circuit includes: a memory controller configured to determine whether a memory cell included in a semiconductor memory device is defective or not and extract a fail address having positional information of the defective memory cell, in a test mode; and a fail address storage unit configured to store the fail address.

Abstract: A memory array with graded resistance lines includes a first set of lines intersecting a second set of lines. A line from one of the sets of lines includes a graded resistance along a length of the line.

Abstract: A memory device includes a memory cell array including a NAND flash cell portion including a plurality of first columns of serially-connected flash memory cells and a non-volatile random access memory (NVRAM) cell portion including a plurality of second columns of NVRAM cells. The flash memory cells and the NVRAM cells are arranged such that respective word lines are connected to flash memory cells and NVRAM cells in each of respective rows, which may correspond to page units including flash memory cells and NVRAM cells.

Abstract: An optical waveguide for a touch panel which obviates a need for positioning a light receiving optical waveguide portion. The touch panel optical waveguide A1 which is to be fitted around a periphery of a display screen of a display of a touch panel, the optical waveguide comprising light emitting cores 3 each having an end face provided on one of opposed portions disposed in opposed relation on opposite sides of the display screen of the display, and light receiving cores 3 each having an end face provided on the other of the opposed portions, wherein the cores 3 are provided on a surface of a planar frame-shaped under-cladding layer (frame) 2 having a shape conformable to the periphery of the display screen of the display.

Abstract: According to the semiconductor memory device of this invention, an XP type MRAM cell array and an STr type MRAM cell array are formed on a single chip. The XP type MRAM cell array is laid over the STr type MRAM cell array to form a layered structure. The STr type MRAM cell array serves as a work memory area, while the XP type MRAM cell array serves as a data storage area. A cell of the XP type MRAM cell array and a cell of the STr type MRAM cell array may be connected to a same bit-line. By passing predetermined current through the bit-line, and passing current through a first word-line connected to the cell of the XP type MRAM cell array, and through a second word-line connected to the cell of the STr type MRAM cell array, it is possible to simultaneously write data into the cells of the XP and STr type MRAM cell arrays.

Abstract: “A process for fabricating active and passive, polymer-based components for use in integrated optics. As a result of this process, active and passive optoelectronic components of a high quality having a high level of integration and high packing density are fabricated. A patternable polymer resist layer of a high quality is deposited onto an optoelectronic component. An etching mask is used in conjunction with a high-grade anisotropic deep etching to produce a pattern, which is filled with monomers through gas-phase or liquid-phase diffusion. The optical properties of the optical component can be selectively changed as a function of the type of monomers used for the diffusion, as well as of the temperature and application time. The process makes it possible to increase the packing density of future integrated monomode optics and simultaneously produce large quantities in a cost-effective manner.

Abstract: A closed flux magnetic memory cell has a ferromagnetic pinned structure and a ferromagnetic free structure. Data is stored by controlling the relative magnetization between the pinned and free structures. The free structure is formed as a horizontally extending toroid, or tube, that is insulated from the pinned structure. A first conductive line passes through the center of the free structure while a second conductive line is connected to the pinned structure. A third conductive line can be formed through the free structure. This line is insulated from the toroid and the first conductor. The third conductive line can also be located outside the free structure. In operation of one embodiment, the first and third conductive lines are used to control the magnetized direction of the free structure. A resistance between the first and second conductive lines defines the data stored in the memory cell.

Abstract: A closed flux magnetic memory cell has a ferromagnetic pinned structure and a ferromagnetic free structure. Data is stored by controlling the relative magnetization between the pinned and free structures. The free structure is formed as a horizontally extending toroid, or tube, that is insulated from the pinned structure. A first conductive line passes through the center of the free structure while a second conductive line is connected to the pinned structure. A third conductive line can be formed through the free structure. This line is insulated from the toroid and the first conductor. The third conductive line can also be located outside the free structure. In operation of one embodiment, the first and third conductive lines are used to control the magnetized direction of the free structure. A resistance between the first and second conductive lines defines the data stored in the memory cell.

Abstract: A chalcogenide material is formed to a first thickness over the first conductive electrode material. The chalcogenide material includes AxBy. A layer that includes a metal is formed to a second thickness over the chalcogenide material. The metal including layer defines some metal including layer transition thickness for the first thickness of the chalcogenide material such that when said transition thickness is met or exceeded, said metal including layer when diffused within said chalcogenide material transforms said chalcogenide material from an amorphous state to a crystalline state. The second thickness being less than but not within 10% of said transition thickness. The metal including layer is irradiated effective to break a chalcogenide bond of the chalcogenide material and diffuse at least some of the metal into the chalcogenide material.

Abstract: A high-speed real-time bi-linear interpolation apparatus is disclosed for scaling an old M.times.M' image into a new N.times.N' image by which the pixel value of a new pixel q(x', y') is interpolated from the pixel values of four immediately enclosing old pixels, p(x, y), p(x+1, y), p(x, y+1), and p(x+1, y+1). The fast bi-linear interpolation apparatus comprises: (a) a counter for obtaining the x-directional and y-directional pixel counts of the new pixel (x', y'), designated as n and n', respectively; (b) an accumulator for calculating the x-directional and y-directional pixel counts of the he old pixel (x, y), designated as m and m', respectively; (c) logic circuits associated with the accumulator means for calculating x-directional and y-directional interpolation parameters Acc and Acc', respectively, wherein Acc is the numerator of fraction after the division of (n.multidot.M.div.N), and Acc' is the numerator of fraction after the division (n'.multidot.M'.div.

Abstract: A magneto-optical recording medium on which rewriting is possible is composed of a substrate and a recording layer exhibiting perpendicular anisotropy formed thereon. The recording layer consists of at least a transition-metal layer and a rare-earth-metal layer, or at least two transition metal--rare earth metal alloy layers, which are alternately overlaid on each other, and each of the layers further contains a precious metal in an amount of 1 atom % to 10 atom %.