Abstract: To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The semiconductor device includes a word line divider, a memory cell, a first wiring, and a second wiring. The word line divider is electrically connected to the first wiring and the second wiring. The memory cell includes a first transistor with a dual-gate structure. A first gate of the first transistor is electrically connected to the first wiring, and a second gate of the first transistor is electrically connected to the second wiring. The word line divider supplies a high-level potential or a low-level potential to the first wiring and supplies a predetermined potential to the second wiring, whereby a threshold voltage of the first transistor is changed. With such a configuration, a semiconductor device that can reduce power consumption and retain data for a long time is driven.

Abstract: A semiconductor apparatus may include a receiver circuit and a termination circuit. The receiver circuit may be coupled to a receiving node, and configured to receive a signal transmitted through a signal transmission line. The termination circuit may be configured to be turned on to set a resistance value of the receiving node in a transition period of the signal, and turned off in a stabilization period of the signal.

Abstract: Memory devices are provided having a cross-point array of polymer junctions with individually-programmed conductances that can be reset. In one aspect, a memory device is provided. The memory device includes: bottom metal lines; top metal lines; and polymer junctions in between the bottom metal lines and the top metal lines, wherein the polymer junctions include an organic polymer doped with a spiropyran and an acid. A method of forming and a method of operating the memory device are also provided.

Abstract: A semiconductor device with a transistor having favorable electrical characteristics is provided. The semiconductor device has a memory circuit and a circuit that are over the same substrate. The memory circuit includes a capacitor, a first transistor, and a second transistor. A gate of the first transistor is electrically connected to the capacitor and one of a source and a drain of the second transistor. The circuit includes a third transistor and a fourth transistor that are electrically connected to each other in series. The first transistor and the third transistor each include an active layer including silicon, and the second transistor and the fourth transistor each include an active layer including an oxide semiconductor.

Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.

Abstract: A method and an apparatus for controlling current in an array cell is disclosed. The method includes applying a supply voltage to a first access point of a transistor, precharging a second access point of the transistor to a predetermined voltage, applying a control voltage to a third access point of the transistor, and discharging the second access point of the transistor to turn on the transistor which causes a current flow through the array cell connected to the transistor.

Abstract: A content addressable memory (CAM) device can include a plurality of CAM cells each formed within a cell area of a substrate. Each cell area can have a cell length dimension in a first direction parallel to a substrate surface. The CAM device can also include at least one common line comprising a contiguous region of the substrate doped to a first conductivity type and formed in a base semiconductor region doped to a second conductivity type. The common line can extend in the first direction for more than one cell length and can be commonly coupled to non-power supply connections to the plurality of CAM cells.

Abstract: A memory cell includes a true data node, a true pullup transistor, a complement data node and a complement pullup transistor. A true switching circuit selectively supplies a first or second supply voltage to a source of the true pullup transistor. A true bias switching circuit selectively supplies a third or fourth supply voltage to a body of the true pullup transistor. When writing a logic high data value to the true data storage node, a control circuit causes the true switching circuit to supply the second supply voltage and the true bias switching circuit to supply the third supply voltage. The second supply voltage is higher than the first supply voltage, and the fourth supply voltage is higher than the third supply voltage. A similar operation is performed with respect to the complement pullup transistor when writing a logic high data value to the complement data storage node.

Abstract: An SRAM has at least two sets of pass transistors for coupling at least two sets of bit lines to true and complement data nodes of an SRAM cell based on the assertion of at least two word lines. The cell includes two pull up transistors and two pull down transistors coupled to the true and complement data nodes. None of the pass transistors are implemented in an active area that includes a pull up transistor or a pull down transistor of the cell.

Abstract: High manufacturing yield is realized and variation in threshold voltage of each MOS transistor in a CMOS·SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. Threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is programmed into control memories according to results of determination. Levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS·SRAM are controlled to a predetermined error span. Body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.

Abstract: A SRAM memory element comprises an influencing element which sets the state of the memory cells within the memory element on start-up to defined values. These defined values are set at the design stage such that on start-up the volatile memory contains firmware or other data. Dependent upon the implementation of the influencing element, the values of stored in the memory cells may be fixed or may subsequently be overwritten during operation of the device. The memory cell may comprise two cross-coupled inverters and the influencing element comprises at least one transistor arranged to connect the input to one of the inverters to ground or a power supply rail when voltage is applied to a controlling node of the transistor.

Abstract: A random access memory circuit includes a plurality of pixels, each having a light sensitive area and a light blocking layer arranged over at least each of the light sensitive areas. In an alternative embodiment, the circuit includes a plurality of memory elements for storing data. Each memory element may comprise a bit node formed between a photodiode, having a light arranged over the photodiode, and a switching element, where data may be stored. The circuit may also include a plurality of reading and writing circuits for reading and writing data to and from the memory cells.

Abstract: In accordance with an embodiment, a semiconductor device includes an SRAM cell on a substrate. The SRAM cell includes: first and second load transistors each having an n-type source region and a p-type drain region, first and second driver transistors each having a p-type source region and an n-type drain region, and first and second transfer transistors each having an n-type source region and a n-type drain region. The n-type source regions of the first and second load transistors, the n-type drain regions of the first and second driver transistors, and the n-type source regions and the n-type drain regions of the first and second transfer transistors are located in a region other than a region present between any two of the p-type drain regions of the first and second load transistors and the p-type source regions of the first and second driver transistors.

Abstract: Multi-gate metal-oxide-semiconductor (MOS) transistors and methods of operating such multi-gate MOS transistors are disclosed. In one embodiment, the multi-gate MOS transistor comprises a first gate associated with a first body factor and comprising a first gate electrode for applying a first gate voltage, and a second gate associated with a second body factor greater than or equal to the first body factor and comprising a second gate electrode for applying a second gate voltage. The multi-gate MOS transistor further comprises a body of semiconductor material between the first dielectric layer and the second dielectric layer, where the semiconductor body comprises a first channel region located close to the first dielectric layer and a second channel region located close to the second dielectric layer. The multi-gate MOS transistor still further comprises a source region and a drain region each having a conductivity type different from a conductivity type of the body.

Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body region and a gate disposed about a first portion of the body region. The device includes a source region adjoining a second portion of the body region, the second portion adjacent the first portion and separating the source region from the first portion. The device includes a drain region adjoining a third portion of the body region, the third portion adjacent the first portion and separating the drain region from the first portion, wherein the source and drain regions are opposing.

Abstract: High manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS.SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. The threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is respectively programmed into control memories according to the results of determination. The levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS.SRAM are controlled to a predetermined error span. A body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.

Abstract: Asymmetrical SRAM cells are improved by providing one or more of improved read stability and improved write performance and margin. A first inverter and a second inverter are cross-coupled and configured for selective coupling to true and complementary bit lines under control of read and write word lines. The first inverter is formed by a first, n-type, FET (NFET) and a second, p-type, FET (PFET). Process and/or technology approaches can be employed to adjust the relative strength of the FETS to obtain, for example, read margin, write margin, and/or write performance improvements.

Abstract: An array is formed by a plurality of cells, wherein each cell is formed by a bipolar junction selection transistor having a first, a second, and a control region. The cell includes a common region, forming the second regions of the selection transistors, and a plurality of shared control regions overlying the common region. Each shared control region forms the control regions of a plurality of adjacent selection transistors and accommodates the first regions of the plurality of adjacent selection transistors as well as contact portions of the shared control region. Blocks of adjacent selection transistors of the plurality of selection transistors share a contact portion and the first regions of a block of adjacent selection transistors are arranged along the shared control region between two contact portions.

Abstract: A memory device of SRAM type has a memory plan constituted by base memory cells organized in lines and in columns. Each cell of a column is connected between two bit lines which are precharged during a reading operation. Circuitry is provided for generating a precharge voltage of the bit lines which is less than a nominal supply voltage of the device.

Abstract: Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters.

Abstract: A content-addressable memory (“CAM”) architecture and method for reducing power consumption thereof are described. A CAM cell array includes CAM cells, each of which includes two thyristor-based storage elements. Each thyristor-based storage element of the CAM cells has a control gate, an anode, and a cathode for providing control gates, anodes, and cathodes of the CAM cells. The CAM cell array further includes matchlines directly coupled to the cathodes of the CAM cells; searchlines directly coupled to the anodes of the CAM cell; and gatelines coupled to the control gates of the CAM cells.

Abstract: Methods and systems for embodiments of a 9T memory cell, memory devices which utilize such 9T memory cells and the creation of embodiments of such memory devices are disclosed. More specifically, an embodiment of a 9T memory cell may comprise a 6T memory cell portion and a 3T read port. Additionally, in one embodiment, a memory which utilizes 9T memory cells may be made by from a grid comprising columns and rows of transistors formed according to a layout for 6T memory cells.

Abstract: A SRAM memory cell including two inverters and a plurality of switches is provided. The SRAM cell is manufactured in a technology offering N/P shunt capabilities and the inputs of the inverters are connected to at least one pair of bit lines (BLa, BLa/; BLb, BLb/) via two of the switches. The switches are controlled by a signal word line (WLa, WLb). Each inverter includes a first transistor (MN0, MN1) of a first conductivity type and a second transistor (MP0, MP1) of a second conductivity type. Each switch includes at least a third transistor (MN2, MN3) of the first conductivity type, characterized in that the two transistors (MP0, MP1) of the second conductivity type in the inverters are arranged in two opposite end regions of the memory cell, respectively.

Abstract: A method and circuit for implementing an enhanced static random access memory (SRAM) read and write performance ring oscillator, and a design structure on which the subject circuit resides are provided. A plurality of SRAM base blocks is connected together in a chain. Each of the plurality of SRAM base blocks includes a SRAM cell, such as an eight-transistor (8T) static random access memory (SRAM) cell, and a local evaluation block coupled to the SRAM cell. The SRAM cell includes independent left wordline input and right wordline input. The SRAM cell includes a read wordline connected high, and a true and complement write bitline pair connected low. In the local evaluation circuit, one input of a NAND gate receiving the read bitline input is connected high. A control signal is combined with an inverted feedback signal to start and stop the ring oscillator.

Abstract: An asymmetric Static Random Access Memory (SRAM) cell is provided. The SRAM cell comprises first and second storage nodes, drive transistors and access transistors. The first and second storage nodes are configured to store complementary voltages. The drive transistors are configured to selectively couple each of the first and second storage nodes to corresponding high and low voltage power supplies, and maintain a first logic state through a feedback loop. The access transistors are configured to selectively couple each of the first and second storage nodes to corresponding first and second bit-lines and maintain a second logic state through relative transistor leakage currents. A method for reading from and writing to the SRAM cell are also provided.

Abstract: An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a single read bit line transistor in series with the word line transistor, when selected, reads the content of the cell.

Abstract: High manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS•SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. The threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is respectively programmed into control memories according to the results of determination. The levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS•SRAM are controlled to a predetermined error span. A body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.

Abstract: A semiconductor device whose operation frequency and power supply voltage are dynamically controlled according to a load subjected to a process to be performed is disclosed. The semiconductor device includes a memory cell array having SRAM cells arranged in an array form, word lines connected to the SRAM cells for respective rows, a row decoder which selects the word lines one by one during normal operation and multi-select word lines which are not adjacent to each other during low-voltage operation, a load circuit which sets the level of the selected word line to potential lower than power supply voltage, and a controller which controls the row decoder and load circuit to selectively control selection of the word lines and the load circuit.

Abstract: Techniques are provided for a computer-readable medium encoding a memory using a back-gate controlled asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An encoded inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop.

Abstract: A cache memory having valid bits, where a circuit configuration in a memory cell of a valid bit is improved so as to perform invalidation at high speed. The invention provides a cache memory including a memory cell that has a function to perform invalidation at high speed. One mode of the invention is a semiconductor device including a memory cell of a valid bit, where two inverters are connected in series to form a loop, a drain of an N-channel transistor is connected to an output signal line of one of the inverters, a gate thereof is connected to a reset signal line of a CPU, and a source thereof is connected to a ground line. The initial value of the memory cell is determined by inputting a reset signal of the CPU to the gate.

Abstract: Structures and methods are provided for SRAM cells having a novel, non-volatile floating gate transistor, e.g. a non-volatile memory component, within the cell which can be programmed to provide the SRAM cell with a definitive asymmetry so that the cell always starts in a particular state. The SRAM cells include a pair of cross coupled transistors. At least one of the cross coupled transistors includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator.

Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: Techniques are provided for asymmetrical SRAM cells which can be improved, for example, by providing one or more of improved read stability and improved write performance and margin. A first inverter and a second inverter are cross-coupled and configured for selective coupling to true and complementary bit lines under control of read and write word lines. The first inverter is formed by a first, n-type, FET (NFET) and a second, p-type, FET (PFET). Process and/or technology approaches can be employed to adjust the relative strength of the FETS to obtain, for example, read margin, write margin, and/or write performance improvements.

Abstract: Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters.

Abstract: An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a single read bit line transistor in series with the word line transistor, when selected, reads the content of the cell.

Abstract: Floating plate memory includes a diode as an access device, wherein the diode has four terminals, the first terminal serves as a word line, the second terminal serves as a storage node, the third terminal is floating, and the fourth terminal serves as a bit line; a floating plate capacitor serves as a storage device, wherein the capacitor includes three plates, the first plate is connected to the storage node, the second plate is floating and the third plate is connected to a plate line; when write, the diode determines whether the storage node is coupled or not by raising the plate line; when read, the diode serves as a sense amplifier to detect the storage node voltage whether it is forward bias or not, and the diode sends binary results to a data latch including a current mirror; and the memory is formed on the bulk and SOI wafer.

Abstract: Half cells of single-event-upset-tolerant memory cells are offset by at least two rows in a memory array. Offsetting the half cells separates them to avoid simultaneous damage to both half cells from a high-energy particle that could otherwise alter multiple nodes and corrupt the data state of the memory cell. Separating the half cells by at least two rows avoids corruption that could occur if diagonally arranged half cells were hit by a high-energy particle. In a particular embodiment, offset half cells are used at the top and bottom, respectively, of two adjacent columns of memory half cells.

Abstract: Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity most of the time, and high speed during writing to the memory cell. Alternatively, inductors coupled between inverters of a latch may be used.

Abstract: Three-state binary adders are disclosed for use in pipelined analog-to-digital converters. According to one advantageous embodiment, a three-state binary adder is provided for use in a digital signal processing system. The three-state binary adder is operable to generate binary codes consisting of three states, namely, “00”, “01” and “10.

Abstract: The DRAM drives a bit line pair connected to a read column select gate and a write column select line connected to a write column select gate by a power supply voltage for an array, and drives a read column select line connected to a read column select gate and write data line pair connected to a write column select gate by a power supply voltage for a peripheral circuitry. Hence, even when one power supply voltage becomes high and another power supply voltage becomes low at the same time, the timing margin and operation margin can sufficiently be secured. Thus, a semiconductor memory device allowing a stable high-speed operation with large timing margin and operation margin will be achieved.

Abstract: Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity most of the time, and high speed during writing to the memory cell. Alternatively, inductors coupled between inverters of a latch may be used.

Abstract: An information storage device which has a layer containing such bistable molecules that the molecular structure reversibly changes due to an isomerization reaction, at least one reaction of the isomerization reaction is caused by electric carrier injection, and the electric characteristics change as between before and after the isomerization reaction.

Abstract: A synchronized mirror delay circuit is used to generate an internal clock signal from an external clock signal applied to the synchronized mirror delay. The internal clock signal is then coupled through a clock tree, and a feedback signal is generated that is indicative of the propagation delay of the internal clock signal through the clock tree. The feedback signal is applied to the synchronized mirror delay to allow the synchronized mirror delay to delay the internal clock signal by a delay interval that compensates for the propagation delay in the clock tree. A lock detector may be used to initially generate the internal clock signal directly from the external clock signal. A fine delay circuit that delays the internal clock signal in relatively fine increments may be used to couple the internal clock signal to the clock tree.

Abstract: A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter includes a NMOS transistor and a PMOS transistor, and an inverter includes a NMOS transistor and a PMOS transistor. The inverters are subjected to cross section. The NMOS transistor is formed within a P well region, and NMOS transistor is formed within a P well region. The P well regions are oppositely disposed with an N well region interposed therebetween.

Abstract: An SRAM cell includes six transistors and two variable resistors. A first pair of transistors form a first inverter, while a second pair of transistors form a second inverter. The remaining two transistors are pass transistors. The inverters are cross-coupled, through the variable resistors, to form a flip flop circuit which stores binary logic states. The variable resistors are formed by doping a portion of a polysilicon layer. Above the doped polysilicon resistor is a thin oxide layer. Disposed above the oxide layer is a thin layer of aluminum or polysilicon, which is connected by metallization. When a positive voltage is applied to the metallization, electrons accumulate in the doped polysilicon resistor, thereby lowering the resistance value of the polysilicon region. This voltage is applied to the interconnect during a write-in cycle, when it is desired to write data to the SRAM cell. The lowered resistance value of the polysilicon resistor allows for relatively fast write-in times for the SRAM cell.

Abstract: A combinatorial chemistry bead that includes an electromagnetic spectral emitter that radiates a distinct electromagnetic code for each bead that uniquely identifies each bead, a terminal apparatus for receiving the electromagnetic code from each bead, and a method for performing combinatorial synthesis using a bead that transmits a distinct electromagnetic code. The invention includes a large number of spectrally narrowed light emitting mechanisms for generating distinct optical codes.

Abstract: A SRAM cell is disclosed. The SRAM cell comprises: a first inverter having an input and an output; a second inverter having an input and an output, the output of the second inverter capacitively coupled to the input of the first inverter, the input of the second inverter capacitively coupled to the output of the first inverter; a first access transistor controlled by a wordline and connected between the output of the first inverter and a bitline; and a second access transistor controlled by the wordline and connected between the output of the second inverter and a complement to the bitline.

Abstract: Memory cells which are adjacent to each other along a column direction share a bipolar transistor driving the potential level of a corresponding bit line. Other memory cells which are adjacent to each other in the column direction share another bipolar transistor driving the potential level of another corresponding bit line. Each bipolar transistor drives the potential level of the corresponding bit line in response to storage information of a selected memory cell, whereby data can be read at a high speed with a low power supply voltage.

Abstract: A semiconductor memory has bit lines, word lines, ground lines, and memory cells. The bit lines intersect the word and ground lines, to form intersections where the memory cells are arranged, respectively. Each of the memory cells consists of a double-emitter resonance-tunnel-hot-electron transistor. This transistor has a collector, a first emitter, and a second emitter. Each base-emitter junction of the transistor has an N-shaped negative differential current-voltage characteristic that shows a relatively small gain up to a peak current and a relatively large gain after a valley current. The transistor has a resonance tunnel barrier and a collector barrier so that most of electrons injected from a first level are reflected by the collector barrier, to provide no collector current, and electrons from a second level or electrons thermally excited pass over the collector barrier, to provide a collector current. The first emitter of each transistor is connected to a corresponding one of the ground lines.

Abstract: A semiconductor memory device equipped with a flash-clear function has a plurality of flip-flop type memory cells each of which is formed by a first multi-emitter transistor and a second multi-emitter transistor, a clear line and a switching circuit. Each of the memory cells is connected between a word top line and a word bottom line. The second multi-emitter transistor has emitter nodes the number of which is smaller than that of emitter nodes of the first multi-emitter transistor. Some of the emitter nodes of the first multi-emitter transistor are connected to the clear line. Through the switching circuit, a current source is selectively connected to the word bottom line and the clear line. Since the first multi-emitter transistor is controlled by the clear line, the content of the same data can easily be written into a plurality of memory cells without such memory cells being caused to change their characteristics.