Abstract: An array of conductive lines for MRAM circuits wherein at least one set of mutually parallel conductive traces is tilted with respect to being perpendicular with a corresponding set of mutually parallel conductive traces wherein individual conductive traces within the sets intersect adjacent individual MRAM cells and wherein the tilting of the at least one set of conductive traces acts to induce both a vertical and horizontal component of a magnetic field such that the net vector addition of magnetic fields induced by the sets of conductive traces is greater than the untilted or perpendicular configuration so as to induce a greater net magnetic field to effect more reliable switching of the underlying MRAM cells. The tilted array also enables reducing the current supplied by the conductive traces while maintaining a comparable net magnetic field to the untilted configuration.

Abstract: A memory device according to the present invention includes a memory cell array including a plurality of memory cells arranged therein, the memory cell array being divided into a plurality of regions each selectable independently of the others as an object for data writing, and further includes a plurality of current supply sections provided correspondingly to the plurality of regions, respectively. Each of the plurality of current supply sections, when a corresponding region of the plurality of regions is selected as an object for data writing, is activated to supply a data write current to the corresponding region and each of the plurality of regions includes a plurality of write select lines provided correspondingly to predetermined units of the plurality of memory cells. The plurality of write select lines are selectively supplied with the data write current from a corresponding one of the plurality of current supply sections.

Abstract: A magnetic RAM (MRAM) using a thermo-magnetic spontaneous Hall effect includes a MOS transistor formed on a substrate; a heating layer formed above the MOS transistor and connected to a source region of the MOS transistor; a memory layer having a data write area to which data is written, the data write area being formed on the heating means; a bit line formed on the data write area; an upper insulating film formed on the bit line and the memory layer; and a write line formed on the upper insulating film so that a magnetic field necessary for writing data is generated in at least the data write area of the memory layer. The MRAM writes or reads data using the fact that a spontaneous Hall voltage greatly differs according to the magnetization state of a memory layer, thereby providing the device a high data sensing margin.

Abstract: A chalcogenide material is formed to a first thickness over the first conductive electrode material. The chalcogenide material includes AxBy. A layer that includes a metal is formed to a second thickness over the chalcogenide material. The metal including layer defines some metal including layer transition thickness for the first thickness of the chalcogenide material such that when said transition thickness is met or exceeded, said metal including layer when diffused within said chalcogenide material transforms said chalcogenide material from an amorphous state to a crystalline state. The second thickness being less than but not within 10% of said transition thickness. The metal including layer is irradiated effective to break a chalcogenide bond of the chalcogenide material and diffuse at least some of the metal into the chalcogenide material.

Abstract: A hybrid magnetic—semiconductor structure can be used as a memory element for the nonvolatile storage of digital information, as well as in other environments, including for example logic applications for performing digital combinational tasks, or a magnetic field sensor. The hybrid device uses ferromagnetic materials for implementing a variable spin resistance. The ferromagnetic layers are fabricated to permit the device to have two stable magnetization states, parallel and antiparallel. In the “on” state the device has two settable, stable resistance states determined by the relative orientation of the magnetizations of the ferromagnetic layers. An external magnetic field can change the magnetization state of the device by orienting the magnetization of the ferromagnetic layers to be parallel or antiparallel, thus changing the resistance of the device to a current of spin polarized electrons.

Abstract: A new nonvolatile hybrid memory cell stacked architecture is provided. The cells are comprised of magnetic spin storage elements stacked on top of each other on a silicon substrate, as well as one or two semiconductor FET isolation elements.

Abstract: A new nonvolatile hybrid memory cell is provided. The cell is comprised of a magnetic spin storage element and one or two semiconductor FET isolation elements. The magnetic spin storage element is an electron spin-based memory element situated on a silicon based substrate and includes a first ferromagnetic layer with a changeable magnetization state, a second ferromagnetic layer with a non-changeable magnetization state, a base layer situated between said first ferromagnetic layer and said second ferromagnetic layer, and a low transmission barrier. The low transmission barrier can be used to adjust a relative base resistance/transimpedance relationship, and thus configure an offset of the device to give a range of outputs ranging from bipolar to unipolar.

Abstract: A method of making a nonvolatile hybrid memory cell is provided. The cell is formed from of a magnetic spin storage element and one or two semiconductor FET isolation elements. The magnetic spin storage element is an electron spin-based memory element situated on a silicon based substrate and includes a first ferromagnetic layer with a changeable magnetization state, a second ferromagnetic layer with a non-changeable magnetization state, and a base layer situated between said first ferromagnetic layer and said second ferromagnetic layer. The base layer is a material having electron levels that are not significantly affected by an electron spin, and can include aluminum.

Abstract: A new nonvolatile hybrid memory cell is provided. The cell is comprised of a magnetic spin storage element and one or two semiconductor FET isolation elements. The magnetic spin storage element is an electron spin-based memory element situated on a silicon based substrate and includes a first ferromagnetic layer with a changeable magnetization state, a second ferromagnetic layer with a non-changeable magnetization state, and a base layer situated between said first ferromagnetic layer and said second ferromagnetic layer. The base layer is a material having electron levels that are not significantly affected by an electron spin.

Abstract: A hybrid memory device combines a ferromagnetic layer and a Hall Effect device. The ferromagnetic layer is magnetically coupled to a portion of a Hall plate, and when such plate is appropriately biased, a Hall Effect signal can be generated whose value is directly related to the magnetization state of the ferromagnetic layer. The magnetization state of the ferromagnetic layer can be set to correspond to different values of a data item to be stored in the hybrid memory device. The magnetization state is non-volatile, and a write circuit can be coupled to the ferromagnetic layer to reset or change the magnetization state to a different value. The write circuit uses a pair of inductively coupled write wires in each row and column, which are each given a signal with an amplitude approximately ½ of that required to change the state of the ferromagnetic layer.

Abstract: A current drive circuit operates receiving higher voltage than in a waiting mode at source terminal of a P-channel first driver transistor, when supplying a current to a node connected to a load circuit. In accordance with the rising source potential of the first driver transistor, the gate potential output to the first driver transistor by a gate potential control circuit rises. When the first and second driver transistors are off, a precharge circuit configured with a P-channel MOS transistor precharges the node to a prescribed potential. As a result, the current drive circuit is provided with increased reliability of the gate insulating films of the driver transistors without decreasing the driving current.

Abstract: A method of creating a memory circuit preferably includes (1) forming a first plurality of select-lines in a plane substantially parallel to a substrate, (2) forming a second plurality of select-lines in a plane substantially parallel to the substrate, where the second plurality of select-lines is divided into first and second groups, where the first group is formed in a direction normal to that of the first plurality of select-lines and the second group is formed in a direction substantially diagonal to that of the first group, (3) forming a plurality of pillars normal to the substrate, and (4) forming an array of memory cells, each memory cell being respectively coupled to a pillar and one of each of said first and second pluralities of select-lines.

Abstract: A cubic memory array is fabricated on a substrate having a planar surface. The cubic memory array includes a plurality of first select-lines organized in more than one plane parallel to the planar surface. A plurality of second select-lines is formed in pillars disposed orthogonal to the planer surface of the substrate. A plurality of memory cells are respectively coupled to the plurality of first and plurality of second select-lines.

Abstract: A nonvolatile ferromagnetic RAM device which is capable of reading the data stored in each magnet quickly and efficiently utilizing a minimal number of components. Specifically there is a nonvolatile ferromagnetic RAM which is capable of reading the data stored in each magnetic bit. The ferromagnetic memory cell, comprising of a base (19) that is oriented in a horizontal plane. There is also a bit (3), made of a ferromagnetic material, having: a height that is oriented perpendicular to the horizontal plane of the base, and a polarity that can be directed along the height. Additionally, there is a sense line (1), positioned proximate the bit (3) sufficient to detect the directed polarity of the bit; and a write line (2), positioned proximate the bit sufficient to direct the polarity of the bit.

Abstract: A ferromagnetic thin-film based digital memory having a plurality of bit structures interconnected with manipulation circuitry having a plurality of transistors so that each bit structure has transistors electrically coupled thereto that selectively substantially prevents current in at least one direction along a current path through that bit structure and permits selecting a direction of current flow through the bit structure if current is permitted to be established therein. A bit structure has a nonmagnetic intermediate layer with two major surfaces on opposite sides thereof and a memory film of an anisotropic ferromagnetic material on each of the intermediate layer major surfaces with an electrically insulative intermediate layer is provided on the memory film on which a magnetization reference layer is provided having a fixed magnetization direction.

Abstract: A magnetic functional device allowing magnetization switching at a high speed even if the size of a magnetic substance is made finer on the sub-micron order. The magnetic functional device includes an information carrier layer formed by a magnetic substance; and a strain-imparting layer (such as piezoelectric layer) formed below the information layer and operably configured to impart a drive force to change the direction of a magnetization vector lying in a first plane of the information carrier thereby processing binary or more information by magnetization directions of the information carrier layer; wherein the drive force is applied in pulse to the information carrier layer in a direction nearly perpendicular to the first plane in which lies the magnetization vector of the information carrier layer when the magnetization vector is in an initial state before the application of the drive force. An effective field derived from a magnetic anisotropy or exchange interaction is used as the drive force.

Abstract: A hybrid memory device combines a ferromagnetic layer and a Hall Effect device. The ferromagnetic layer is magnetically coupled to a portion of a Hall plate, and when such plate is appropriately biased, a Hall Effect signal can be generated whose value is directly related to the magnetization state of the ferromagnetic layer. The magnetization state of the ferromagnetic layer can be set to correspond to different values of a data item to be stored in the hybrid memory device. The magnetization state is non-volatile, and a write circuit can be coupled to the ferromagnetic layer to reset or change the magnetization state to a different value. The memory device can also be fabricated to include an associated transistor (or other suitable switch) that functions as an isolation element to reduce cross-talk and as a selector for the output of the device when such is used in a memory array.

Abstract: A hybrid memory device combines a ferromagnetic layer and a Hall Effect device. The ferromagnetic layer is magnetically coupled to a portion of a Hall plate, and when such plate is appropriately biased, a Hall Effect signal can be generated whose value is directly related to the magnetization state of the ferromagnetic layer. The magnetization state of the ferromagnetic layer can be set to correspond to different values of a data item to be stored in the hybrid memory device. The magnetization state is non-volatile, and a write circuit can be coupled to the ferromagnetic layer to reset or change the magnetization state to a different value. The memory device can also be fabricated to include an associated transistor (or other suitable switch) that functions as an isolation element to reduce cross-talk and as a selector for the output of the device when such is used in a memory array.

Abstract: A nonvolatile ferromagnetic RAM device which is capable of reading the data stored in each magnet quickly and efficiently utilizing a minimal number of components. Specifically there is a nonvolatile ferromagnetic RAM which is capable of reading the data stored in each magnetic bit. The ferromagnetic memory cell, comprising of a base (19) that is oriented in a horizontal plane. There is also a bit (3), made of a ferromagnetic material, having: a height that is oriented perpendicular to the horizontal plane of the base, and a polarity that can be directed along the height. Additionally, there is a sense line (1), positioned proximate the bit (3) sufficient to detect the directed polarity of the bit; and a write line (2), positioned proximate the bit sufficient to direct the polarity of the bit.

Abstract: A non-volatile RAM device is disclosed which utilizes a plurality of ferromagnetic bits (6) each surrounded by a coil of a write line (13) for directing the remnant polarity thereof is disclosed. The direction of magnetic remnance in each bit (6) is dictated by the direction of a current induced into write line (13). Further, a magneto sensor (7) comprising a magneto resistor (1) coupled to a collector (2) is placed approximate each bit (6). The magneto resistor (1) is coupled to a control circuit (30) for receiving current. The current passing across magneto resistor (1) is biased in a direction either right or left of the original current flow direction. The collector is coupled to a sense line (4), which in turn, is coupled to an amplifier (12). When current flow is biased in the direction of the collector, the serial resistance of the magneto resistor will be decreased, and the sense line (4) will receive a high amount of current.

Abstract: A hybrid memory device combines a ferromagnetic layer and a Hall Effect device. The ferromagnetic layer is magnetically coupled to a portion of a Hall plate, and when such plate is appropriately biased, a Hall Effect signal can be generated whose value is directly related to the magnetization state of the ferromagnetic layer. The magnetization state of the ferromagnetic layer can be set to correspond to different values of a data item to be stored in the hybrid memory device. The magnetization state is non-volatile, and a write circuit can be coupled to the ferromagnetic layer to reset or change the magnetization state to a different value. The memory device can also be fabricated to include an associated transistor (or other suitable switch) that functions as an isolation element to reduce cross-talk and as a selector for the output of the device when such is used in a memory array.

Abstract: A symmetric magnetic tunnel device including first and second magnetic tunnel junctions each including a pinned magnetic layer, an insulating tunnel layer and a free magnetic layer stacked in parallel juxtaposition to allow tunneling of electrons through the insulating tunnel layer between the pinned and free magnetic layers. The first and second magnetic tunnel junctions positioned in parallel juxtaposition so as to form a continuous electron path through the first and second magnetic tunnel junctions and to provide a cell signal across the first and second magnetic tunnel junctions greater than a cell signal across each of the first and second magnetic tunnel junctions individually.

Abstract: A vertically integrated magnetic memory with Hall effect sensing or reading. It has a ferromagnetic structure with a nearly enclosed magnetic path, which is a vertical structure integrated on a chip. Each memory cell has a closed magnetic field that has high strength for a strong Hall effect. The magnet is a closed loop, robust reproducible magnet. A memory array of such cells uses little power in that only few cells need to draw the read current for a short time required to read the information. A silicon or GaAs chip implementation of the memory is one embodiment, among others, wherein the field required to saturate the electrons can be achieved without excessive power.

Abstract: A Magnetoresistive Random Access Memory (MRAM) device (10) and a method for manufacturing the MRAM device (10). The MRAM device (10) has a plurality of pairs of sense lines (21A, 21B, 22A, 22B, 23A, 23B, 24A, 24B), a plurality of pairs of memory cells (51A, 51B), and a plurality of word lines (31, 32, 33, 34). For two adjacent sense lines (21A, 22A), a first end of the first sense line (21A) is placed adjacent to a second end of the second sense line (22A) and a second end of the first sense line (21A) is placed adjacent to a first end of the second sense line (22A). Decoding transistors (82, 83, 84, 85, 86, 87, 88, 89) are connected to the second ends of the plurality of pairs of sense lines (21A, 21B, 22A, 22B, 23A, 23B, 24A, 24B).

Abstract: Magnetic integrated circuit structures exhibit desirable characteristics for purposes of realizing a magnetic semiconductor memory. In combination with a carrier-deflection-type magnetic field sensor, each of a variety of magnet structures realize a condition in which the magnetic field is substantially orthogonal to the direction of travel of carriers of a sense current, thereby achieving maximum sensitivity. In general, the magnetic structures are highly efficient and achieve a high degree of control of the magnetic field. As a result, a minimum-size device such as a MOS device suffices for purposes of sourcing a magnetizing current. By basing a magnetic memory cell on a single minimum-size MOS device, a small cell may be realized that compares favorably with a conventional DRAM or FLASH memory cell. The greater degree of control over the magnetic field afforded by the magnetic structures enables cross-coupling between cells in a memory array to be minimized.

Abstract: A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction.

Abstract: A semiconductor structure is disclosed in which two regions of semiconductor material positioned adjacent to each other have different electron mobilities. By application of a magnetic field to the device, a Hall voltage is created across the boundary region between the regions of semiconductor material to modify their resistance. By detecting the change in resistance, the device can function as a memory cell, a programmable logic device, a head for hard disk drives, a measurement tool for measuring magnetic fields, or other apparatus.

Abstract: Improved methods for selecting memory cells in magnetic random access memory (MRAM) are provided. Whenever a state in a memory cell is sensed, a MRAM requires to adjust an output of comparator to a zero voltage (auto-zeroing step) before the content of memory cell is detected. This invention sequentially accesses memory cells 29-30 once sense line 25 is selected and auto-zeroed. Accordingly, a higher speed operation is attained because the invention does not require an auto-zeroing step every sensing a memory cell.

Abstract: A modified Hall Effect device can be used as a memory element for the nonvolatile storage of digital information. The novel device includes a ferromagnetic layer that covers a portion of a Hall plate and is electrically isolated from the Hall plate. The ferromagnetic layer on the Hall plate can be changed by an externally applied field, and permits the device to have two stable magnetization states (positive and negative) along an anisotropy axis, which can correspond to two different data values (0 or 1) when the device is used as a memory element. In another embodiment of the invention, the Hall plate is integrated with a conduction channel of a FET, and the ferromagnetic layer is incorporated in proximity to, or as part of the gate over the conducting channel. This device can be described as a "ferromagnetic gated FET.

Abstract: A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction.

Abstract: An electronic transducer array and transfer device and method which provides for activation of selected transducers at selected times. In one application, the device performs data transfer by a combination of suitably interconnected submillimeter transducers (4) capable of sensing and/or actuating microscopic data-storage cells, and electronic switching (402, 602, 702) to activate selected individual transducers. One embodiment of the invention provides for magnetic transducers for reading (304) and writing (302) on a magnetic medium (8). Another embodiment of the invention provides tunneling electron transducers (10) arranged in an array.

Abstract: A semiconductor structure is disclosed in which two regions of semiconductor material positioned adjacent to each other have different electron mobilities. By application of a magnetic field to the device, a Hall voltage is created across the boundary region between the regions of semiconductor material to modify their resistance. By detecting the change in resistance, the device can function as a memory cell, a programmable logic device, a head for hard disk drives, a measurement tool for measuring magnetic fields, or other apparatus.

Abstract: A non-volatile random access memory is described incorporating a plurality of memory cells, each memory cell having a Hall effect device including amorphous magnetic material and a switch for directing current through the flail effect device. An array of memory cells are interconnected by word lines, current lines, and bit lines. The invention overcomes the problem of a rugged non-volatile random access memory with long term reliability.

Abstract: A magnetic thin film memory device having information recorded in a magnetic thin film thereof by the direction of magnetization, and adapted to reproduce the recorded information on the basis of the voltage generated as a result of the change of the magnetization direction due to the extraordinary Hall effect, magnetoresistance effect or the like.A magnetic thin film memory device in which a magnetic thin film is formed of ferrimagnetic substance having perpendicular magnetic anisotropy, and producing extraordinary Hall effect in the composition of RE rich and having the minimum saturation field which enables recording in a small magnetic field and is hard to be influenced by temperatures.

Abstract: An apparatus and method for imaging the magnetic structure and the magnetic domains of a sample is described incorporating a scanning tunneling microscope (STM), a voltage generator for varying the voltage on the tip, an ammeter for measuring the current through the tip, circuitry to determine the tip voltage at zero current and a current source for passing current longitudinally through the sample. The invention may further include an applied magnetic field in the plane of the sample and orthogonal to current passing through the sample. A high density non-volatile memory is described incorporating the above apparatus except for the applied magnetic field and further incorporating a layer of ferromagnetic material having magnetic domains therein indicative of information.

Abstract: A nonvolatile magnetic random access memory can be achieved by an array of magnet-Hall effect (M-H) elements. The storage function is realized with a rectangular thin-film ferromagnetic material having an in-plane, uniaxial anisotropy and inplane bipolar remanent magnetization states. The thin-film magnetic element is magnetized by a local applied field, whose direction is used to form either a "0" or "1" state. The element remains in the "0" or "1" state until a switching field is applied to change its state. The stored information is detcted by a Hall-effect sensor which senses the fringing field from the magnetic storage element. The circuit design for addressing each cell includes transistor switches for providing a current of selected polarity to store a binary digit through a separate conductor overlying the magnetic element of the cell.

Abstract: A nonvolatile random access memory is disclosed having a substrate (50) carrying separate magnetically polarizable domains (19) each surrounded by a full write loop member (18) and arranged to penetrate the Hall channel (36) of a dual drain FET (16) with its residual magnetic field. The domains are organized in word rows and bit columns, are each written to by a single full write current through the surrounding loop member and each read by a comparator connected to the FET drains (42, 42'). The memory can be fabricated in a variety of forms (e.g. a planar card).

Abstract: Improvements are made in a non-volatile magnetic random access memory. Such a memory is comprised of an array of unit cells, each having a Hall-effect sensor and a thin-film magnetic element made of material having an in-plane, uniaxial anisotropy and in-plane, bipolar remanent magnetization states. The Hall-effect sensor is made more sensitive by using a 1 m thick molecular beam epitaxy grown InAs layer on a silicon substrate by employing a GaAs/AlGaAs/InAlAs superlattice buffering layer. One improvement avoids current shunting problems of matrix architecture. Another improvement reduces the required magnetizing current for the micromagnets. Another improvement relates to the use of GaAs technology wherein high electron-mobility GaAs MESFETs provide faster switching times. Still another improvement relates to a method for configuring the invention as a three-dimensional random access memory.

Abstract: An electronic transducer array and transfer device and method which provides for activation of selected transducers at selected times In one application, the device performs data transfer by a combination of suitably interconnected submillimeter transducers (4) capable of sensing and/or actuating microscopic data-storage cells, and electronic switching (402, 602, 702) to activate selected individual transducers. One embodiment of the invention provides for magnetic transducers for reading (304) and writing (302) on a magnetic medium (8). Another embodiment of the invention provides tunneling electron transducers (10) arranged in an array.

Abstract: An optical modulator utilizing a magnetic semiconductor device, whose operation is based on the Hall effect, includes a magnetic material formed on a semiconductor substrate. When an incoming beam of light having a dominant polarization direction is directed onto the magnetic material it becomes modulated. The result is an outgoing beam of light which has a rotated plane of polarization when compared to the dominant polarization direction. The direction of the rotated plane of polarization is indicative of the information stored in the magnetic material. The modulator of the present invention further includes a means for writing the information to the magnetic material and a semiconductor sensor means for electrically verifying the contents of the magnetic material.

Abstract: A non-volatile, static magnetic memory device, whose operation is based on the Hall effect, is disclosed. The device includes a magnetic patch which stores data in the form of a magnetic field, a semiconductor Hall bar and a pair of integrally-formed bipolar transistors used for amplifying and buffering the Hall voltage produced along the Hall bar. Current is forced to flow down the length of the Hall bar causing a Hall voltage to be developed in a direction transverse to the direction of both the magnetic field and the current. The bases of the bipolar transistors are ohmically coupled to the Hall bar to sense the Hall voltage--the polarity of which is representative of the stored information. A system of current carrying conductors is employed for writing data to individual magnetic patches.

Abstract: A non-volatile, static magnetic memory device, whose operation is based on the Hall effect, is disclosed. The device includes a magnetic patch which stores data in the form of a magnetic field, a semiconductor Hall bar and a pair of integrally-formed bipolar transistors used for amplifying and buffering the Hall voltage produced along the Hall bar. Current is forced to flow down the length of the Hall bar causing a Hall voltage to be developed in a direction transverse to the direction of both the magnetic field and the current. The bases of the bipolar transistors are ohmically coupled to the Hall bar to sense the Hall voltage--the polarity of which is representative of the stored information. A system of current carrying conductors is employed for writing data to individual magnetic patches.

Abstract: A non-volatile, static magnetic memory device, whose operation is based on the Hall effect, is disclosed. The device includes a magnetic patch which stores data in the form of a magnetic field, a semiconductor Hall bar and a pair of integrally-formed bipolar transistors used for amplifying and buffering the Hall voltage produced along the Hall bar. Current is forced to flow down the length of the Hall bar causing a Hall voltage to be developed in a direction transverse to the direction of both the magnetic field and the current. The bases of the bipolar transistors are ohmically coupled to the Hall bar to sense the Hall voltage--the polarity of which is representative of the stored information. A system of current carrying conductors is employed for writing data to individual magnetic patches.

Abstract: A magnetic memory element is fabricated from a thin magnetic film wherein the magnetic film is grown on a lattice-matched substrate and subsequently patterned to form a closure domain. The closure domain is comprised of a plurality of legs which are joined at domain walls. The individual legs are patterned in the thin magnetic film to lie parallel to an easy axis of the thin film crystal structure being used. Thus, each closure domain represents a magnetic memory element. Fringing fields about the memory elements are eliminated due to the closure domain design. An array of such closure domains can be grown on a substrate and can be packed to high densities up to the limits of current lithographic technology. Such thin film magnetic memory arrays are non-volatile and are compatible with existing RAMs.

Abstract: A memory is built in a tool holder to which a working tool such as drill or the like is attached. Various tool information such as kind of tool, dimensions of tool, tool use time, and the like is written into the memory. The tool holder having the memory therein is coupled with an external unit by contactless coupling means which doesn't need any electrical coupling, thereby allowing the tool information to be written into or read out of the memory. The information is transmitted between the memory in the tool holder and the external unit by way of the optical or magnetical coupling. The memory built in the tool holder consists of a non-volatile memory such that the memory content is not erased even if the power supply is shut off.

Abstract: A cross tie random access memory has spaced binary memory elements of thin film magneto-resistive material. A source, drain, and channel under each memory element forms a transistor with the thin film memory element which acts as the gate of the transistor. Circuitry is provided to write in and read out a data bit in the addressed binary memory element by providing current under only the memory element being addressed.

Abstract: A sheet random access memory (SHRAM) is a truly random access, nonvolatile and transportable memory characterized by the cell density, size and power requirements of smaller dynamic memories but having the nonvolatile character of core memories or magnetic disks and tape and the rugged transportability of magnetic disk and tape. The SHRAM is characterized by a memory media comprising a two dimensional magnetic substrate and a fixed driving device for writing and reading into the substrate and a fixed sensing device for sensing the information at each cell location. In one embodiment the fixed sensing device is a sensing line in close proximity to a cell location. In a second embodiment, a fixed sensing device includes a Hall effect device which senses the magnetic configuration of the cell. In a third embodiment, the fixed sensing device includes an SCS thyristor in which the cathode gate is coupled to the magnetic configuration of the cell.

Abstract: A third conductor is added to a pair of first and second parallel conductors transmitting signals, a part of which conductors are located in an alternating magnetic field. The three conductors are so arranged that the first and third conductors are symmetrical with respect to the center line of the second conductor, and the first and third conductors are interconnected at both extremities thereof.

Abstract: A drive circuit includes drive input and output terminals, a supply terminal, a drive transistor, and a drive-control circuit. The drive transistor includes a control terminal, a first transistor terminal coupled to the drive output terminal, and a second transistor terminal coupled to the supply terminal. The drive-control circuit has an input terminal coupled to the drive input terminal and has an output terminal coupled to the control terminal of the drive transistor. The drive-control circuit generates on the control terminal of the drive transistor a signal level that changes at a first rate during a first time period and at a second higher rate during a second time period following the first time period. As a result, when used as a data-output driver, one can adjust the first and second rates and time periods such that the drive circuit meets both the 50-ohm and 50 pf falling-slew-rate ranges specified in the Intel® PC-100 specification.

Abstract: A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction.