Abstract: A processing apparatus includes a bit-cell array including at least one bit-cell line including a plurality of bit-cells electrically connected to each other in series, wherein each of the plurality of bit-cells includes: a first magnetic resistor that is configured to store a first resistance value based on a movement of a location of a magnetic domain-wall; a second magnetic resistor that is configured to store a second resistance value, wherein the second resistance value is equal to or less than the first resistance value; a first switching element configured to switch an electrical signal applied to the first magnetic resistor; and a second switching element configured to switch an electrical signal applied to the second magnetic resistor.

Abstract: The present disclosure relates to a magnon spin valve device, a magnon sensor, a magnon field effect transistor, a magnon tunnel junction and a magnon memory. A magnon spin valve device may comprise a first ferromagnetic insulation layer, a non-magnetic conductive layer disposed on the first ferromagnetic insulation layer, and a second ferromagnetic insulation layer disposed on the non-magnetic conductive layer.

Abstract: A domain wall moving type magnetic recording element includes: a domain wall moving layer in which first layers containing a rare earth metal and second layers containing a transition metal are alternately stacked in a first direction; and a first electrode and a second electrode which face the domain wall moving layer and are arranged to be away from each other. The domain wall moving layer has SOT suppression parts which are positioned in one of interfaces between the first layers and the second layers and contain a non-magnetic metal. The SOT suppression parts are locally distributed at the interface.

Abstract: A layout method includes: forming a layout structure of a memory array having first and second rows, each including a plurality of storage cells, wherein at least one of the storage cells includes a fuse; disposing a word line between the first and second rows; disposing a plurality of control electrodes across the word line for connecting the storage cells of the first row and the storage cells of the second row respectively; disposing a first cut layer on a first control electrode of the control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the control electrodes located on a second side of the word line; wherein the first side of the word line is opposite to the second side of the word line.

Abstract: A semiconductor device includes a substrate, a first magnetic tunnel junction (MTJ) structure, a second MTJ structure, and an interconnection structure. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction, and the interconnection structure includes a first metal interconnection and a second metal interconnection. The second metal interconnection is disposed on and contacts the first metal interconnection.

Abstract: This magnetic recording head includes a main magnetic pole, a write shield, and an element. The element has a first portion, a second portion, and a non-magnetic conductive layer disposed therebetween. The element has a first current path connecting the main magnetic pole and the non-magnetic conductive layer to each other, and a second current path connecting the write shield and the non-magnetic conductive layer to each other.

Abstract: A semiconductor device includes a substrate, a first magnetic tunnel junction (MTJ) structure, a second MTJ structure, and an interconnection structure. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction, and the interconnection structure includes a first metal interconnection and a second metal interconnection. The second metal interconnection is disposed on and contacts the first metal interconnection. A material composition of the second metal interconnection is different from a material composition of the first metal interconnection.

Abstract: A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.

Abstract: This disclosure relates to selectively performing a read with increased accuracy, such as a self-reference read, from a memory. In one aspect, data is read from memory cells, such as magnetoresistive random access memory (MRAM) cells, of a memory array. In response to detecting a condition associated with reading from the memory cells, a self-reference read can be performed from at least one of the memory cells. For instance, the condition can indicate that data read from the memory cells is uncorrectable via decoding of error correction codes (ECC). Selectively performing self-reference reads can reduce power consumption and/or latency associated with reading from the memory compared to always performing self-reference reads.

Abstract: Disclosed herein are related to a memory device including a set of memory cells and a memory controller. In one aspect, each of the set of memory cells includes a select transistor and a storage element connected in series between a corresponding bit line and a corresponding source line. In one aspect, the memory controller is configured to apply a first write voltage to a bit line coupled to a selected memory cell, apply a second write voltage to a word line coupled to a gate electrode of a select transistor of the selected memory cell during a first time period, and apply a third write voltage to a source line coupled to the selected memory cell. The second write voltage may be between the first write voltage and the third write voltage.

Abstract: The present disclosure is drawn to, among other things, a method of managing a magnetoresistive memory (MRAM) device. In some aspects, the method includes receiving a configuration bit from a write mode configuration register. In response to determining the configuration bit is a first value, the MRAM device is operated in a NOR emulation mode. In response to determining the configuration bit is a second value, the MRAM device is operated in a persistent memory mode.

Abstract: A semiconductor device and a method of operating the same are provided. The semiconductor device includes a transistor and a fuse structure electrically connected to the transistor. The fuse structure includes a first fuse element, a second fuse element, and a fuse medium. The second fuse element at least partially overlaps the first fuse element. The fuse medium connects the first fuse element and the second fuse element. The fuse medium includes an electrically conductive material.

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

Abstract: Various means for improvement in signal-to-noise ratio (SNR) for a magnetic field sensor are disclosed for low power and high resolution magnetic sensing. The improvements may be done by reducing parasitic effects, increasing sense element packing density, interleaving a Z-axis layout to reduce a subtractive effect, and optimizing an alignment between a Z-axis sense element and a flux guide, etc.

Abstract: A 1S-1T ferroelectric memory cell is provided that include a transistor and a two-terminal selector device. The transistor exhibits a low conductive state and a high conductive state (channel resistance), depending on drive voltage. The two-terminal selector device exhibits one of an ON-state and an OFF-state depending upon whether the transistor is in its low conductive state or its high conductive state. The transistor may be, for instance, a ferroelectric gate vertical transistor. Modulation of a polarization state of ferroelectric material of the vertical transistor may be utilized to switch the state of the selector device. The memory cell may thus selectively be operated in one of an ON-state and an OFF-state depending upon whether the selector device is in its ON-state or OFF-state.

Abstract: A memory device that includes a first magnetic insulating tunnel barrier reference layer present on a first non-magnetic metal electrode, and a free magnetic metal layer present on the first magnetic insulating tunnel barrier reference layer. A second magnetic insulating tunnel barrier reference layer may be present on the free magnetic metal layer, and a second non-magnetic metal electrode may be present on the second magnetic insulating tunnel barrier. The first and second magnetic insulating tunnel barrier reference layers are arranged so that their magnetizations are aligned to be anti-parallel.

Abstract: A method includes forming a cell layer including first and second cells, each of which is configured to perform a circuit function; forming a first metal layer above the cell layer and including a first conductive feature and a second conductive feature extending along a first direction, in which the first conductive feature extends from the first cell into the second cell, and in which a shortest distance between a center line of the first conductive feature and a center line of the second conductive feature along a second direction is less than a width of the first conductive feature, and the second direction is perpendicular to the first direction; forming a first conductive via interconnecting the cell layer and the conductive feature.

Abstract: The present disclosure includes apparatuses, methods, and systems for charge separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell, and determining a data state of the memory cell based, at least in part, on a comparison of an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.

Abstract: The invention relates to hard magnets that include an intermetallic compound having the general composition XaX?bYcZd where X and X? independently from one another are representative of a 3d transition metal with unpaired electrons; Y is a 4d or 5d transition metal of groups 5, 8, 9, or 10 Z is a main group element of groups 13, 14 or 15; a and d independently from one another represent a number between 0.1 and 2.0; and b and c independently from one another represent a number between 0.0 and 2.0; such that a+b+c+d is between 3.0 and 4.0.

Abstract: A magnetoresistance effect element includes a first ferromagnetic layer, a second ferromagnetic layer, a first non-magnetic layer; and a second non-magnetic layer, wherein, the first ferromagnetic layer and the second ferromagnetic layer are formed so that at least one of them includes a Heusler alloy layer, the first non-magnetic layer is provided between the first ferromagnetic layer and the second ferromagnetic layer, the second non-magnetic layer is in contact with any surface of the Heusler alloy layer and has a discontinuous portion with respect to a lamination surface, and the second non-magnetic layer is made of a material different from that of the first non-magnetic layer and is a (001)-oriented oxide containing Mg.

Abstract: A spin-orbit-torque magnetization rotational element includes: a spin-orbit torque wiring layer which extends in an X direction; and a first ferromagnetic layer which is laminated on the spin-orbit torque wiring layer, wherein the first ferromagnetic layer has shape anisotropy and has a major axis in a Y direction orthogonal to the X direction on a plane in which the spin-orbit torque wiring layer extends, and wherein the easy axis of magnetization of the first ferromagnetic layer is inclined with respect to the X direction and the Y direction orthogonal to the X direction on a plane in which the spin-orbit torque wiring layer extends.

Abstract: A magnetic element is provided. The magnetic element includes a free magnetization layer having a surface area that is approximately 1,600 nm2 or less, the free magnetization layer including a magnetization state that is configured to be changed; an insulation layer coupled to the free magnetization layer, the insulation layer including a non-magnetic material; and a magnetization fixing layer coupled to the insulation layer opposite the free magnetization layer, the magnetization fixing layer including a fixed magnetization so as to be capable of serving as a reference of the free magnetization layer.

Abstract: Aspects of the present disclosure are directed to magnetic tunnel junction (MTJ) structures comprising multiple MTJ bits connected in series. For example, a magnetic tunnel junction (MTJ) stack according to the present disclosure may include at least a first MTJ bit and a second MTJ bit stacked above the first MTJ bit, and a resistance state of the MTJ stack may be read by passing a single read current through both the first MTJ bit and the second MTJ bit.

Abstract: A magnetic storage device includes a magnetoresistive effect element. The magnetoresistive effect element includes a first ferromagnetic layer; a second ferromagnetic layer; a non-magnetic layer between the first ferromagnetic layer and the second ferromagnetic layer; and a first layer provided at a side of the first ferromagnetic layer opposite to a side of the first ferromagnetic layer at which the non-magnetic layer is provided. The first layer includes a rare-earth element and the first layer has a region including boron (B) at a proportion higher than a proportion of boron (B) in the first ferromagnetic layer.

Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a stack including word lines, a bit line penetrating the stack, a global bit line disposed above the stack, global word lines disposed above the stack, a common select line disposed above the stack, a first contact plug coupling the global bit line and the bit line to each other and penetrating the common select line, and second contact plugs coupling the global word lines and the word lines to each other respectively and penetrating the common select line.

Abstract: Embodiments of the present invention disclose an MRAM cell layout for 32 nm, 45 nm, and 65 nm CMOS process technology.

Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, and containing magnesium (Mg) and oxygen (O). The nonmagnetic layer further contains an additive element selected from fluorine (F), sulfur (S), hydrogen (H) and lithium (Li).

Abstract: To provide a control circuit capable of not only suppressing an increase in power consumption with a simple configuration but also preventing erroneous writing and destruction of a memory element. Provided is a control circuit that outputs a signal for discharging charges accumulated in a source line and a bit line according to activation of a word line, and outputs a signal for making the source line and the bit line be in a floating state by a start of writing or reading, with respect to a memory cell including the source line, the bit line, a transistor that is provided between the source line and the bit line, and switches on and off by a potential of the word line, and a memory element connected to the transistor in series.

Abstract: A magnetic memory element having a magnetic free layer and a magnetic reference layer with a non-magnetic barrier layer between the magnetic reference layer and the magnetic free layer. A spin current layer (which may be a precessional spin current layer) is located adjacent to the magnetic free layer and is separated from the magnetic free layer by a non-magnetic coupling layer. A material layer adjacent to and in contact with the spin current layer, has a material composition and thickness that are chosen to provide a desired effective magnetization in the spin current layer. The material layer, which may be a capping layer or a seed layer, can be constructed of a material other than tantalum which may include one or more of Zr, Mo, Ru, Rh, Pd, Hf, W, Ir, Pt and/or alloys and/or nitrides of these elements.

Abstract: A system includes a multiturn counter that can store a magnetic state associated with a number of accumulated turns of a magnetic field. The multiturn counter includes a plurality of magnetoresistive elements electrically coupled in series with each other. A matrix of electrical connections is arranged to connect magnetoresistive elements of the plurality of magnetoresistive elements to other magnetoresistive elements of the plurality of magnetoresistive elements.

Abstract: A magnetic memory device includes a first electrode, a second electrode, and a layer stack located between the first electrode and the second electrode. The layer stack includes a reference layer, a tunnel barrier layer, a free layer, and a magnetoelectric multiferroic layer including at least one crystalline grain. The magnetization of the magnetoelectric multiferroic layer may be axial, canted, or in-plane. For axial or canted magnetization of the magnetoelectric multiferroic layer, a deterministic switching of the free layer may be achieved through coupling with the axial component of magnetization of the magnetoelectric multiferroic layer. Alternatively, the in-plane magnetization of the magnetoelectric multiferroic layer may be employed to induce precession of the magnetization angle of the free layer.

Abstract: A hall bar device for a memory or logic application can include a gate electrode, a boron-doped chromia layer on the gate electrode; and a hall bar structure with four legs on the boron-doped chromia layer. For a memory application, the hall bar device can be written to by applying a pulse voltage across the gate electrode and one leg of the hall bar structure in the absence of an applied magnetic field; and can be read from by measuring a voltage across the one leg of the hall bar structure and its opposite leg.

Abstract: Disclosed is a method for generating, from a first electric current having a first frequency, a plurality of second currents each having a second respective frequency component, the method including the following steps: supplying a frequency distributor including a first set of pillars including a layer made from a first magnetic material and having a resonance frequency; exciting each pillar of the first set with an electromagnetic field having the first frequency, the ratio between twice the resonance frequency of each pillar of the first set and the first frequency being equal, to within ten percent, to a first natural integer; and generating, by each pillar of the first set, a second frequency component in the second respective current.

Abstract: A method is presented for preventing excessive cap dielectric loss in memory areas and logic areas of a device. The method includes forming a first conductive line with top via and a conductive pad over a dielectric layer, wherein the conductive pad includes a microstud, depositing a dielectric cap in direct contact with the first conductive line and the conductive pad, and constructing a top electrode, a magnetic tunnel junction (MTJ) stack, and a bottom electrode in vertical alignment with the microstud of the conductive pad.

Abstract: Magnetic memory devices and methods are provided. In one aspect, a memory device may comprise a control circuitry and at least one array of memory structures. Each memory structure may comprise a metal layer and a first magnetic tunnel junction (MTJ) disposed on the metal layer. The metal layer may include a first region and a second region. Electrical resistivity of at least a first part of the first region is different from electrical resistivity of the second region. The first magnetic tunnel junction (MTJ) may comprise a first free layer adjacent to the metal layer, a first barrier layer adjacent to the first free layer, and a first reference layer adjacent to the first barrier layer. The first free layer is in contact with the first region of the metal layer.

Abstract: A spin torque oscillator includes a first electrode, a second electrode and a device layer stack located between the first electrode and the second electrode. The device layer stack includes a spin polarization layer including a first ferromagnetic material, an assist layer including a third ferromagnetic material, a ferromagnetic oscillation layer including a second ferromagnetic material located between the spin polarization layer and the assist layer, a nonmagnetic spacer layer located between the spin polarization layer and the ferromagnetic oscillation, and a nonmagnetic coupling layer located between the ferromagnetic oscillation layer and the assist layer. The assist layer is antiferromagnetically coupled to the ferromagnetic oscillation layer through the non-magnetic coupling layer, and the assist layer has a magnetization that is coupled to a magnetization of the ferromagnetic oscillation layer.

Abstract: A memory cell array includes a first column of memory cells, a second column of memory cells, a first bit line, a second bit line and a source line. The second column of memory cells is separated from the first column of memory cells in a first direction. The first column of memory cells and the second column of memory cells are arranged in a second direction. The first bit line is coupled to the first column of memory cells, and extends in the second direction. The second bit line is coupled to the second column of memory cells, and extends in the second direction. The source line extends in the second direction, is coupled to the first column of memory cells and the second column of memory cells.

Abstract: Embodiments of a memory, and calibration and operation methods thereof for reading data in memory cells are disclosed. In an example, an apparatus comprises transistors, and a charge sharing circuit coupled to the transistors through gate terminals of the transistors. The charge sharing circuit comprises a programmable electrical source, a first switch coupled to the programmable electrical source, a capacitor coupled to the first switch, and a second switch coupled to the capacitor, the first switch, and the gate terminals of the transistors. The programmable electrical source is configured to provide electrical charges to the capacitor when the first switch is turned on and the second switch is turned off. The capacitor is configured to provide at least a portion of the electrical charges to the gate terminals of the transistors when the first switch is turned off and the second switch is turned on.

Abstract: This invention is about a method to make an MRAM element with small dimension, by making an MTJ as close as possible to the via, ideally aligning the MTJ and the via in a direction perpendicular to the wafer surface, for making the MRAM element dimension as small as possible. The invention provides a process scheme to flatten the interface of bottom electrode during film deposition, which ensures a good deposition of atomically smooth MTJ multilayer as close as possible to an associated via which otherwise might be atomically rough. The flattening scheme is first to deposit a thin amorphous conducting layer in the middle of BE deposition and immediately to bombard the amorphous layer by low energy ions to provide kinetic energy for surface atom diffusion to move from high point to low kinks. With such surface flattening scheme, not only the MRAM element can be made extremely small, but its device performance and magnetic stability can also be greatly improved.

Abstract: An analog Magnetoresistive Random Access Memory (MRAM) cell is provided. The analog MRAM cell includes a magnetic free layer having a first domain having a first magnetization direction, a second domain having a second magnetization direction opposite to the first magnetization direction and a domain wall located between the first domain and the second domain. The analog MRAM cell further includes a magnetically pinned layer. The analog MRAM cell also includes an insulating tunnel barrier between the magnetic free layer and the magnetically pinned layer. The analog MRAM cell additionally includes an electrode located adjacent to the magnetic free layer configured to generate heat by supplying current to decrease a conductance of the magnetic free layer.

Abstract: A metamagnetic tunneling-based spin valve device for multistate magnetic memory comprising an electronic memory logic element with four stable resistance states. A metamagnetic tunneling-based spin valve device for multistate magnetic memory comprising a layer of a metamagnetic material, a layer of a nonmagnetic material on the layer of a metamagnetic material, and a layer of a ferromagnetic material on the layer of a nonmagnetic material. A method of making a metamagnetic tunneling-based spin valve device for multistate magnetic memory.

Abstract: A magnetoresistance effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, and the tunnel barrier layer has a spinel structure represented by a composition formula of AIn2Ox(0<x?4), and an A-site is a non-magnetic divalent cation which is one or more selected from a group consisting of magnesium, zinc and cadmium.

Abstract: A magnetic sensor includes a plurality of magnetic detection elements, and a plurality of magnetic field generators associated with the plurality of magnetic detection elements. Each of the plurality of magnetic field generators includes a first ferromagnetic material section and a first antiferromagnetic material section. The first antiferromagnetic material section is in contact with and exchange-coupled to the first ferromagnetic material section. The first ferromagnetic material section has an overall magnetization. The plurality of magnetic field generators includes first and second magnetic field generators configured so that the overall magnetization of the first ferromagnetic material section of the first magnetic field generator is in a different direction from the overall magnetization of the first ferromagnetic material section of the second magnetic field generator.

Abstract: An apparatus is provided which comprises: a first magnet with perpendicular magnetic anisotropy (PMA); a stack of layers, a portion of which is adjacent to the first magnet, wherein the stack of layers is to provide an inverse Rashba-Bychkov effect; a second magnet with PMA; a magnetoelectric layer adjacent to the second magnet; and a conductor coupled to at least a portion of the stack of layers and the magnetoelectric layer.

Abstract: In high performance computing, the potential compute power in a data center will scale to and beyond a billion-billion calculations per second (“Exascale” computing levels). Limitations caused by hierarchical memory architectures where data is temporarily stored in slower or less available memories will increasingly limit high performance computing systems from approaching their maximum potential processing capabilities. Furthermore, time spent and power consumed copying data into and out of a slower tier memory will increase costs associated with high performance computing at an accelerating rate. New technologies, such as the novel Zero Copy Architecture disclosed herein, where each compute node writes locally for performance, yet can quickly access data globally with low latency will be required. The result is the ability to perform burst buffer operations and in situ analytics, visualization and computational steering without the need for a data copy or movement.

Abstract: According to one embodiment, a magnetic memory device includes a conductive member, a first magnetic layer, a first counter magnetic layer, and a first nonmagnetic layer. The conductive member includes a first portion, a second portion, and a third portion between the first portion and the second portion. The first counter magnetic layer is provided between the third portion and the first magnetic layer in a first direction crossing a second direction. The second direction is from the first portion toward the second portion. The first nonmagnetic layer is provided between the first magnetic layer and the first counter magnetic layer. The third portion includes a first position, and a second position between the first position and the first counter magnetic layer in the first direction. A second concentration of boron at the second position is lower than a first concentration of boron at the first position.

Abstract: A memory device and an operating method of the memory device, the memory device including a memory cell array including a plurality of memory cells respectively arranged at points at which a plurality of word lines and a plurality of bit lines cross; and a control logic circuit configured to precharge a selected word line connected to a selected memory cell and precharge a selected bit line connected to the selected memory cell in a read operation, wherein the control logic circuit is further configured to precharge a first unselected word line among unselected word lines to a second voltage when the selected word line is precharged to a first voltage, a level of the first voltage is lower than a level of a third voltage applied to an unselected bit line when the selected word line is precharged to the first voltage, and a level of the second voltage is higher than the level of the third voltage.

Abstract: The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.

Abstract: A magnetic element includes a first magnetic layer and a first nonmagnetic layer. An angle ?0 between a first direction and the magnetization direction of the first magnetic layer satisfies 0°<?0<90° or 90°<?0<180° in a state in which neither a voltage nor a magnetic field is substantially applied to the first magnetic layer; and the first direction is from the first nonmagnetic layer toward the first magnetic layer. A resistance·area of the first nonmagnetic layer is 10 ??m2 or more.

Abstract: A method for manufacturing an array of magnetic memory elements, wherein first memory element types are formed in a first region and second type of magnetic memory element types are formed in a second region. A shadow-mask is used during deposition to limit the deposition of at least one layer of memory element material to only the second region wherein the second memory element types are to be formed. The method can include depositing full film magnetic memory element layers over an entire substrate and then using the shadow-mask to deposit at least one performance altering material in the second memory element region. Alternatively, a first shadow-mask can be used to deposit a series of first memory element layers in a first region, and a second shadow-mask can be used to deposit a plurality of second memory element layers in a second region.