Abstract: A unique topography of I.sup.2 L bipolar semiconductor elements provides Read-Write Random Access Memory (RAM) with very high packing density, low cost, and good power and speed characteristics and with a very simple metallization pattern.

Abstract: A random access memory element, fed by a constant current source, contains two complementary transistors forming a pnpn or npnp structure, with a lateral transistor and a transverse transistor. The constant current source is connected to an emitter of the lateral transistor, which is at a distance from its collector. This transistor has a second emitter near this collector, this second emitter receiving a control voltage which is able to trigger the assembly.

Abstract: The bit lines of a word organized memory array are precharged to a potential which is substantially equal to the flip points (i.e. the point at which the cell changes state) of the memory cells of the array prior to each read and each write operation. This ensures the non-disturbance of the unselected memory cells of the array, provides greater design freedom of the memory array components, and enables the memory array to operate faster and more reliably.

Abstract: There is described a logic element employing fixed threshold and variable threshold transistors electrically connected together in a unique manner to form a latch. The latch can be made to retain data by keeping certain internal nodes at a high or low voltage level. As such it acts as an ordinary semiconductor memory latch, whose data can be changed by externally overriding the internal voltage levels of the latch cell. The novel results of the cell described are achieved by replacing one or several of the transistors in the latch by specially constructed transistors, whose threshold voltage can be raised or lowered upon application of a relatively high voltage pulse between their gate and substrate. By application of such a high voltage pulse, the data stored in the latch can be translated into controlled threshold shifts of the variable threshold transistors, which uniquely represent the initial latch state.

Abstract: A complementary metal-ferroelectric-semiconductor transistor structure (MFST) in which an n-channel MFST is electrically coupled to a p-channel MFST in complementary fashion with the source of the n-channel MFST connected to the drain of the p-channel MFST and the drain of the n-channel MFST connected to the source of the p-channel MFST. The memory element is controlled in response to a polarizing voltage, and erasing voltage, a reference signal, and input signals such that the input signals are compared with respect to the reference signal. A matrix of memory elements arranged in rows and columns is also described with each of the memory elements comprised of a complementary MFST structure.

Abstract: This relates to an integrated injection logic (I.sup.2 L) bi-polar memory cell employing both vertical and lateral injectors. The two embodiments disclosed have been optimized with respect to layout in a word-organized array such that coupling between surface regions and coupling to read/write-write/read lines can be manufactured during a single metallization step. To this end, the substrate forms the common injector of the vertical pnp transistors.

Abstract: An integrated semiconductor memory device of the static type uses a memory cell circuit having an MOS transistor of the conventional type as the access transistor, along with a resistance element buried under field oxide and an inverted field-effect transistor formed by a polycrystalline layer over a gate region. The MOS transistor connects a storage node to the access line, and the inverted field-effect transistor connects the storage node to reference potential. The storage node is connected to a second node through the resistance element, and a resistor connects the second node to a voltage supply; the magnitude of the resistance element varies according to the voltage on the storage node. The impedance of the inverted field-effect is determined by the voltage on the second node which is a moat region forming the gate.

Abstract: A random access memory using complementary field effect transistors, comprising an array of a plurality of storing locations, address signal lines for addressing said plurality of storing locations, a data signal line commonly coupled to said plurality of storing locations for inputting/outputting a data signal, each said location comprising a flip-flop including first and second inverters cross connected to each other and each implemented by complementary field effect transistors, field effect switching transistors connected in series with said first inverter and to be non-conductive in a write operation mode, a transmission gate connected between the input/output node of said flip-flop and said data signal line to be operable as a function of the signal in said address signal line, said transmission gate comprising two complementary field effect switching transistors connected in parallel with each other, each individually responsive to the complementary states of the address signal in said address signal l

Abstract: Transistor memory cells which may be operated in both the erasable "read only" and the "random access" modes. Each cell includes a plurality of MOS transistors interconnected to permit random access storage and at least two MNOS transistors. The latter may be set, one to one threshold level and the other to a second threshold level to represent read only storage of a logic 1, and the threshold levels may be reversed to represent read only storage of a logic 0. The MOS transistors may be randomly accessed both for read and write independently of what the MNOS transistors are storing.

Abstract: A high density, static, virtually nonvolatile, Random Access Memory (RAM) cell is disclosed in which variable threshold n-channel depletion mode Metal-Nitride-Oxide-Semiconductor (MNOS) transistors are the load devices for a pair of active, n-channel, enhancement mode, Insulated Gate Field Effect Transistors (IGFETs) in a flip-flop circuit. N-channel enhancement mode access transistors also IGFETs connect the cell to the bit line and the bit line. Information is written in, and read, in volatile form conventionally. A +25 volt, 10 msec pulse applied to the gates of the depletion mode MNOS load devices transfers the data from the volatile mode to the nonvolatile mode.

Abstract: A new integrated circuit in which bias currents are supplied by means of a current injector, a multi-layer structure in which current is supplied, by means of injection and collection of charge carriers via rectifying junctions, to zones to be biased of circuit elements of the circuit, preferably in the form of charge carriers which are collected by the zones to be biased themselves from one of the layers of the current injector. By means of said current injector circuit arrangements can be realized without load resistors being necessary, while the wiring pattern may be very simple and the packing density of the circuit elements may be very high. In addition a simple method of manufacturing with comparatively few operations can in many cases be used in particular upon application of transistors having a structure which is inverted relative to the conventional structure.