Abstract: An apparatus comprising non-volatile memory is configured to access a selected unit of encoded SLC data in the non-volatile memory during a first programming phase of a process of folding data stored at a single bit per memory cell to data stored at multiple bits per memory cell. The apparatus recovers the selected unit of SLC data based on redundancy data formed from units of SLC data that data include the selected unit of SLC data. The apparatus saves the recovered selected unit of SLC data to memory. The apparatus uses the saved recovered unit of SLC data during a second programming phase of folding the data stored at a single bit per memory cell to the data stored at multiple bits per memory cell, thereby saving considerable time in not having to again recover the SLC data using the redundancy data.

Abstract: A semiconductor memory system and an operating method thereof include a controller configured to perform macro management; and a memory device including Nand pages, counters, a self-management component, and devoted memories, wherein the memory device is coupled and controlled by the controller, the Nand pages contains data corresponding to commands received from the controller, the counters are configured to track operation information corresponding to the Nand pages in accordance with the commands, the devoted memories are configured to record recovery information, and the self-management component configured to perform micro management in accordance at least in part with the operation information or the recovery information.

Abstract: Provided herein may be a semiconductor memory device including a memory cell, a read and write circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The read and write circuit includes a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines, respectively. The current sensing circuit is coupled to the read and write circuit through a plurality of sensing lines. The control logic is configured to control operations of the current sensing circuit and the read and write circuit. At least two page buffers among the plurality of page buffers are coupled to one of the plurality of sensing lines. The control logic controls the read and write circuit to simultaneously perform a current sensing operation for the at least two page buffers.

Abstract: A semiconductor memory device may include: a memory cell array including a plurality of memory cells; a peripheral circuit for performing a program operation on the memory cell array; and a control logic for controlling the peripheral circuit to perform the program operation on the memory cell array. The control logic may control the peripheral circuit to perform a program operation on memory cells included in a selected physical page among the plurality memory cells, in response to a program command, and control the peripheral circuit to perform an additional program operation on at least one memory cell among the memory cells included in the selected physical page, based on whether the program operation has passed.

Abstract: A memory device and an operating method for controlling a non-volatile memory are provided. The non-volatile memory includes segments. Each of the segments includes memory cells. The operating method includes the following steps. A programming operation is performed multiple times on the memory cells in sequence according to increment commands, a segment order, and a memory cell order. When receiving a read command, a read operation is performed multiple times on the memory cells according to the segment order and the memory cell order until a last programmed memory cell is learned. According to an address of the last programmed memory cell, a replay-protected monotonic count value associated with a number of the increment commands is calculated.

Abstract: An electronic memory array includes a plurality of memory domains, a current controller, and a selector device. Each memory domain includes a plurality of bit cells. The current controller includes a current controller output electrically connectable to said plurality of memory domains and is configured to control a bit cell current. The selector device is electrically connected to the current controller and the plurality of memory domains. The selector device is configured to selectively electrically connect the current controller output to only a select one of said memory domains, such that the current controller controls only the bit cell current of the bit cells of the select memory domain.

Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.

Abstract: An apparatus is described. The apparatus includes a storage device controller having logic circuitry to apply a program voltage verification process for a first threshold level to a group of non volatile memory cells and correlate first program voltages for the group of non volatile memory cells determined from the process to a second threshold level to determine second program voltages for the second threshold level for the group of non volatile memory cells. The second threshold level is higher than the first threshold level.

Abstract: A memory device includes a first cell above a substrate, a first line connected to the first cell, a second cell above the first cell connected with the first cell, a second line connected to the second cell, a third cell above the second cell connected with the second cell, a third line connected to the third cell, a fourth cell above the third cell connected with the third cell, a fourth line connected to the fourth cell, and a driver applying voltages to the lines when data is written to a cell in a write operation. To write data to the second cell, the driver applies a write voltage to the second line, applies a first voltage lower than the write voltage to the first line, and applies a second voltage higher than the first voltage and lower than the write voltage to the third and fourth lines.

Abstract: A memory system includes a nonvolatile memory device and a controller configured to control the nonvolatile memory device. The nonvolatile memory device includes a first data storage region in which a memory cell stores one-bit data in a first mode and a second data storage region in which a memory cell stores two-bit or more data in a second mode. The controller controls the nonvolatile memory device to perform a read operation on the first data storage region and the second data storage region in the second mode. The controller decodes first data read from the first data storage region, and decodes second data read from the second data storage region. The controller controls the nonvolatile memory device to perform the read operation on the first data storage region in the second mode.

Abstract: A memory device includes a memory cell array, a read operator, a shift level determiner, and a read operation controller. The read operator applies a read voltage to a selected word line coupled to selected memory cells and reads the selected memory cells in response to an evaluation signal. The shift level determiner calculates a shift value indicating a difference between a number of memory cells read as on-cells and a reference number, and determines a shift level of a threshold voltage distribution for the selected memory cells. The soft read table storage stores soft read set parameters. The read operation controller determines a plurality of soft read voltages based on the shift level and the soft read set parameters and controls the read operator in response to the evaluation signal.

Abstract: An apparatus can have an array of memory cells and a controller coupled to the array. The controller can be configured to read a group sentinel cells of the array and without reading a number of other groups of cells of the array to determine that data stored in the number of other groups of cells lacks integrity based on a determination that data stored in the group of sentinel cells lacks integrity.

Abstract: A non-volatile memory device determines the bit-line location of a memory cell selected for memory operation relative to a nearest source line, generates a modified bit-line bias voltage based on the bit-line location and applies the modified bit-line bias voltage to the selected memory cell. In some embodiments, the memory cell is selected to be programmed. In this manner, the non-volatile memory device compensates for source line resistance at the memory cells.

Abstract: An operating method of memory system may include: reading target data stored in a target memory page, using a plurality of read voltages, respectively; sequentially storing read data corresponding to the target data in a plurality of latches including a first latch and a second latch, respectively; performing a first error correction code (ECC) decoding operation on first read data stored in the first latch; and performing a second ECC decoding operation on second read data stored in the second latch, when the first ECC decoding operation fails.

Abstract: A BER corresponding to a group of memory cells programmed via a programing signal having one or more program step characteristics is determined. The determined BER and a target BER is compared. In response to the determined BER being different than the target BER, one or more program step characteristics are adjusted to adjust the determined BER to the target BER.

Abstract: An apparatus and method of skip coding user data is provided. According to skip coding, for each cell in which an upper page is 0, data is stored in a half page. For each portion of data in which the upper page is 1, data is not stored in the half page. Thus, cells of a NAND memory may each store 3.5 bits, in one of twelve available states.

Abstract: A memory system includes a controller suitable for providing first data, a cache program command corresponding to the first data, second data, and a normal program command corresponding to the second data; and a memory device suitable for programming the first data to a target die according to the cache program command, setting the target die to a normal state after the program operation for the first data is completed, and programming the second data to the target die according to the normal program command.

Abstract: A semiconductor storage device includes first, second, and third transistors, first, second, and third bit lines connected to the first, second, and third transistors, a word line connected to the first, second, and third transistors, and a control circuit configured to perform a program operation for writing data to the second and third transistors, including raising a first voltage applied to the first bit line at a first timing, raising a second voltage applied to the word line at a second timing, raising a third voltage applied to the second bit line at a third timing, raising a fourth voltage applied to the third bit line at a fourth timing, and lowering the first voltage at a fifth timing. The first voltage is raised to a first predetermined voltage, and each of the third and fourth voltages is raised to a second predetermined voltage smaller than the first predetermined voltage.

Abstract: Techniques are described for reprogramming memory cells to tighten threshold voltage distributions and improve data retention. In one aspect, the memory cells of a word line WLn are reprogrammed after programming of memory cells of an adjacent, later-programmed word line WLn+1. The reprogramming can be limited to lower state memory cells of WLn which are adjacent to lower state memory cells of WL+1. A program pulse magnitude used in the reprogramming can be tailored to the data states of the WLn memory cell and the adjacent, WLn+1 memory cell. In some cases, the program pulse magnitudes can be grouped to reduce the implementation complexity and time. The reprogramming can occur after an initial program operation has completed, during an idle time of a control circuit.

Abstract: A method of performing a programming operation to a three dimensional (3D) NAND memory device is disclosed. The method makes residual electrons trapped in storage regions of middle dummy memory cells of an unselected string of the 3D NAND memory device to be removed during the pre-charging phase, so as to reduce program disturb to an selected string which neighbors the unselected string.

Abstract: A memory system includes a semiconductor storage device including a memory cell array including a plurality of groups of memory cells, and a control circuit configured to perform, upon receipt of a write command, a write operation on one of the groups of memory cells, and a memory controller is configured to, when transmitting the write command to perform the write operation on the one of the groups of memory cells, determine a first write voltage value for the write operation based on a total number of write operations or erase operations that have been performed on the one of the groups of memory cells, and transmit the write command to the semiconductor storage device together with the determined first write voltage value.

Abstract: Disclosed herein is a memory controller controlling data transfer between a host system and a flash memory. The memory controller is configured to operate on one of a plurality of operation states including first and second operation states. In the first operation state, a first memory area included in the flash memory is used in a first storage mode that stores information of less than n bits in one cell, and a second memory area included in the flash memory is used in a second storage mode that stores information of n bits or more in one cell. In the second operation state, the first memory area is used in the second storage mode, and the second memory area is used in the first storage mode.

Abstract: Devices and techniques are disclosed herein to address high latency associated with large-scale un-map or trim commands associated with flash memory. In an example, a method can include receiving a trim command for a partition of a storage system, identifying a record of a partition table of the storage system corresponding to the partition, updating a partition count of the record with a count value of a partition counter of the storage system, and incrementing the partition counter.

Abstract: A computer-implemented method, according to one approach, is for calibrating read voltages for a block of memory. The computer-implemented method includes: determining a current operating state of a block which includes more than one word-line therein, and where more than one read voltage is associated with each of the word-lines. Moreover, for each of the word-lines in the block: one of the read voltages associated with the given word-line is selected as a reference read voltage, and an absolute shift value is calculated for the reference read voltage. A relative shift value is determined for each of the remaining read voltages associated with the given word-line, where the relative shift values are determined with respect to the reference read voltage. Furthermore, each of the read voltages associated with the given word-line are adjusted using the absolute shift value and each of the respective relative shift values.

Abstract: Techniques for accessing multi-level cell (MLC) crosspoint memory cells are described. In one example, a circuit includes a crosspoint memory cell that can be in one of multiple resistive states (e.g., four or more resistive states). In one example, to perform a read, circuitry coupled with the memory cell applies one or more sub-reads at different read voltages. For example, the circuitry applies a first read voltage and detects if the memory cell thresholds in response to the first read voltage. If the memory cell thresholded in response to the first read voltage, the state of the memory cell can be determined without further reads. If the memory cell did not threshold in response to the first read voltage, a second read voltage with a greater magnitude is applied across the memory cell. If the memory cell thresholded in response to the second read voltage, the state of the memory cell can be determined without further reads.

Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.

Abstract: A power switch circuit comprises a first level shifter configured to turn on a first switching element configured to receive a supply voltage from an external voltage supply pad in response to a program operation of a one-time programmable (OTP) memory cell array, a second level shifter configured to turn on a second switching element and provide the supply voltage to the OTP memory cell array in response to the program operation, a third level shifter configured to turn on a third switching element and provide an internally generated power voltage to the OTP memory cell array in response to a read operation of the OTP memory cell array, and an Electro-Static Discharge (ESD) protection circuit configured to turn off the first switching element in response to a flow of ESD voltage from the voltage supply pad.

Abstract: A memory system comprising a plurality of memory cells each including a storage element having a first terminal and a control terminal. The method for operating the memory system includes applying a first program voltage to control terminals of storage elements and applying a basic reference voltage to first terminals of the storage elements during a first program operation, performing a group verification by comparing threshold voltages of the storage elements with a middle voltage, performing a first program test to check if the threshold voltages of the storage elements are greater than a first programming threshold voltage, and performing a second program operation according to a result of the group verification and a result of the first program test. The middle voltage is smaller than the first programming threshold voltage.

Abstract: A memory device includes a plurality of memory cells arranged in N rows, N being a positive integer. A method includes programming a first row of the N rows; after programming the first row, programming a (2m+1)th row, m being an integer between 1 and N/2?1; and immediately after programming the (2m+1)th row, programming a (2m)th row; and after programming an (N?2)th row, programming an Nth row. Even rows closer to the first row are programmed before even rows farther away from the first row.

Abstract: A processing device in a memory system receives a memory command indicating a read window size and a first read voltage and identifies a read window for a first data block of the memory component having the read window size and centered at the first read voltage. The processing device determines whether a number of bit flips for the first data block within the read window exceeds an error threshold and, in response to the number of bit flips exceeding the error threshold, refreshes data stored on the first data block of the memory component.

Abstract: A memory management method and a storage controller are provided. The method includes performing a decoding operation to a first data stored in a first word line among multiple word lines of a rewritable non-volatile memory module to determine whether the decoding operation is successful or failed, and obtain a first error value of the first word line; when the decoding operation is determined as successful, determining whether to mark the first word line as a bad word line according to the first error value and a first threshold; and when the decoding operation is determined as failed, obtaining a second error value of a second word line adjacent to the first word line, and determining whether to mark both of the first and second word lines as the bad word line according to the first error value, the second error value, and a first threshold.

Abstract: A methodology and structure for accounting for fabrication difference in memory holes is described. Increasing the distance of the memory holes from the sources of etchant or other fabrication material results in different characteristics of the memory from the outer memory holes to the inner memory holes. These difference can be accounted for by grouping the memory holes and altering the parameters of the program or verify operations based on the groupings. The bitline voltage for the inner grouping can be less than the bitline voltage for the outer groupings. The sense timing can be greater for the outer groupings relative to the inner groupings. This can result in voltage threshold for the inner groupings and outer groupings overlying each other to improve memory performance.

Abstract: A memory control method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first physical unit of a rewritable non-volatile memory module; decoding the first data by a decoding circuit; updating reliability information according to the decoded first data; reading second data from a second physical unit of the rewritable non-volatile memory module; and decoding the second data by the decoding circuit according to the updated reliability information.

Abstract: An apparatus includes a pair of memory cells configured to represent data using joint data states where one of the joint data states comprises an error-prone joint data state. The apparatus further includes an encoder configured to convert user data into joint data states according to a dual-cell gray-code encoding scheme in which the error-prone joint data state does not encode user data.

Abstract: A computer-implemented method, the method comprising: in an initial setup of weights for a floating gate including rows, columns, and a separate input line: comparing a current weight to a desired weight; performing a feedback to the input line to set a voltage to change the floating gate field effect transistor (FET) threshold voltage (VT) and the current weight; and checking that the current weight is within a predetermined tolerance of the desired weight; and performing a stochastic pulse update on the floating gate based on the checking.

Abstract: Read operations are performed in a memory device which efficiently provide baseline read data and recovery read data. In one aspect, on-die circuitry, which is on a die with an array of memory cells, obtains recovery read data before it is requested or needed by an off-die controller. In another aspect, data from multiple reads is obtained and made available in a set of output latches for retrieval by the off-die controller. Read data relative to multiple read thresholds is obtained and transferred from latches associated with the sense circuits to the set of output latches. The read data relative to multiple read thresholds can be stored and held concurrently in the set of output latches for retrieval by the off-die controller.

Abstract: Numerous embodiments of programming systems and methods for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.

Abstract: A storage device includes a nonvolatile memory including a plurality of nonvolatile memory cells, a write buffer memory storing first data and second data received from a host, and a storage controller storing the first data and the second data that are stored in the write buffer memory into the nonvolatile memory. The storage controller performs a first program operation and a second program operation on a plurality of first memory cells connected to a first word line group to store the first data, and performs a first program operation and a second program operation on a plurality of second memory cells connected to a second word line group to store the second data. While the storage controller performs the first program operation on the plurality of second memory cells, the first data is written in the write buffer memory.

Abstract: A program method of a nonvolatile memory device including a plurality of memory cells, each storing at least two bits of data, includes performing a first program operation based on a plurality of program voltages having a first pulse width to program first page data into selected memory cells connected to a selected word line among the plurality of memory cells; and performing a second program operation based on a plurality of program voltages having a second pulse width different from the first pulse width to program second page data into the selected memory cells in which the first page data is programmed.

Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.

Abstract: Numerous embodiments are disclosed for an analog neuromorphic memory system for use in a deep learning neural network. In one embodiment, the analog neuromorphic memory system comprises a plurality of vector-by-matrix multiplication systems, each vector-by-matrix multiplication system comprising an array of memory cells, a low voltage row decoder, a high voltage row decoder, and a low voltage column decoder; a plurality of output blocks, each output block providing an output in response to at least one of the plurality of vector-by-matrix multiplication systems; and a shared verify block configured to concurrently perform a verify operation after a program operation on two or more of the plurality of vector-by-matrix systems.

Abstract: Methods of operating an electronic system include allocating a group of memory cells of a plurality of groups of memory cells having a particular rank of a plurality of ranks for storing data of a particular data level of a plurality of data levels, determining a need for an additional group of memory cells for storing data of the particular data level, moving or discarding data from a different group of memory cells storing data of a different data level of the plurality of data levels in response to determining the need for the additional group of memory cells for storing data of the particular data level, and allocating the different group of memory cells for storing data of the particular data level.

Abstract: In a method of programming in a nonvolatile memory device, channels of a plurality of cell strings are precharged through ground selection transistors by a precharge voltage of a source line. A turn-on voltage is applied to a selected ground selection transistor of a selected cell string among the plurality of cell strings, during a verification read period of an N-th program loop. The turn-on voltage applied to the selected ground selection transistor is maintained to precharge the channels for an (N+1)-th program loop, without recovery after the verification read period of the N-th program loop is finished. Power consumption is reduced and an operation speed is increased by maintaining the turn-on voltage of the selected ground selection line to precharge the channels of the cell strings without recovery after the verification read operation is finished.

Abstract: A processing device determines that read level thresholds between first programming distributions of a second programming pass associated the memory component are calibrated. The processing device changes one or more of the read level thresholds between the first programming distributions. The processing device adjusts one or more read level threshold between second programming distributions of a first programming pass based on the change to the one or more read level thresholds between the first programming distributions.

Abstract: A method of performing a programming operation to a three dimensional (3D) NAND memory device is disclosed. The method makes residual electrons trapped in storage regions of middle dummy memory cells of the unselected string of the 3D NAND memory device to be removed during the pre-charging phase, so as to reduce program disturb to the selected string which neighbors the unselected string.

Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.

Abstract: A semiconductor memory includes memory cells, a word line and bit lines of the memory cells, sense amplifiers connected to the bit lines, respectively, and a controller. Each sense amplifier includes first, second, and third transistors. The third transistor has one end connected to each of the first and second transistors, and the other end connected to a corresponding bit line. During a read operation, at a first time of a first period during which the controller applies a first read voltage to the word line, the controller applies a first voltage higher than ground voltage to the first transistor, and a second voltage to the second transistor. Also, at the first time, a first sense amplifier applies a voltage to a first bit line through its first and third transistors, and a second sense amplifier applies a voltage to a second bit line through tis second and third transistors.

Abstract: A memory system includes a plurality of first memory chips connected to a first bus, a plurality of second memory chips connected to a second bus, and a controller that is connected to the first and second buses and configured to execute a write operation by performing processes that include selecting one of the plurality of first memory chips based on first information including data reading speed information and/or data writing speed information for the plurality of first memory chips, and selecting one of the plurality of second memory chips based on second information including data reading speed information and/or data writing speed information for the plurality of second memory chips.

Abstract: A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.