Abstract: A vertical gain memory cell including an n-channel metal-oxide semiconductor field-effect transistor (MOSFET) and p-channel junction field-effect transistor (JFET) transistors formed in a vertical pillar of semiconductor material is provided. The body portion of the p-channel transistor is coupled to a second source/drain region of the MOSFET which serves as the gate for the JFET. The second source/drain region of the MOSFET is additionally coupled to a charge storage node. Together the second source/drain region and charge storage node provide a bias to the body of the JFET that varies as a function of the data stored by the memory cell. A non destructive read operation is achieved. The stored charge is sensed indirectly in that the stored charge modulates the conductivity of the JFET so that the JFET has a first turn-on threshold for a stored logic “1” condition and a second turn-on threshold for a stored logic “0” condition.

Abstract: Present invention describes an efficient implementation of differential sensing in single ended DRAM arrays. According to one embodiment of the present invention, a respective local sense amplifier compares the accessed memory cell data with a dummy cell data in the opposite or adjacent block of the accessed block that is connected to a respective local bit line in the opposite block, amplifies the result of the comparison and puts the data on a global bit line. In one embodiment, the invention is process and temperature invariant using reference method and means for canceling cross coupling between read lines and write lines.

Abstract: A semiconductor device includes a plurality of DRAM memory cells each having first, second, and third MOS transistors; a plurality of first word lines coupled to the gates of the first MOS transistors; a plurality of second word lines coupled to the gates of the second MOS transistors; a plurality of first bit lines coupled to the source/drain paths of the first MOS transistors; and a plurality of second bit lines coupled to the source/drain paths of the second MOS transistors. The plurality of DRAM memory cells includes a series of such memory cells defining a plurality of groups of k memory cells, and the plurality of first word lines includes a group of k first word lines, each of which is coupled to a gate of a first MOS transistor only in every kth DRAM memory cell of the series, wherein k is greater than one.

Abstract: A system-on-chip (SOC) device or a random access memory (RAM) chip includes a RAM block. The RAM block includes memory cells, each of which has three transistors. Each memory cell is coupled to both a read bit line and a write bit line. A transparent continuous refresh mechanism has been implemented to read the content of a memory cell and re-write it back to the memory cell without disturbing the access (read/write) cycle, making refresh operations transparent to the system level. The continuous refresh mechanism includes a collision detection mechanism to prevent writing and reading the same memory cell at the same time.

Abstract: A memory cell having first and second access transistors coupled to a storage transistor is disclosed. The access transistors are high gate threshold voltage transistors to reduce leakage current in the memory cell. The gate threshold voltage of the access transistors are, for example, 0.1 to 0.4V higher than typical transistors. Reducing leakage current advantageously improves the retention time of the memory cell.

Abstract: A semiconductor integrated circuit is disclosed, in which a memory is activated at high speed in commensurate with a high-speed logic circuit mounted with the memory in order to reduce the cost using a DRAM of a 3-transistor cell requiring no capacitor. A pair of data lines connected with a plurality of memory cells having the amplification function are set to different precharge voltage values, thereby eliminating the need of a dummy cell. The elimination of the need of the dummy cell unlike in the conventional DRAM circuit using a gain cell reduces both the required space and the production cost. A hierarchical structure of the data lines makes a high-speed operation possible. Also, a DRAM circuit can be fabricated through a fabrication process matched with an ordinary logic element.

Abstract: A system-on-chip (SOC) device or a random access memory (RAM) chip includes a RAM block. The RAM block includes memory cells, each of which has three transistors. Each memory cell is coupled to both a read bit line and a write bit line. A transparent continuous refresh mechanism has been implemented to read the content of a memory cell and re-write it back to the memory cell without disturbing the access (read/write) cycle, making refresh operations transparent to the system level. The continuous refresh mechanism includes a collision detection mechanism to prevent writing and reading the same memory cell at the same time.

Abstract: A semiconductor integrated circuit is disclosed, in which a memory is activated at high speed in commensurate with a high-speed logic circuit mounted with the memory in order to reduce the cost using a DRAM of a 3-transistor cell requiring no capacitor. A pair of data lines connected with a plurality of memory cells having the amplification function are set to different precharge voltage values, thereby eliminating the need of a dummy cell. The elimination of the need of the dummy cell unlike in the conventional DRAM circuit using a gain cell reduces both the required space and the production cost. A hierarchical structure of the data lines makes a high-speed operation possible. Also, a DRAM circuit can be fabricated through a fabrication process matched with an ordinary logic element.

Abstract: A memory cell having first and second access transistors coupled to a storage transistor is disclosed. The access transistors are high gate threshold voltage transistors to reduce leakage current in the memory cell. The gate threshold voltage of the access transistors are, for example, 0.1 to 0.4V higher than typical transistors. Reducing leakage current advantageously improves the retention time of the memory cell.

Abstract: A memory module stores digital data. The memory module has many memory cells biased by a voltage source. Each memory cell has an access transistor electrically connected to a word line and a bit line for receiving bits from the bit line when the word line turns on the access transistor, a switching circuit electrically connected to the access transistor, and a capacitor electrically connected to the switching circuit. The switching circuit turns on or off according to the bit from the access transistor. The capacitor stores charge supplied by the switching circuit when the switching circuit turns on. The capacitor stores charge supplied by the voltage source when the switching circuit turns off. When the access transistor turns off, the switching circuit or the voltage source provides charge to the capacitor to sustain the voltage level of the capacitor to compensate for charge leakage of the capacitor.

Abstract: A system-on-chip (SOC) device or a random access memory (RAM) chip includes a RAM block. The RAM block includes memory cells, each of which has three transistors. Each memory cell is coupled to both a read bit line and a write bit line. A transparent continuous refresh mechanism has been implemented to read the content of a memory cell and re-write it back to the memory cell without disturbing the access (read/write) cycle, making refresh operations transparent to the system level. The continuous refresh mechanism includes a collision detection mechanism to prevent writing and reading the same memory cell at the same time.

Abstract: A memory organized as a two-dimensional array of data storage cells having a plurality of rows and columns. Each data storage cell has first, second, third, and fourth terminals, each data storage cell sinking a current between the first and second terminals indicative of a charge stored therein when the third terminal is at a first potential. The memory has a plurality of bit lines, one corresponding to each column. The first terminal of each data storage cell in each column is connected to the bit line corresponding to that column when the third terminal is at the first potential and each data storage cell is disconnected from that bit line when the third terminal is at a second potential. The memory also includes a plurality of column select lines and row select lines. There is one column select line corresponding to each column and one additional column select line adjacent to either the first or last column.

Abstract: An RF power amplifier is provided for use with wireless transmission systems such as cellular phones. An RF power amplifier includes direct drive amplifier circuitry operating in a push-pull scheme. The RF power amplifier includes a pair of switching devices driven by a pair of mutually coupled inductive devices. The inductive devices may be magnetically or capacitively coupled together. The RF power amplifier may be formed on a single integrated circuit and include an on-chip bypass capacitor. The RF power amplifier may utilize a voltage regulator for providing a regulated voltage source. The RF power amplifier may be provided using a dual oxide gate device resulting in an improved amplifier. The RF power amplifier may be packaged using flip chip technology and multi-layer ceramic chip carrier technology.

Abstract: A semiconductor memory cell is configured using a sense amplifier and a memory cell containing MOS transistors. In a write cycle, the sense amplifier inputs write data to accumulate charges in the memory cell. In a read cycle, the sense amplifier outputs read data in response to the charges accumulated in the memory cell. A cell array is configured using sense amplifiers and memory cells, which are arranged in a matrix form in such a way that each sense amplifier is connected with the memory cells which are arranged in a same column. In addition, a pair of a write word line and a read word line are shared by the memory cells which are arranged in a same row, while a pair of a write bit line and a read bit line are shared by the memory cells which are arranged in a same column. Further, the sense amplifier is connected with the pair of the write bit line and read bit line. The write word line is arranged between the read word line and a ground line having a ground level.

Abstract: A semiconductor memory device comprising a write transistor with a gate connected to a write word line and with a first impurity region forming a source or drain connected to a bit line, a read transistor with a gate connected to a second impurity region forming a source or drain of the write transistor, a first impurity region connected to a read word line, and a second impurity region connected to a bit line, and a capacitor connected between the gate and the second impurity region of the read transistor.

Abstract: A semiconductor memory cell is configured using a sense amplifier and a memory cell containing MOS transistors. In a write cycle, the sense amplifier inputs write data to accumulate charges in the memory cell. In a read cycle, the sense amplifier outputs read data in response to the charges accumulated in the memory cell. A cell array is configured using sense amplifiers and memory cells, which are arranged in a matrix form in such a way that each sense amplifier is connected with the memory cells which are arranged in a same column. In addition, a pair of a write word line and a read word line are shared by the memory cells which are arranged in a same row, while a pair of a write bit line and a read bit line are shared by the memory cells which are arranged in a same column. Further, the sense amplifier is connected with the pair of the write bit line and read bit line. The write word line is arranged between the read word line and a ground line having a ground level.

Abstract: A three terminal non-volatile memory element includes a standard (low voltage) CMOS transistor, i.e. a storage transistor, having a drain coupled to a read bit line and a source connected to ground. The storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. Of importance, in submicron technology, the source and drain regions of the storage transistor merge, thereby providing a highly reliable, conductive path. Thus, the state of the memory cell can be advantageously read solely via the read bit line.

Abstract: A dynamic random access memory. The memory includes a write transistor N3 and a read transistor N2. In a preferred embodiment the write transistor has a threshold level higher than the read transistor. A sense amplifier senses and amplifies a difference in voltage between a bit line and a sense node that is developed when the read transistor permits or does not permit current to flow between ground an a bit line. Associated semiconductor device structures and fabrication techniques are also disclosed.

Abstract: A non-volatile memory cell (81) includes a drain-side select transistor (86), a source-side select transistor (87), and a storage transistor (88). The drain-side select transistor (86) is adjacent to the drain of the storage transistor (88) to prevent drain-disturb events. The source-side select transistor (87) is adjacent to the source of the storage transistor (88) to prevent source-disturb events. The select gate (152) of the drain-side select transistor (86), the select gate (143) of the source-side select transistor (87), and the floating gate (147) of the storage transistor (88) are formed on a dielectric layer (123) having a uniform thickness.

Abstract: A memory cell with a stored charge on its gate, comprising (A) a channel forming region, (B) a first gate formed on an insulation layer formed on the surface of the channel forming region, the first gate and the channel forming region facing each other through the insulation layer, (C) a second gate capacitively coupled with the first gate, (D) source/drain regions formed in contact with the channel forming region, one source/drain region being spaced from the other, and (E) a non-linear resistance element having at least two ends with one end connected to the first gate.

Abstract: A non-volatile memory cell is provided that includes a low voltage CMOS storage transistor having a source region and a drain region that are commonly connected to ground. The low voltage storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. The high programming voltage is applied to the low voltage storage transistor through a high voltage p-channel transistor. The high voltage p-channel transistor has a thicker gate oxide than the storage transistor, thereby enabling the p-channel transistor to withstand higher voltages. The high voltage p-channel transistor also has a higher breakdown voltage than a high voltage n-channel transistor of the same size. Both the low voltage storage transistor and the high voltage p-channel transistor are fabricated in accordance with a standard sub 0.35 micron process.

Abstract: A non-volatile memory cell includes a well region formed in a semiconductor substrate. First and second avalanche injection elements reside in the well region. A bifurcated floating-gate electrode includes a first segment overlying the first avalanche injection element and a second segment overlying the second avalanche injection element. A first contact region resides in the well region adjacent to the first segment of the floating-gate electrode, and a second contact region resides in the well region adjacent to the second segment of the floating-gate electrode. Upon the application of programming or erasing voltage, electrical charge is independently transferred to each of the first and second segments of the floating-gate electrode from the first and second avalanche injection elements, respectively.

Abstract: A zero-power non-volatile memory cell includes a control element, an avalanche injection element, and a CMOS inverter. A floating-gate electrode is capacitively coupled to the control element, the avalanche injection element, and to the CMOS inverter. The avalanche injection element is arranged, so as to transfer electrical charge onto the floating-gate electrode. The presence of stored data within the memory cell is indicated by reading a supply voltage V.sub.DD at an output terminal of the inverter. Accordingly, data can be read from the non-volatile memory cell without applying electrical power to the cell.

Abstract: Methods are disclosed in making a multi-state dynamic memory using a three transistor cell. The cell construction is consistent with a logic semiconductor process and is therefore useful for embedded memory applications. Considerations are given to write levels, read levels, reference devices, and sense amplifier design. Two cell enhancements are proposed: substituting a PFET in place of and NFET for the write select transistor so that improved noise margin can be achieved and adding a capacitor for extended refresh times. Methods are also introduced to reduce select transistor leakage current during the deselected state.

Abstract: A semiconductor memory device includes cells arranged in a matrix formation. Each of the cells includes a driver transistor, a read transistor which is controlled by a read word line and outputs read data read from the cell to a read bit line, a write transistor which is controlled by a write word line and supplies write data supplied from a write bit line to a cell capacitor connected to a gate of the driver transistor, and a column write select transistor which is controlled by a column write select signal line and is connected to the write transistor in series. The write data is supplied to the cell capacitor via both the column write select transistor and the write transistor.

Abstract: A nondestructive read, three device BICMOS gain cell for a DRAM memory having two FETs and one bipolar device. The gain cell has an improved access time (less latency), can operate for longer periods of time before a refresh operation is required, requires a smaller storage capacitance than a traditional DRAM cell, and can be produced commercially at lower costs than are presently available. In a preferred embodiment, the gain cell comprises an n channel metal oxide semiconductor field effect write transistor having its gate connected to a write word line WLw. Its drain is connected to a storage node Vs having a storage capacitance Cs associated therewith, and its source is connected to a write bit line BLw. An n channel metal oxide semiconductor field effect read transistor has its gate connected to the storage node Vs and its source connected to a read word line WLr. A PNP transistor has its base connected to the drain of the read transistor and its emitter connected to a read bit line BLr.

Abstract: The present invention discloses a static random access memory cell having a reduced cell size and method of manufacturing the same. According to the invention, the SRAM cell includes: a word line and a bit line; an access device connected to the word and bit lines, wherein in case that the word line is selected, the access device outputs data inputted from the bit line; a pull-up device connected to the access device as well as to a predetermined power voltage, wherein the pull-up device operates in pull-up manner according to the data inputted from the access device; and a pull-down device connected to the access device and the pull-up device as well as to a ground, wherein the pull-down device operates in pull-down manner according to the data inputted from the access devices.

Abstract: A semiconductor memory in which integration is enhanced is provided. An NMOS transistor Qn1 has a gate connected to a write word line WWLn, a source connected to a write bit line WBLn, and a drain connected to a node N1. An NMOS transistor Qn2 has a gate connected to a read word line RWLn and a source connected to a read bit line RBLn. An NMOS transistor Qn3 has a gate connected to the drain of the NMOS transistor Qn1, a source connected to a ground level, and a drain connected to the drain of the NMOS transistor Qn2. An NMOS transistor Qn4 has a gate connected to a ground level, a source connected to the source of the NMOS transistor Qn3, and a drain connected to the drain of the NMOS transistor Qn1. The NMOS transistor Qn4 is kept off so that the drain of the NMOS transistor Qn1 is dielectrically isolated from the source of the NMOS transistor Qn3.

Abstract: A semiconductor memory device of a three-transistor cell type dynamic random-access memory with improved performances includes a circuit arranged between a write bit line and a read bit line. During a read operation, the circuit generates a voltage difference responsive to information that is stored in the memory cell during a read operation. A latch-type sense amplifier amplifies and latches the voltage difference between the write bit line and the read bit line. When information is read from a memory cell, the information in the memory cell amplified by the latch-type sense amplifier is read through the read bit line while being written to the memory cell via the write bit line to refresh the information in the memory cell.

Abstract: A memory circuit which enables storage of more than two logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by a charge stored on the transistor's gate. By enabling the current to be detected in discrete increments, it becomes possible to represent more than one bit of information with the charge stored in the memory cell. Usage of additional increments necessitates more precise storage and detection circuitry. In one embodiment, the storage circuitry uses feedback to obtain a greater logic state retrieval accuracy.

Abstract: An enhanced, scalable EEPROM memory cell is provided with a structure having a plurality of half-height tunnel oxide depletion mode transistors. The structure further has individual wordlines controlling the write and read transistors, respectively. With such a structure, lower voltages are used to program/erase the memory cell. The memory cell is scalable to small dimensions through the use of transistors having half-height tunnel oxide regions.

Abstract: A system and method for reading multi-bit memory cells. The invention resides in employing a plurality of comparators to compare the voltage contained in a multi-bit memory cell with a reference voltage, where each comparator is associated with a single pair of bit lines. For each pair of bit lines, a first bit line is coupled to a multi-bit memory cell and a second bit line is coupled to a dummy cell containing a reference voltage. The first bit line is also coupled to a data bus. The data bus is configured to connect the first bit line to a first input of each of a plurality of comparators that are associated with other bit lines and memory cells. Each comparator has a unique reference voltage applied to its second input. Each comparator compares the voltage on the first bit line with the applied reference voltage and outputs the result of this comparison to a controller.

Abstract: A DRAM memory having shared read/write lines. The DRAM memory is comprised of an array of 3T memory cells. Data is digitally stored in the form of capacitors that are either charged or discharged. Horizontal data lines are used to convey data bits to be stored in the array of memory cells. Vertical read/write lines are used to perform both read and write functions. Activating a single read/write line causes a bit of data from a memory cell to be placed onto a corresponding data line. Simultaneously, an inverted copy of that data bit is stored in an adjacent memory cell. Hence, instead of having a separate read line and a separate word line for each memory cell, the present invention has a dual function read/write word line.

Abstract: A memory cell structure for a semiconductor device includes a capacitor for storing electric charge, a first transistor for controlling storage and release of charge in the capacitor, and a second transistor interposed in a conduction path which connects the capacitor and the first transistor to each other. The second transistor serves as a cut-off transistor for interrupting the electrical connection between a charge storing capacitor and the first transistor when the capacitor is in the charged state, to thereby prevent effectively the charge from leaking by way of the source region of the first transistor. A dynamic semiconductor memory device includes a memory cell array having a plurality of memory cells of this.

Abstract: A memory is formed from an array of switchless integrated circuit memory cells in a high-density configuration. These cells comprise a capacitor and two diodes in a configuration where one diode is used to charge one pole of the capacitor, and the other diode is used to discharge it from that same pole, over separate paired lines used respectively for charging and discharging, as well as reading. The other pole of the capacitor is tied to a single line used for both charging and discharging, and in support of reading. Drive and sense circuitry located at the periphery of the cell array is used to perform interconnect switching functions while writing or reading charges on cells in the array. Alternative high-density switched cell variations are also described. The cell arrays are fabricated on monolithic integrated circuits which are interconnected with one another by using a method which deposits and etches conductive material which links conductive traces between the monolithic dice.

Abstract: A memory device includes a first address signal line, a pair of second address signal lines, a standby signal line, and a memory cell provided at a cross point at which the first address signal line crosses the pair of second address signal lines. The memory cell includes first and second elements connected, via a connection node, in series between the pair of second address signal lines in a forward direction, each of the first and second elements having a negative-differential conductance characteristic. A threshold diode is connected between the first address signal line and the connection node, and has a characteristic in which a current flows in the threshold diode when a voltage applied across the threshold diode exceeds threshold voltages. A gate is connected to the standby signal line and controls currents flowing in the first and second elements.

Abstract: A dynamic random access memory. The memory includes a write transistor N3 and a read transistor N2. In a preferred embodiment the write transistor has a threshold level higher than the read transistor. A sense amplifier senses and amplifies a difference in voltage between a bit line and a sense node that is developed when the read transistor permits or does not permit current to flow between ground an a bit line. Associated semiconductor device structures and fabrication techniques are also disclosed.

Abstract: A single poly EE cell and an array using said cell, with the array being provided electrical connections such that the select gate for the read select transistor and the select gate for the write select transistor may be separately controlled. In the array, first level metal is utilized for connection to the gates of the read and write select transistors and second level metal is utilized for connection to the product term connections of the cell.

Abstract: A current memory cell for sampling a current (I) at a current terminal (5) during a sample interval and for applying the current (I) to the current terminal (5) during a hold interval. A first switch (S1) connects a PMOS transistor (P1) as a diode during the sample interval and as a current source during the hold interval. During the sample interval the current in the current terminal (5) is mirrored to the PMOS transistor (P1). During the hold interval the current of the PMOS transistor is mirrored to the current terminal. The mirroring is effected by means of two NMOS transistors (N1, N2) and one reversing switch (S2), which reverses the input and output of the current mirror circuit between the sample intervals and the hold intervals. The current mirror circuit (N1, N2) and the PMOS current source (P1) collectively behave as a current sink which is insensitive to the substrate voltages which are caused by the body effect.

Abstract: The gate of a transistor Q1 serving as a selection transistor is connected to a word line and the source thereof is connected to a bit line BL. The gate of a transistor Q2 serving as a cell capacitor is connected to the drain of the transistor Q1 and the drain thereof is connected to a pulse generation circuit. Whether an inverted layer is formed in the channel region of the transistor Q2 or not is determined according to the stored data. An inverted layer is formed in the channel region of the transistor Q2 having data "1" stored as storage data. The source of the transistor Q2 is connected to the gate of a transistor Q3. The drain of the transistor Q3 is connected to a pulse generation circuit 11 and the source thereof is connected to the drain of the transistor Q1. The transistor Q2 having an inverted layer formed therein is turned on when a preset voltage is supplied from the pulse generation circuit 11 in the stored data reading operation, and in this case, the transistor Q3 is turned on.

Abstract: A floating gate memory device comprises a channel for conducting carriers from source to drain, a semiconductor heterostructure forming a potential well (floating gate) for confining carriers sufficiently proximate the channel so as to at least partially deplete it, and a graded bandgap injector region between the control gate and the floating gate for controlling the injection of carriers into and out of the potential well. Also described is a three element memory cell, including the memory device and two FETs, which operates from a constant, non-switched supply voltage and two-level control voltages. Arrays of memory devices may also be used to detect light in a variety of applications such as imaging.

Abstract: A memory cell array (61) comprises a plurality of three-transistor type memory cells (10) arranged in a plurality of rows and columns. A plurality of pairs of write bit lines (WB1, WB2) and a plurality of read bit lines (RB) are provided corresponding to each column of the memory cell array (61). The plurality of write word lines (WWL) and the plurality of read word lines (RWL) are provided corresponding to each row of the memory cell array (61). Information is written to memory cells (10) in odd rows through the respective one write bit lines of the pairs of write bit lines (WB1, WB2), and information is written to memory cells (10) in even rows through the respective other write bit lines of the pairs of write bit lines (WB1, WB2). A sense amplifier (30) is connected to each of the pairs of write bit lines (WB1, WB2). At the time of write operation, refresh operation is performed by the sense amplifier (30) with respect to memory cells (10) in non-selected columns.

Abstract: The memory cell of the present invention is a three transistor cell, including two floating gate MOS transistors connected in series with a select transistor. The source of the first memory cell floating gate memory transistor is connected to a source of a first potential. Its gate is connected to a first sense line. Its drain is connected to the source of the second memory cell floating gate transistor. The gate of the second memory cell floating gate transistor is connected to a second sense line. The drain of the second memory cell floating gate transistor is connected to the source of a select transistor. The gate of the select transistor is connected to a word line. The source of the select transistor is connected to a bit line.A plurality of memory cells may be connected together as a byte, and may be placed in an array. The gates of the select transistors are connected together.

Abstract: A read only memory device including: a memory cell array having a plurality of memory cells each storing one of three states; selection means, connected to the memory cell array, for selecting a pair of the memory cells from the memory cell array simultaneously in accordance with an address signal; a first sense amplifier, operatively connected to one of the pair of the memory cells, for producing a three bit output corresponding to the state stored in the one of the pair of the memory cells selected by the selection means; and a second sense amplifier, operatively connected another of the pair of memory cells, for producing a three bit output corresponding to the state stored in the another of the pair of the memory cells selected by the selection means.

Abstract: There is disclosed a semiconductor memory cell comprising a capacitor for storing charges between a data writing MOS transistor and a data reading MOS transistor.

Abstract: An electrically erasable programmable semiconductor memory cell having an associated conducting column line, read/write line, sense line and row line includes a floating gate transistor which controls the discharge of the read/write line to the column line during read cycles. During write cycles and precharging of said read/write line the column line is made electrically floating so that a faster precharge time and hence access time is obtained and so that access time is independent on the conducting state of the floating gate transistor resulting at commencement of a read cycle.

Abstract: In a 3-transistor random access memory for dynamic operation, the invention discloses a structure in which one of the transistors is stacked on the other transistor. A transistor for writing is disposed on a transistor for reading, and one of its terminals is used in common with the gate electrode of a transistor for judging data. The other terminal is connected to one of the terminals of the transistor for reading.A memory cell capable of extremely large scale integration can be obtained.

Abstract: A memory cell comprises a substrate of a first conductivity type (preferably N type) in which is formed a first region of opposite conductivity type. Second, third and fourth regions of first conductivity type are then formed in the first region, said second and third regions being separated by a first portion of the first region and said third and fourth regions being separated by a second portion of the first region. A fifth region of first conductivity type is then formed in the second portion of the first region and a first electrode is attached to the fifth region. This electrode is electrically isolated from the second, third and fourth regions and extends on insulation over the first portion of said first region to said second region and also extends over said third region and a part of the second portion of said first region. This electrode is covered by insulation.

Abstract: An integrated circuit memory cell (10) having a bit line (12), a word line (14) and a cell voltage supply (26) is provided. The integrated circuit memory cell (10) includes a first clock line (34) and a second clock line (36). A first transistor (20) is interconnected to the bit line (12) and the word line (14) for providing access to the memory cell (10). A second transistor (22) is interconnected to the cell voltage supply source (26) and to the first transistor (20) thereby defining a first node (S). The second transistor (22) provides a charging path from the cell voltage supply source (26) to the first node (S). A capacitor (30) is provided and interconnects the first clock line (34) and the second transistor (22). The interconnection between the capacitor (30) and the second transistor (22) defines a second node (K).

Abstract: A semiconductor memory device forming a static type memory cell uses three field effect transistors. One is connected between a storage node and a bit line so it functions as an access transistor. The storage node is connected to a refresh node through a second transistor having its gate shorted to drain, and the third transistor connects the refresh node to a supply voltage. A voltage dependent capacitor connects the refresh node to a refresh clock. A logic 1 on the storage node turns on the third transistor and charges the refresh node, which turns on the capacitor so the refresh clock is coupled through to turn on the second transistor and refresh the storage node. When a logic 0 is stored, this will not happen.