Abstract: The disclosed technology teaches a memory device with memory cells, each with a sense circuit with an input node in current flow communication, a BLC transistor, a transfer transistor, a current source transistor, and an output circuit to generate data based on a voltage on the sensing node. Also disclosed is a sensing sequence in which control circuits apply BLC voltage to the BLC transistor, transfer voltage to the transfer transistor and current control voltage to the current source transistor to provide a charging current to the BL, and to adjust the current control voltage to provide a keeping current on the BL from the current source transistor, and to apply a read voltage to a selected memory cell on the bit line. Additionally included is applying a timing signal to the output circuit to generate the data based on a voltage on the sensing node.

Abstract: Systems, devices, and methods for direct memory access. A system direct memory access (SDMA) device disposed on a processor die sends a message which includes physical addresses of a source buffer and a destination buffer, and a size of a data transfer, to a data fabric device. The data fabric device sends an instruction which includes the physical addresses of the source and destination buffer, and the size of the data transfer, to first agent devices. Each of the first agent devices reads a portion of the source buffer from a memory device at the physical address of the source buffer. Each of the first agent devices sends the portion of the source buffer to one of second agent devices. Each of the second agent devices writes the portion of the source buffer to the destination buffer.

Abstract: Memory devices and methods of repairing a memory are provided. A first array includes normal memory cells, and a second array includes repair memory cells. The repair memory cells are configured to be used in place of the normal memory cells. A look-up table comprises memory bitcells configured to store a set of entries including addresses of defective memory cells of the normal memory cells. A match circuit is configured to evaluate whether an input memory address is stored as a defective address in the memory bitcells. The match circuit is also configured to generate a selection signal for selecting the normal memory cells or the repair memory cells based on the evaluation.

Abstract: An architecture of the memory device may leverage a transmission path resistance compensation scheme for memory cells to reduce the effect of parasitic loads in accessing a memory cell. A memory cell of such a memory device may experience a total resistance including a transmission path resistance associated with the respective access lines of the memory cell and an added compensatory resistance. The foregoing memory device may leverage a spike mitigation scheme to mitigate the harmful effect of a voltage and/or rush current to the near memory cells of the memory device. In addition, spike mitigation circuitry may include coupling a resistor on access lines near the respective decoders. Further, spike mitigation circuitry may include coupling a resistor between the decoders.

Abstract: A memory device is disclosed that includes a row of storage locations that form plural columns. The plural columns include data columns to store data and a tag column to store tag information associated with error locations in the data columns. Each data column is associated with an error correction location including an error code bit location. Logic retrieves and stores the tag information associated with the row in response to activation of the row. A bit error in an accessed data column is repaired by a spare bit location based on the tag information.

Abstract: Memory devices, systems, and associated methods with per die temperature-compensated refresh control, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory cells and a sensor configured to measure a temperature of the memory device. The memory device determines a frequency at which it is receiving refresh commands. The memory device is further configured to skip refresh operations of the memory cells based, at least in part, on the determination and on the temperature of the memory device.

Abstract: A memory device includes a data storage region and a spare column remap storage. The data storage region includes a plurality of sub-arrays, and each of the plurality of sub-arrays has a plurality of main columns and a plurality of spare columns. The spare column remap storage includes a plurality of storage units storing column address information of a repaired main column of one of the plurality of sub-arrays and address information of a repaired main column of another of the plurality of sub-arrays into at least one of the plurality of storage units included in the spare column remap storage.

Abstract: A circuit includes a first driver, a second driver, and a burst mode control circuit coupled to the first and second drivers. The burst mode control circuit is configured to implement a burst mode operation having a burst soft-on portion and a burst portion. During the soft-on portion of the burst mode operation, the burst mode control circuit is configured to cause the first and second drivers to produce a first set of pulses of increasing pulse width. During the burst portion of the burst mode operation, the burst mode control circuit is configured to cause the first and second drivers to produce a second set of pulses of a constant pulse width.

Abstract: A method for forming a high dielectric constant (high-?) dielectric layer on a substrate including performing a pre-clean process on a surface of the substrate. A chloride precursor is introduced on the surface. An oxidant is introduced to the surface to form the high-? dielectric layer on the substrate. A chlorine concentration of the high-? dielectric layer is lower than about 8 atoms/cm3.

Abstract: A method of operating a memory macro includes receiving a first signal indicating a first operational mode of the memory macro, receiving a second signal indicating a second operational mode of the memory macro, generating, by a first logic circuit, a third signal and a fourth signal based on the first signal and a fifth signal thereby causing a change in the first operational mode of the memory macro, and generating, by a second logic circuit, the fifth signal and a sixth signal based on at least the second signal and thereby causing a change in the second operational mode of the memory macro. The first logic circuit is coupled to a first memory cell array and a first IO circuit. The second logic circuit is coupled to a first and second set of word line driver circuits.

Abstract: A sequencing device has at least one sequencing channel configured to fluidically connect a first gap with a second gap. The sequencing channel is formed as a cavity in the region of the first gap and is formed as a pore in the region of the second gap. The pore has a smaller cross section than the cavity.

Abstract: Memory devices are disclosed. A memory device may include a number of fuses and a number of transmit lines configured to transmit data from the number of fuses. The memory device may also include a number of monitoring circuits. Each monitoring circuit of the number of monitoring circuits is coupled to a transmit line of the number of transmit lines. Each monitoring circuit comprises logic configured to receive the data from the number fuses via the transmit line. The logic is further configured to generate a result responsive to the data and indicative of pass/fail status of the transmit line. Associated methods and systems are also disclosed.

Abstract: A method and apparatus for implementing power up detection in a power down cycle to dynamically determine whether a failed component in a system prevents another Initial Program Load (IPL) or re-IPL, or result in a loss of resources. Predefined mandatory functions are called to collect power down/up data that prevents re-IPL, or results in the reduction of resources. A user is notified, allowing the customer to continually utilize the system, while ordering hardware to be replaced.

Abstract: Embodiments of information handling systems (IHS) and computer implemented methods are disclosed herein to proactively restore missing firmware components to a computer readable storage device of an IHS. In one embodiment, a method may execute a first set of program instructions, before an operating system (OS) is loaded into a system memory of the IHS, to determine if one or more firmware components previously stored within the computer readable storage device is/are missing. If the first set of program instructions determines at least one firmware component is missing, the method may execute additional program instructions to retrieve a copy of the missing firmware component(s) from a remotely located system, and store the retrieved copy of the missing firmware component(s) within the computer readable storage device. The additional program instructions can be executed before the OS is loaded in some embodiments, and after the OS is loaded in other embodiments.

Abstract: A method for a memory subsystem redundancy with priority decoding is described. The method includes dynamically repairing a local input/output (IO) unit of a first memory subsystem bank based on a current redundancy fuse input pattern of the first memory subsystem bank. The method also includes concurrently generating a redundancy shift signal in each global IO based on the current redundancy fuse input pattern to shift the repaired local IO unit and lower order local IO units of the first memory subsystem bank relative to the repaired local IO unit.

Abstract: A memory system includes a memory medium including a plurality of matrices and a plurality of data input/output (I/O) terminals, a row address adding circuit configured to add row address additive values to an input row address for accessing memory cells of the plurality of matrices, and a column address adding circuit configured to add column address additive values to an input column address for accessing to memory cells of the plurality of matrices. The plurality of matrices are configured into a plurality of matrix sub-groups, wherein each matrix sub-group includes matrices accessed through the same data I/O terminal. The row address additive values are different from each other according to the matrix sub-groups, and the column address additive values are different from each other according to the matrix sub-groups.

Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

Abstract: According to one general aspect, an apparatus may include a plurality of stacked integrated circuit dies that include a memory cell die and a logic die. The memory cell die may be configured to store data at a memory address. The logic die may include an interface to the stacked integrated circuit dies and configured to communicate memory accesses between the memory cell die and at least one external device. The logic die may include a reliability circuit configured to ameliorate data errors within the memory cell die. The reliability circuit may include a spare memory configured to store data, and an address table configured to map a memory address associated with an error to the spare memory. The reliability circuit may be configured to determine if the memory access is associated with an error, and if so completing the memory access with the spare memory.

Abstract: Disclosed is a memory cell including parallel-connected first access transistors and a first variable resistor in series between a bitline and a source line and parallel-connected second access transistors and a second variable resistor in series between the bitline and the source line. A write wordline controls one pair of first and second access transistors so that, during an initialization mode, the resistors are concurrently subjected to the same write bias conditions for one-time programming to switch from an unprogrammed state (where the resistors have the same first resistance state) to a programmed state (where one resistor has switched to a second resistance state and a bit is stored). Discrete first and second read wordlines control another pair of first and second access transistors to enable discrete read processes associated with the first and second variable resistors. Also disclosed are an associated circuit (e.g., a PUF) and a method.

Abstract: A memory device and a refresh method thereof are provided. The memory device includes a memory array and a controller. The memory array includes a plurality of normal areas and a redundancy area near the plurality of normal areas. The redundancy area includes a plurality of redundancy word lines. A plurality of boundary word lines are arranged near boundaries between the plurality of normal areas and the redundancy area. The controller refreshes the plurality of redundancy word lines in sequence, and refreshes the plurality of boundary word lines in sequence after refreshing the plurality of redundancy word lines in sequence.

Abstract: A memory arrangement comprises a non-volatile memory plane (2), a replacement plane (3), an address select block (302), and a counter arrangement (300) having at least one counter (310 to 312). The at least one counter (310 to 312) is configured to be incremented at a write cycle of the memory arrangement (1). The address select block (302) is configured to switch from the non-volatile memory plane (2) to the replacement plane (3), if a counter value of the at least one counter (310 to 312) is higher than a predetermined limit.

Abstract: Methods, apparatuses and systems related to managing access to a memory device are described. A memory device includes fuses and latches for storing a repair segment locator and a repair address for each repair of one or more defective memory cells. A segment-address determination circuit generate an active segment address based on the repair address according to the repair segment locator and an address for a read or a write operation. A comparator circuitry is configured to determine whether the active segment address matches the address for the read or the write operation for replacing the one or more defective memory cells with the plurality of redundant cells when the address for the read/write operation corresponds to the one or more defective memory cells.

Abstract: A memory apparatus includes a pseudo static random access memory and a controller. The controller is configured to provide an external command to the pseudo static random access memory. When the memory apparatus starts a burst read operation or a burst write operation, the controller provides a plurality of page starting addresses to the pseudo static random access memory, and the pseudo static random access memory sequentially performs the burst read operation or the burst write operation according to a sequence of receiving the page starting addresses.

Abstract: A memory decoder enables the selection of a conductor of a row or column of a crosspoint array memory. The decoder includes a circuit to apply a bias voltage to select or deselect the conductor. The conductor can be either a wordline or a bitline. The decoder also includes a select device to selectively provide both high voltage bias and low voltage bias to the circuit to enable the circuit to apply the bias voltage. Thus, a single end device provides either rail to the bias circuit.

Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.

Abstract: A semiconductor memory device has a memory cell array area including a normal area including memory blocks and a redundant memory area including a redundant block which is a replacement target of a defective block among memory blocks; a storage unit storing address information indicating a position of the defective block in the normal area and address information indicating a position of the redundant block being the replacement target of the defective block, both being in association with each other as a first information; and an output circuit outputting a data row exhibiting a positional relation between the defective block and a memory block other than the defective block in the normal area based on the first information stored in the storage unit in response to the data read signal.

Abstract: A non-volatile storage device includes a non-volatile storage circuit including a plurality of fuse sets suitable for sequentially outputting fuse data according to a counting address, each fuse set including an enable fuse, a plurality of address fuses, and a duplication fuse; a read control circuit suitable for receiving the fuse data, and outputting latch data by selectively masking data of the enable fuse and the address fuses using data of the duplication fuse within the received fuse data; and a program control circuit suitable for controlling programming the duplication fuse of a duplicated fuse set among the fuse sets when a repair address inputted from outside is identical to data of the address fuses within the duplicated fuse set, or to program the repair address into an available fuse set among the fuse sets, according to a program mode signal.

Abstract: A volatile memory device is configured to self-document by identifying its own bad or at-risk excludable memory locations in a nonvolatile identification embedded in itself, without using additional board real estate. The identification of bad or at-risk memory is readable by firmware outside the device. The device includes volatile memory cells that have respective failure susceptibility values, some of which indicate bad or at-risk memory cells. The memory device also includes read logic and write logic, and may include refresh logic. The identification may be embedded in the device by blowing fuses in an adaptation of self-repair activity, or by writing identification data into a serial presence detect logic, for example. The configured memory device may efficiently, persistently, and reliably provide detailed memory test results regarding itself, thereby allowing customers to accept and safely use memory that would otherwise have been discarded to prevent software crashes.

Abstract: A device includes a first memory including a plurality of memory dice that are arranged vertically to each other, a second memory of a second type, and a controller die that transfers first data between the first memory and a first internal memory of a processor using a first interface and that transfers second data between the second memory and a second internal memory of the processor using a second interface. The first and second memory types are different types of memories. The first and second interfaces are different from each other. The first and second internal memories are different from each other.

Abstract: In some examples, a circuit for use with a fluid ejection device includes a plurality of decoders responsive to a common address to activate respective control signals at different times for selecting respective memories of the fluid ejection device. Each respective decoder of the plurality of decoders comprising a discharge switch to deactivate a control signal of the respective decoder while another decoder of the plurality of decoders is activating a control signal in response to the common address.

Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.

Abstract: Consecutive logical block addresses (LBAs) are mapped to consecutive good blocks in a sequence of blocks in a memory device. For each bad block, a mapping process substitutes a next available good block. For a selected LBA, the mapping process determines a number X>1 of bad blocks before, and including, a corresponding block in the sequence, a number Y of bad blocks in the X blocks after the corresponding block in the sequence, and maps the LBA to a block which is X+Y blocks after the corresponding block, or, if the block which is X+Y blocks after the corresponding block is a bad block, to a next good block. The mapping technique can be used for a sequence of blocks in a trimmed die, where a bad block register stores physical block addresses of the trimmed away blocks.

Abstract: Exemplary methods, apparatuses, and systems include determining that data in a group of memory cells of a first memory device is to be moved to a spare group of memory cells. The group of memory cells spans a first dimension and a second dimension that is orthogonal to the first dimension and the spare group of memory cells also spans the first dimension and the second dimension. The data is read from the group of memory cells along the first dimension of the group of memory cells. The data is written to the spare group of memory cells along the second dimension of the spare group of memory cells.

Abstract: An information processing apparatus includes: an acquisition unit that acquires information from an external apparatus that stores data; and a switching unit that, for each item of the data, switches between a first mode in which the acquisition unit acquires attribute information of the data from the external apparatus, and a second mode in which the acquisition unit acquires, from the external apparatus, information for displaying an image that indicates a feature of the data.

Abstract: Methods, apparatuses and systems related to managing access to a memory device are described. A memory device includes a plurality of banks that each include (1) a plurality of memory cells and (2) a plurality of redundant cells configured to replace one or more target memory cells in the plurality of memory cells. A set of shared fuses and latches may be used to store a row address for each repair that may be implemented in one of the plurality of banks. A shared match circuit coupled to the set of shared latches and the plurality of memory banks may be configured to at least partially implement a row repair for the row address for a bank associated with a commanded operation.

Abstract: Structures including non-volatile memory elements and methods of fabricating a structure including non-volatile memory elements. A first non-volatile memory element includes a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. A second non-volatile memory element includes a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. A first bit line is coupled to the first electrode of the first non-volatile memory element and to the first electrode of the second non-volatile memory element. A second bit line is coupled to the second electrode of the first non-volatile memory element.

Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.

Abstract: An apparatus for beam shaping of laser radiation in the form of ultra short pulses includes an achromatic optical device comprising a first substrate having a first Abbe number and a second substrate connected to the first substrate and having a second Abbe number that is different from the first Abbe number. The first and second substrates are arranged to allow the laser radiation to at least partially pass through the first and second substrates in succession, wherein an optically functional transformation boundary surface is disposed on one of the first and second substrates. The optically functional transformation boundary surface allows the laser radiation to pass at least partially, such that a profile of the laser radiation is transformed into a top-hat profile.

Abstract: An efuse circuit adapted for a memory device is provided. The efuse circuit includes a plurality of efuse sets and a control circuit. Each of the plurality of efuse sets includes a plurality of efuses. When a power is turned on, the control circuit detects each of the plurality of efuse sets to generate a detection signal. The control circuit determines whether the efuses of each of the efuse sets are burned according to the detection signal to determine whether to perform a burn operation on the plurality of efuses. When the control circuit determines that at least one of the plurality of efuses is a burned efuse according to the detection signal, the control circuit latches a write data of at least one burned efuse and disables an overwrite operation on the efuse set to which the at least one burned efuse belongs.

Abstract: A method of determining a potential malfunction of a memory device is executable at a supervisory entity computer communicatively coupled to the memory device. The method includes, over a pre-determined period of time, determining a subset of input/output (I/O) operations having been sent to the memory device for processing, applying at least one counter to determine an actual activity time of the memory device during the pre-determined period of time, applying a pre-determined model to generate an estimate of a benchmark processing time for each one of the subset of transactions, calculating a benchmark processing time for the subset of I/O operations, generating a performance parameter based on the actual activity time and the benchmark processing time, and based on an analysis of the performance parameter, determining if the potential malfunction is present in the memory device.

Abstract: A vertically integrated neuro-processor comprises a plurality of neural storage-processing units (NSPU's). Each NSPU comprises at least a neuro-storage circuit and a neuro-processing circuit. The neuro-storage circuit comprises a memory array for storing at least a synaptic weight, while the neuro-processing circuit performs neural processing with the synaptic weight. The memory array and the neuro-processing circuit are vertically stacked and communicatively coupled by a plurality of inter-level connections.

Abstract: There is provided with a control apparatus of an image processing system. The image processing system has a plurality of image capturing apparatuses that capture images of an object from different viewpoints. An obtaining unit obtains a position of the object. A setting unit sets, for a captured image by an image capturing apparatus of the plurality of image capturing apparatuses, priority in accordance with similarity between a viewpoint direction from the position of the object to the image capturing apparatus and a viewpoint direction from the position of the object to another image capturing apparatus of the plurality of image capturing apparatuses.

Abstract: A decoder structure for selecting a column of memory cells in a memory architecture includes an array of decoder cells organized into different rows. Each row includes a plurality of sub-column groups of decoder cells configured to receive a same input signal. Each sub-column group of decoder cells of a row is coupled to a sub-column group of decoder cells of a subsequent row. The decoder structure further includes a plurality of precharge transistors connected to the decoder cells of a row so as to form a plurality of inverter blocks.

Abstract: The present disclosure includes apparatuses, methods, and systems for sensing two memory cells to determine multiple data values. An embodiment includes a memory having a plurality of memory cells and circuitry configured to sense memory states of each of two self-selecting multi-level memory cells (MLC) of the plurality of memory cells to determine multiple data values. The data values are determined by sensing a memory state of a first MLC using a first sensing voltage in a sense window between a first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to a second memory state and sensing a memory state of a second MLC using a second sensing voltage in a sense window between the first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to the second memory state.

Abstract: Methods, systems, and devices for plate node configurations and operations for a memory array are described. A single plate node of a memory array may be coupled to multiple rows or columns of memory cells (e.g., ferroelectric memory cells) in a deck of memory cells. The single plate node may perform the functions of multiple plate nodes. The number of contacts to couple the single plate node to the substrate may be less than the number of contacts to couple multiple plate nodes to the substrate. Connectors or sockets in a memory array with a single plate node may define a size that is less than a size of the connectors or sockets with multiple plate nodes. In some examples, a single plate node of the memory array may be coupled to multiple lines of a memory cells in multiple decks of memory cells.

Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

Abstract: Long term optical memory includes a storage medium composed from an array of silicon nanoridges positioned onto the fused silica glass. The array has first and second polarization contrast corresponding to different phase of silicon. The first polarization contrast results from amorphous phase of silicon and the second polarization contrast results from crystalline phase of silicon. The first and second polarization states are spatially distributed over plurality of localized data areas of the storage medium.

Abstract: A semiconductor memory system includes a memory medium and a data input/output (I/O) pin repair control circuit. The memory medium includes a plurality of memory dies and a spare die. Each of the plurality of memory dies has a plurality of memory regions and a plurality of data I/O pins, and the spare die has a plurality of spare regions and a plurality of data I/O pins. The data I/O pin repair control circuit performs a repair process for replacing an abnormal data I/O pin among the plurality of data I/O pins included in any of the plurality of memory dies with a data I/O pin of the plurality of data I/O pins included in the spare die.

Abstract: Memory devices incorporating selective boosting techniques and methods for managing memory devices incorporating selective boosting techniques. One or more bit cells of a memory device are tested during a test phase and one or more addresses of one or more weak bit cells are stored in a non-volatile weak bit address memory within the memory device.

Abstract: Apparatuses and methods for decoding addresses for memory are disclosed. An example apparatus includes a memory cell array and a row decoder. The memory cell array includes a bank of memory including a plurality of groups of memory. Each of the groups of memory includes sections of memory, and each of the sections of memory including memory cells arranged in rows and columns of memory. The row decoder decodes addresses to access a first group of memory to include rows of prime memory from a first block of memory and to include rows of prime memory from a second block of memory. The row decoder decodes the addresses to access a second group of memory to include rows of prime memory from the second block of memory and to include rows of redundant memory. The rows of redundant memory are shared with the first and second blocks of memory.