Abstract: A pseudo dual port memory device in which an operating speed is improved and stability is increased is provided. The pseudo dual port memory device may include a memory cell, a pair of bit lines connected to the memory cell, a write driver, a sense amp, and a column multiplexer which is connected to the bit lines, receives a write multiplexer control signal and a read multiplexer control signal, connects the bit lines to the write driver in response to the write multiplexer control signal, and connects the bit lines to the sense amp in response to the read multiplexer control signal. A precharge control signal generation circuit which is connected to the column multiplexer may generate a precharge control signal on the basis of the read and write multiplexer control signals, and a bit line precharge circuit may precharge the bit lines based on the precharge control signal.

Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

Abstract: Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations.

Abstract: An operation method for a 3D NAND flash including a plurality of wordline (WL) layers. The operation method includes: writing data into a WLn layer of the plurality of WL layers according to a writing sequence from a first end of the plurality of WL layers to a second end of the plurality of WL layers in a write operation, wherein the WLn layer is a selected WL layer; and applying a first pass voltage on a first WL layer of the plurality of WL layers and applying a second pass voltage on a second WL layer of the plurality of WL layers during a verify phase; wherein the operation method is operated without a pre-pulse phase during or before the verify phase.

Abstract: In an embodiment, a method includes: receiving data representative of an electrical circuit including an arrangement of devices, inputs, outputs, and power sources; determining a minimum number of segments based on the received data; grouping the devices into N segments based on common features shared between two or more of the devices, where N is equal to the minimum number of segments; and generating discrete portions of the grouped devices to form a physical layout representative of a physical manifestation of the electrical circuit, such that when the discrete portions are integrated together they form a physical manifestation of the electrical circuit.

Abstract: A memory device that operates at high speed is provided. The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.

Abstract: Embodiments of a memory, and calibration and operation methods thereof for reading data in memory cells are disclosed. In an example, first data from a plurality of memory cells is sensed, each of the first data corresponding to a first bit. Measurements of first currents converted from voltages of the first data are obtained. Second data from the plurality of memory cells is sensed, each of the second data corresponding to a second bit which is different from the first bit. Measurements of second currents converted from voltages of the second data are obtained. One or more parameters corresponding to one or more components of a charge sharing circuit are adjusted until each of a plurality of reference currents provided by a plurality of transistors is within a predetermined range of a nominal value determined based on the measurements of first currents and the measurements of second currents.

Abstract: A content-address memory (CAM) and an operation method are provided. The content-address memory comprises: a plurality of first signal lines; a plurality of second signal lines; and a plurality of CAM memory cells coupled to the first signal lines and the second signal lines, wherein in data match, a plurality of input signals are input into the CAM memory cells via the first signal lines; the input signals are compared with contents stored in the CAM memory cells; and a match result is determined based on an electrical characteristic of the second signal lines.

Abstract: A memory device with single transistor drivers and methods to operate the memory device are described. In some embodiments, the memory device may comprise memory cells at cross points of access lines of a memory array, a first even single transistor driver configured to drive a first even access line to a discharging voltage during an IDLE phase, to drive the first even access line to a floating voltage during an ACTIVE phase, and to drive the first even access line to a read/program voltage during a PULSE phase, and a first odd single transistor driver configured to drive a first odd access line, the first odd access line physically adjacent to the first even access line, to the discharging voltage during the IDLE phase, to drive the first odd access line to the floating voltage during the ACTIVE phase, and to drive the first odd access line to a shielding voltage during the PULSE phase.

Abstract: Provided herein may be a storage device configured to check a status of a memory device based on data read without output of a status check command, and determine a subsequent command to be generated. The storage device may include a memory device and a memory controller configured to control the memory device. The memory device may include a read data generator configured to generate new read data including both read data corresponding to a read command received from the memory controller and information indicating a status of the memory device. The memory controller may include: a status information determiner configured to determine the status of the memory device based on the new read data received from the read data generator and generate status information and a command generator configured to generate a command to be output to the memory device based on the status information.

Abstract: Devices and techniques are disclosed herein to compensate for variance in one or more electrical parameters across multiple signal lines of an array of memory cells. A compensation circuit can provide a bias signal to a first one of the multiple signal lines, the bias signal having an overdrive voltage greater than a target voltage by a selected increment for a selected overdrive period.

Abstract: An apparatus includes a plurality of NAND strings in a block with word lines connected to cells of the NAND strings and select lines connected to select gate transistors of the NAND strings. A control circuit is configured to, after a read operation of memory cells of the block apply substantially zero volts to the global word lines to discharge the word lines to substantially zero volts. The control circuit is further configured to turn off the select gate transistors to isolate channels, turn off the block select transistors to isolate the word lines from the global word lines, and with the block select transistors turned off, apply a low positive voltage on the global word lines.

Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping element, and control circuit. The memory cell and clamping element can be both coupled to a digit line. The control circuit can be configured to cause the clamping element to clamp the voltage of the digit line for a period of time while the digit line driver is caused to bias the digit line at a voltage level sufficient to enable selection of the memory cell. In addition, the control circuit can be configured to cause the access line driver to bias an access line coupled to memory cell when the voltage of the digit line is at the voltage level sufficient to enable selection of the memory cell.

Abstract: A semiconductor device includes a semiconductor substrate having an upper surface region and a lower surface region. The lower surface region is recessed relative to the upper surface region so a sidewall region of the semiconductor substrate extends from the lower surface region to the upper surface region. A gate electrode overlies the upper surface region of the semiconductor substrate and is spaced laterally apart from the sidewall region. An epitaxial source/drain region is disposed in the semiconductor substrate between the gate electrode and the sidewall region. A dummy gate electrode is spaced apart from the gate electrode by the epitaxial source/drain region and is disposed over the sidewall region. The dummy gate electrode has a non-planar lower surface having a first peripheral portion extending over the upper surface region, an intermediate portion extending downward along the sidewall region, and a second peripheral portion extending over the lower surface region.

Abstract: In some embodiments, a memory device includes a memory bank, a global data line, a first tri-state unit, a latch, a second tri-state unit and a pre-charge unit. The first tri-state unit is configured between the memory bank and the global data line. The latch is configured to provide a state signal based on a data signal from the memory bank. The second tri-state unit is configured between the global data line and the latch. The pre-charge unit pre-charges the global data line to a first intermediate level or a second intermediate level depending on the state signal during the global data line is caused to be electrically isolated from the memory bank by the first tri-state unit and electrically isolated from the latch by the second tri-state unit.

Abstract: A static memory apparatus and a data reading method thereof are provided. The static memory apparatus includes a plurality of memory cells, a plurality of dummy memory cells, a sense amplifier, and a discharge current adjuster. The dummy memory cells respectively include a plurality discharge ends for discharging charges on a dummy bit line. The sense amplifier is enabled for a sensing and amplifying operation according to a signal on the dummy bit line, and the sense amplifier generates readout data accordingly. The discharge current adjuster adjusts at least one discharge current on at least one controlled discharge end according to an operating voltage of the memory cells.

Abstract: Devices which store data for a period of time. In one form, devices store data in which the data store is subject to periodic and/or relatively short power outages. In one example, a radio frequency identification (“RFID”) transponder, and more particularly, a RFID transponder that is used in orientation independent applications, is disclosed. Other applications are directed to devices used where a supply power is intermittent. In a first aspect of embodiments described herein, there is disclosed a method of and/or device that includes a memory adapted to store data, a supply of power adapted to provide supply power to the memory, a path of leakage, the leakage path serving, over time, to diminish the integrity of data stored in the memory, and a leakage attenuator adapted to selectively attenuate the rate of leakage.

Abstract: A semiconductor memory device includes a bit line sense amplification unit configured to sense/amplify data loaded on a bit line, and a driving control unit configured to supply a power line of the bit line sense amplification unit with an overdriving voltage in an overdriving period and supply an internal voltage line with a voltage of the power line of the bit line sense amplification unit in a discharge driving period.

Abstract: A semiconductor device with reduced leakage current and a method of manufacturing these reduced leakage current semiconductor devices are disclosed. The reduced leakage current semiconductor devices may be used for both static circuits and dynamic circuits. The reduced leakage current semiconductor devices reduce leakage current in the device when the node is not transitioning which occurs more than 95% of the time.

Abstract: Circuits, systems, and methods for discharging loads are provided. One circuit includes a node coupled to a voltage source, a capacitor, a source-follower device coupled between the node and the capacitor, and a current source coupled to the capacitor. The source-follower device is configured to switchably couple the capacitor to the node to discharge the voltage source and the current source is configured to discharge the capacitor. One system includes the above circuit coupled to a memory device such that the circuit is configured to discharge voltage from the memory device. A method includes discharging, via a capacitor coupled to the memory device, a high voltage from the memory device and discharging, via a current source coupled to the capacitor, the high voltage from the capacitor. The capacitor is configured to discharge the high voltage within a predetermined range of time.

Abstract: According to some embodiments, an electronic circuit comprises a digital output which is held to a logic one after the power supply was removed, for a time duration in a narrow range. The electronic circuit comprises a first array of elements comprising capacitors and discharging devices (diodes or transistors). A time constant detector detects which elements has the discharging time closest to the target. A second array of elements also comprises capacitors and discharging devices, with discharging durations proportional to the discharging durations of the first array. A decoder charges the appropriate element from the second array. After the power is removed, this charged element starts to discharge. During the discharge duration, a comparator outputs a logic one, and a logic zero after the discharge is completed.

Abstract: According to one embodiment, a memory includes a temporary storage area which temporary stores data in a read/write operation to an array. The temporary storage area comprises a clamp FET connected between a first data bus and a second data bus, a first precharge FET connected between the first data bus and first potential, a second precharge FET connected between the second data bus and the first potential, a first storage area connected to the first data bus, and a second storage area connected to the second data bus. The control circuit is configured to generate a precharge state in which the first data bus is precharged to the first potential and the second data bus is precharged to a second potential lower than the first potential, when the data is transferred from the second storage area to the first storage area.

Abstract: In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.

Abstract: A circuit includes a first plurality of memory cells coupled with a first data line and a first data transfer circuit coupled with the first data line and a second data line. In a first operation mode of the circuit, the first data line is left floating and is caused to have a first logical value by a current in at least one memory cell of the first plurality of memory cells. In a second operation mode of the circuit, the first data line is configured to reflect data stored in a memory cell of the plurality of memory cells, and the second data line is configured to reflect the data on the first data line through the first data transfer circuit.

Abstract: A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit uses one power supply level for the bit line driving path and a second supply level for a data latch of the sense amp. The latch's supply level is of a high level that used for driving the bit lines and can be provided by a charge pump. The sense amp need use only NMOS devices for its analog path. For balancing performance and current consumption, the sense amp also includes an additional latch to support a “hybrid lockout” sensing mode, where in a verify operation a read-lockout is used between different data states, but not between the low and high quick pass write (QPW) verifies.

Abstract: A digital voltage boost circuit, optionally working in parallel with an analog voltage regulator, periodically injects a constant amount of current each cycle into the bit line of a high density memory array to eliminate the bias voltage reduction which would otherwise occur. This results in a much faster recovery time and reduces the semiconductor real estate required. A pulse generator in the boost circuit generates one or more current modulation signals which control corresponding current supply devices in a current source. The boost circuit drives a constant amount of current to the bias voltage node each memory cycle.

Abstract: A semiconductor device includes a global bit line and a local bit line, and a switch coupled therebetween. Upon performing a precharge operation, a precharge voltage is supplied to the global bit line with turning the switch ON, so that the local bit line receives the precharge voltage through the global bit line and the switch, and after a lapse of a predetermined time, a precharge voltage is further supplied to the local bit line without an intervention of the global bit line and the switch.

Abstract: There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.

Abstract: A charge/discharge circuit is configured to directly charge a storage system using a power source under a power-on stage and to charge the storage system using power pre-stored in a capacitor under a power-off stage. With the aid of the charge/discharge circuit, an access speed of the storage system is prevented from being slowed down by attaching the large capacitance of the capacitor, and data accuracy of the storage system is prevented from being affected by sudden loss of power supply of the power source.

Abstract: A pre-charge controlling method and device are provided. The pre-charge controlling method includes pre-charging a first global bit line with a first pre-charge voltage by using at least a first pre-charge circuit located between a plurality of sub arrays included in a memory cell array and pre-charging the first global bit line with a second pre-charge voltage by using a second pre-charge circuit located outside the memory cell array.

Abstract: Disclosed herein is a semiconductor device comprising a global bit line, a first local bit line coupled to normal memory cells, a second local bit line coupled to redundant memory cells first and second hierarchical switches, a precharge circuit precharging the global bit line, a redundancy determination circuit determining whether or not an accessed address matches a defective address, and a control circuit. In a standby state, the global bit line and the second local bit line are precharged through the second hierarchical switch. In an active state, the first local bit line is precharged through the first hierarchical switch, subsequently when the redundancy determination circuit determines that the addresses do not match, the second hierarchical switch is inactivated to access the normal memory cells, and when the redundancy determination circuit determines that the addresses match each other, the first hierarchical switch is inactivated to access the redundant memory cells.

Abstract: A semiconductor memory apparatus comprises bit line sense amplifier unit, and a pair of precharge elements coupled in series between a first bit line and a second bit line and having an asymmetrical contact resistance ratio.

Abstract: A nonvolatile semiconductor memory quickly and precisely accumulates a desired amount of charges corresponding to data-to-be-written in a charge accumulating part of a memory cell. When charges are injected into the charge accumulating part of the memory cell by applying a writing voltage corresponding to the data-to-be-written to the drain or source region of the memory cell, the writing voltage is reduced on the basis of an increase in the amount of charges accumulated in the charge accumulating part.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.

Abstract: A non-volatile memory device can include a word line that is operatively coupled to a non-volatile memory cell. A local bit line can be operatively coupled to the non-volatile memory cell. A discharge line that is associated with the local bit line can be configured to discharge the local bit line and a discharge diode can be electrically coupled between the local bit line and the discharge line.

Abstract: Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines.

Abstract: Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump.

Abstract: A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.

Abstract: In at least one embodiment, a sense amplifier circuit includes a pair of bit lines, a sense amplifier output, a keeper circuit, and a noise threshold control circuit. The keeper circuit is coupled to the pair of bit lines and includes an NMOS transistor coupled between a power node and a corresponding one of the pair of bit lines. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the corresponding bit line and configured to maintain a voltage level of the corresponding bit line. The noise threshold control circuit is connected to the sense amplifier output and the pair of bit lines. The noise threshold control circuit comprises a half-Schmitt trigger circuit or a Schmitt trigger circuit.

Abstract: A data transmission circuit includes an enable signal generation unit configured to receive a first enable signal and generate a second enable signal having a pulse width controlled according to a swing width of data inputted through a first data line, and a sense amplification unit configured to sense and amplify the data inputted through the first data line in response to the second enable signal, and transmit the amplified data to a second data line.

Abstract: Systems, apparatus, memory devices, sense amplifiers and methods are provided, such as a system that includes an input node, a first transistor having a gate that couples to the input node, and a second transistor having another gate that couples to the input node. In one or more embodiments, the second transistor has a greater activation voltage threshold than does the first transistor and the first transistor amplifies a signal that is present on the input node. In one such embodiment, after the first transistor amplifies the signal, the second transistor maintains the amplified signal on the input node while the first transistor is deactivated.

Abstract: A semiconductor memory device includes memory cells, a sensing amplifier, a precharge circuit, and a control signal generator. The precharge circuit has a NMOS transistor and two PMOS transistors, and is used to precharge bit lines of a bit line pair, wherein the NMOS transistor is controlled by a first control signal, and the two PMOS transistors are controlled by a second control signal. The control signal generator is used to generate the first and second control signals, wherein the first control signal is at a logic high level only when the second control signal is at a first logic low level, the first control signal is at a logic low level when the second control signal is at a second logic low or a first logic high level, and the second logic low level is higher than the first logic low level.

Abstract: The disclosure relates to a device for supplying to at least one integrated circuit a high voltage for erasing and/or programming of a memory. The device includes at least one contact terminal linked to at least one contact terminal of the integrated circuit, a monitor for monitoring a data signal received by the integrated circuit and detecting in the data signal a write command of the memory, and a voltage supplier for applying the high voltage to a terminal of the integrated circuit when a write command of the memory has been detected by the monitor.

Abstract: A semiconductor memory device includes a plurality of word lines wired in a first direction, a plurality of bit lines wired in a direction crossing the first direction, a memory cell array including a plurality of DRAM cells provided corresponding to intersections between the word lines and the bit lines, a word line driver which drives the word lines, and a plurality of word line potential stabilization transistors connected to the respective word lines and disposed on an opposite side of the word line driver with the memory cell array sandwiched between the word line potential stabilization transistors and the word line driver, each word line potential stabilization transistor turning on when the word line adjacent to a relevant one of the word lines is selected, thereby connecting the relevant word line to a non-selected potential, and turning off when the relevant word line is selected.

Abstract: A non-volatile memory device and a sensing method thereof are disclosed, which can sense multi-level data using resistance variation. The non-volatile memory device includes a cell array and a sensing unit. The cell array includes a plurality of unit cells where data is read out or written. The sensing unit compares a sensing voltage corresponding to data stored in the unit cell with a reference voltage, amplifies/outputs the compared result, measures a difference in discharge time where the sensing voltage is discharged in response to a resistance value of the unit cell during an activation period of a sensing enable signal after a bit line is precharged, and senses the data in response to the measured result.

Abstract: A memory array includes: at least one differential local bit line pair; at least one differential global bit line pair; at least a column selection signal, for charging the differential local bit line pair to a predetermined voltage; at least an enable signal for coupling the differential local bit line pair to the differential global bit line pair when a voltage of the differential local bit line pair reaches a specific value; and a local sense accelerator, coupled to the differential local bit line pair, for determining a voltage of the differential local bit line pair, and enabling an accelerator signal for latching one of the differential local bit line pair and pulling the other low when the voltage reaches the specific value.

Abstract: A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial programming cycle, first and second load voltages are charged from the charge pump. The first load is removed from the charge pump during a verify operation. The first load voltage is subsequently recharged by charge sharing from the second load voltage so that the charge pump is not initially necessary for recharging the first load voltage.

Abstract: A precharge signal generation circuit of a semiconductor memory apparatus may comprise a read/write precharge command generation section configured to delay a precharge command by a first delay time set in response to a control signal to generate one of a read precharge command and a write precharge command; and a read/write bank precharge address generation section configured to delay a bank column address strobe signal by a second delay time set in response to the precharge command delayed in the read/write precharge command generation section, and generate one of a read bank precharge address and a write bank precharge address.

Abstract: A circuit includes a plurality of capacitors responsive to a plurality of latches that store a test code. A first bit line is coupled to a bit cell and coupled to a sense amplifier. A second bit line is coupled to the bit cell and coupled to the sense amplifier. A differential charge from a set of the plurality of capacitors is applied to the first bit line and to the second bit line. The set of the plurality of capacitors is determined based on the test code and the test code is independent of an output of the sense amplifier.