Abstract: A circuit for controlling a sense amplifier of a semiconductor memory apparatus including a sense amplifier control unit that controls an enable point of a sense amplifier control signal which is generated by an active command and a precharge command, according to whether a refresh signal is enabled. A sense amplifier driver that generates a sense amplifier driving signal in response to input of the sense amplifier control signal and a bit line equalization signal.

Abstract: Disclosed is a semiconductor memory device which includes a sense amplifier, arranged between a first mat and a second mat, switches for controlling the connection between first and second bit lines of each of the first and second mats on one hand and the sense amplifier on the other, and a control unit for exercising control so that, when an input test mode signal indicates a test mode, both the switch associated with the selected mat and the switch associated with the non-selected mat will be turned on.

Abstract: A semiconductor memory device includes first and second global bit lines; first, second, third and fourth local bit lines; first, second, third and fourth hierarchical switches for respectively connecting the first global bit line and the first local bit line to each other, the second global bit line and the second local bit line to each other, the first global bit line and the third local bit line to each other, and the second global bit line and the fourth local bit line to each other; and first and second precharge circuits for respectively precharging the first and second global bit lines. When a memory cell connected to the first local bit line is read, the third hierarchical switch is turned off, and the first precharge circuit terminates its precharge operation after the third hierarchical switch is turned off and before a selected word line connected to the memory cell to be read is activated.

Abstract: A current-mode sensing structure of a high-density multiple-port register in embedded flash memory procedure and a method for the same are proposed. A multiple-port register file cell is used to send out a select signal of “0” or “1”. Based on this select signal, a turn-on voltage and a cell current are output. Next, a dummy bit line of an embedded dummy flash cell is used to define a reference voltage according to the turn-on voltage and generate a corresponding reference current. Finally, the cell current and the reference current are sent to a current comparator amplifier, which senses and outputs a difference value between the cell current and the reference current to perform session at once (SAO) recording. Because the difference value has only two possibilities: the reference current or its negative, the sensing time of the current comparator amplifier can be shortened.

Abstract: A semiconductor storage device has first and second cell arrays including a plurality of memory cells to store data, a sense amplifier selectively connected with either one of the first and second cell arrays, a first precharge circuit to set a pair of bit lines in the first cell array to a predetermined voltage, a second precharge circuit to set a pair of bit lines in the second cell array to a predetermined voltage, a first switch circuit to connect the sense amplifier with the first cell array, a second switch circuit to connect the sense amplifier with the second cell array, and a switch controller to control conductive state of the first and second switch circuits. In non-selection state where the sense amplifier does not access any of the cell arrays, the switch controller controls one of the switch circuits into conducting state.

Abstract: A dynamic RAM incorporates a plurality of dynamic memory cells, each of which comprises a MOSFET having a gate set as a select terminal, one source and drain set as input/output terminals, and the other source and drain connected to storage nodes of a capacitor, a plurality of word lines respectively connected to the select terminals of the plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to the input/output terminals of the plurality of dynamic memory cells, and a sense amplifier array comprising a plurality of latch circuits which respectively amplify differences in voltage between the complementary bit line pairs placed so as to extend in directions opposite to each other from each pair of input/output terminals. Power supply lines are provided in mesh form inclusive of a portion above word drivers.

Abstract: A semiconductor memory apparatus includes a sense amplifier that receives a driving voltage through a sense amplifier power supply input terminal and detects and amplifies a difference between signals that are supplied to two input lines, a sense amplifier voltage supply unit that supplies a driving voltage and an overdriving voltage higher than the driving voltage to the sense amplifier through the sense amplifier power supply input terminal using a power supply voltage, and a driving voltage control unit that maintains a driving voltage level of the sense amplifier power supply input terminal in response to the level of the power supply voltage, after a voltage of the sense amplifier power supply input terminal is elevated to a power supply level responding to the overdriving voltage in order to perform the overdriving operation.

Abstract: A method and system for pre-charging and biasing a latch-type sense amplifier are described. According to an embodiment of the invention, the data latch portion of the latch-type sense amplifier includes two cross-coupled inverters having two output nodes, and two input nodes. The input nodes of the data-latch are connected to a pair of complementary bit-lines via bias control transistors. The bias control transistors are to pre-charge the input nodes based on the voltage levels of the bit-lines so as to bias the voltage levels at the input nodes in a direction the input nodes will seek upon activation of the sense amplifier.

Abstract: A semiconductor memory device includes a memory cell array, a decoder, and an access control unit. The decoder generates a word line voltage according to an address for a plurality of memory cells in the memory cell array. The access control unit controls access to the plurality of memory cells according to the word line voltage and additional access information separate from the address.

Abstract: The disclosure concerns a semiconductor memory device including a plurality of transistors. Each of the transistors has a first data state having a first threshold voltage and a second data state having a second threshold voltage. A sense amplifier is provided for a plurality of bit lines connected to drain diffusion regions of the transistors, one of the bit lines being connected to the sense amplifier. The first data state is a state in which impact ionization is generated near a drain junction by operating the transistor and in which excessive majority carriers produced by this impact ionization are held in the semiconductor layer. The second data state is a state in which a forward bias is applied between the semiconductor layer and the drain diffusion region to extract the excessive majority carriers from within the semiconductor layer to the drain diffusion region.

Abstract: A semiconductor memory device includes a plurality of memory mats each including a memory cell storing data, a sense latch portion performing detection of data stored by the memory cell, and a buffer circuit externally outputting read data detected by the sense latch portion. The sense latch portion and the buffer circuit are shared between a plurality of memory mats and are arranged between a plurality of memory mats.

Abstract: An apparatus includes a plurality of first driving signal driving units, and generates a first driving signal by driving an input signal, a plurality of second driving signal driving units, each of which drives an input signal and generates a second driving signal, a timing control unit that controls each of the first driving signal driving units such that a predetermined time difference is generated between an enable timing of the first driving signal and an enable timing of the second driving signal, a plurality of sense amplifier driving units, each of which generates a first driving level and a second driving level according to the first driving signal and the second driving signal, and a plurality of sense amplifiers that are provided for respective bit line pairs, and each include first type switching elements operating according to the first driving level and second type switching elements operating according to the second driving level.

Abstract: A variable resistance memory sense amplifier has a built-in offset to assist in switching the sense amplifier when a resistive memory cell is in a low resistance state. The built-in offset can be achieved by varying size, threshold voltage, associated capacity or associated resistance of the transistors within the sense amplifier.

Abstract: A memory device includes a first sensing amplifier to amplify data received from the memory array, a first driver to generate a first tri-state signal responsive to the amplified data from an first sense amplifier and to provide the first tri-state signal to a data bus line, a second sensing amplifier to amplify data received from the memory array, and a second driver to generate a second tri-state signal responsive to the amplified data from an second sense amplifier and to provide the second tri-state signal to the data bus line, where the first sensing amplifier and the first driver are located in different regions of the device, and the second sensing amplifier and the second driver are located in a common region of the device.

Abstract: A circuit for enabling a sense amplifier in a semiconductor memory device includes a delay unit for outputting the delayed sense amplifier enable signal as a sense amplifier enable delay signal after delaying a sense amplifier enable signal in response to a delay control signal; and a delay control unit for controlling an intensity of the delay control signal by receiving a reference signal having a temperature reduction dependent characteristic. The length of the sensing time can increase by adjusting the delay at the sense amplifier enable signal according to a temperature decrease when a memory cell is formed on a silicon on insulator, and the sense amplifier enabling circuit is formed on a bulk silicon layer. In addition, the enable time point in the sense amplifier can be smoothly adjusted, and the possibility of operation failure in the semiconductor memory device can be reduced by reducing the occurrence of the sensing failure at the sense amplifier.

Abstract: Disclosed is a semiconductor memory device includes two equalizing elements, each connected between a pair of bit lines and being separately subjected to on/off control by respective control signals. When performing a test, one of the control signals is kept HIGH and the other of the control signal is kept LOW during a precharge period, and activation/deactivation of the two equalizing elements is separately controlled. A failure such as a defect in one of the two equalizing elements subjected to the on/off control by the control signal can be thereby detected.

Abstract: A sense amplifier includes: NMOS transistors, drains thereof being coupled to output nodes, gates thereof being coupled to the output nodes, sources thereof being coupled in common to the ground potential node; PMOS transistors, drains thereof being coupled to the drains of the NMOS transistors, sources thereof being coupled to the input nodes; PMOS transistors, drains thereof being coupled to the input nodes, gates thereof being coupled to the output nodes, sources thereof being coupled to the power supply node via a current source device; and NMOS transistors disposed between the output nodes and the ground potential node to be turned on before sensing; and an equalizing transistor disposed between the output nodes.

Abstract: An amplifier circuit includes an amplifier section (700), an equalization section (770), and an activation section (720). The P-channel transistors (702, 704) of the amplifier section are coupled to a supply terminal (802). The N-channel transistors (706, 708) of the amplifier section are coupled between the P-channel transistors and the first and second input terminals (760, 762), respectively. In the activation section, first and second pull down transistors (722, 724) are coupled between the first and second input terminals, respectively, and a second power supply terminal (726), and third pull down transistor between the first and second input terminals. The control gates of the first, second and third pull down transistors are coupled to each other. In operation, a voltage signal applied to the first and second input terminals is amplified by the N-channel transistors. A control signal is then applied to couple the first and second input terminals to a supply voltage.

Abstract: A sense amplifier comprises a transistor configured to be switched with a column select line to pass a bit line equalization voltage, an array equalize device coupled to the transistor for receiving the bit line equalization voltage, a sense amplifier equalize device, a multiplexer coupled between the sense amplifier equalize device and the array equalize device, and a cross-coupled amplifier latch coupled to the sense amplifier equalize device.

Abstract: A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pulldown circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

Abstract: An apparatus included in a semiconductor memory device for precharging a bit line and a bit line bar and sensing and amplifying a data delivered to one of the bit line and the bit line bar includes a precharge means for precharging the bit line and the bit line bar as a ground; a sense amplifying means for sensing and amplifying the data by using a low voltage having a lower voltage level than the ground and a high voltage having a higher voltage level than a supply voltage; and an auxiliary sense amplifying means coupled to the bit line and the bit line bar for controlling each voltage level of the bit line and the bit line bar.

Abstract: A memory device includes a pair of complementary bitlines including a first bitline and a second bitline. A bitline precharge block is coupled between the first bitline and the second bitline. A sense amplifier is coupled to both the first bitline and the second bitline and a sense amplifier precharge block is coupled to the sense amplifier. The sense amplifier precharge block can be activated independently from the bitline precharge block. An isolation block is coupled between the pair of complementary bitlines and the bitline precharge block on one side and the sense amplifier and sense amplifier precharge block on another side.

Abstract: A method and circuitry for boosting a driven signal along a circuit line so as to reduce RC delays is disclosed. In one embodiment, the circuitry includes a line amplifier positioned at a distance from the circuitry that drives signals onto the line, for example, across a memory array. The line amplifier detects the driven signal on the line at early stages, and even before the signal reaches its full potential, the amplifier amplifies that signal and drives it back to the line to help boost the detected signal. In a preferred embodiment, the amplifier comprises a differential amplifier capable of boosting one of two input signal lines. In an alternative embodiment, the amplifier output may additionally input to a feedback loop, which loop ultimately drives a pull-up transistor to boost the detected signal and passes it back to the line to even further assist the differential amplifier in boosting.

Abstract: A cell arrangement comprising a memory cell arranged in parallel to a first capacitor is charged to a first voltage potential. A second capacitor is charged to a second voltage potential, which is higher than the first voltage potential. The second capacitor is connected to the cell arrangement while the voltage over the cell arrangement comprising the first capacitor is kept constant. The resulting current from the second capacitor through the memory cell is used to detect the state of the memory cell.

Abstract: An MRAM memory chip includes a plurality of magnetoresistive memory cells each including a magnetic tunnel junction having first (fixed) and second (free) magnetic regions, where the second magnetic region includes at least two ferromagnetic layers that are antiferromagnetically coupled, wherein a coil surrounds the memory chip for creating a magnetic offset field. Further, a method of writing to an MRAM chip includes bringing the memory cells into an active state exhibiting a reduced switching field before writing thereto and bringing the memory cells into a passive state exhibiting enlarged switching field after writing thereto.

Abstract: A system and method for sensing a current. The system includes an operational amplifier including a first input terminal, a second input terminal, and a first output terminal. The first input terminal is biased to a predetermined voltage, and the second input terminal and the first output terminal are directly connected. Additionally, the system includes a switch coupled to the first output terminal and a first node. The switch is controlled by at least a first control signal. Moreover, the system includes a comparator including a third input terminal, a fourth input terminal, and at least a second output terminal. The comparator is configured to receive a first input signal at the third input terminal and a second input signal at the fourth input terminal. The first input signal and the second input signal are associated with the first node and the predetermined voltage.

Abstract: The memory device has a plurality of memory cells each coupled to a bitline. A feedback transistor is coupled to the bitline and provides voltage feedback on the bitline's precharge status. A biasing transistor is coupled to the feedback transistor. The biasing transistor provides a bias voltage to the feedback transistor in response to a reference voltage on the biasing transistor. A cascode-connected transistor is coupled to the feedback transistor and the biasing transistor. This transistor provides a stable bias voltage to the biasing transistor. An output latch circuit is coupled to the bitline for providing a latched output of the memory cell's data.

Abstract: A CMOS static random access memory (SRAM) and a bit select for the SRAM. The bit select includes a dual single-ended sense receiving a difference signal on a bit line pair and selectively sensing signals developing on each bit line independently of the other. Single ended outputs from the dual-ended sense are provided to an output driver. The output driver provides a pair of selectively-complementary output signals.

Abstract: A reduced gate delay multiplexed interface and output buffer circuit for random access memory arrays, such as synchronous dynamic random access memory (“SDRAM”) devices, or other integrated circuit devices incorporating embedded memory arrays which reduces data access time and clock latency. In accordance with the present invention, data is multiplexed (or selected) and driven out at the memory bank level rather than at the output pad area (or the embedded RAM macro edge) as in prior art techniques.

Abstract: Digital data apparatuses and digital data operational methods are described.

Abstract: An SRAM device comprising a column having opposing bit lines, asymmetric memory cells spanning the opposing bit lines in alternating orientations, and a sense amplifier. The sense amplifier includes sensing circuitry configured to sense values stored in the cells and switching circuitry configured to apply signals to the sensing circuitry as a function of the orientations.

Abstract: A signal transmission system is constructed to transmit data over a signal transmission line without requiring precharging the signal transmission line for every bit, by eliminating the intersymbol interference component introduced by preceding data. The signal transmission line has a plurality of switchable signal transmission lines organized in a branching structure or a hierarchical structure, at least one target unit from which to read data is connected to each of the plurality of signal transmission lines, and a readout circuit including a circuit for eliminating the intersymbol interference component is connected to the signal transmission line, wherein the intersymbol interference component elimination circuit reduces noise introduced when the signal transmission line is switched between the plurality of signal transmission lines, and thereby provides a smooth intersymbol interference component elimination operation when the signal transmission line is switched.

Abstract: A sense amplifier is provided that includes a measure branch receiving an input current to be detected, a reference branch receiving a reference current, and an equalizing circuit including a comparator. The equalizing circuit selectively equalizes a measure node of the measure branch with a reference node of the reference branch, and the comparator compares a voltage at the measure node of the measure branch with a voltage at the reference node of the reference branch. The equalizing circuit is such that, when activated, equalization of the measure node with the reference node is virtual and substantially does not involve a flow of current between the measure node and the reference node of the reference branch. The sense amplifier is particularly suited for reading memory cells of a semiconductor memory. Also provided is a method for sensing an input current.

Abstract: In one embodiment of the invention an integrated circuit is provided including a sense amplifier to read data from a memory cell that has a first transfer gate, a second transfer gate, a comparator, and a control circuit. The first transfer gate has a first pole coupled to a positive power supply. The second transfer gate has a first pole coupled to a bitline of the memory cell. The comparator has a first input coupled to a second pole of the first transfer gate, a second input coupled to a second pole of the second transfer gate, and an output coupled to the second input. The comparator compares signals on the first and second inputs and selectively generates a greater differential signal there-between. The control circuit turns off the comparator responsive to a logical zero being read from the memory cell avoiding the generation of the greater differential signal.

Abstract: An integrated circuit is provided which includes a sensing circuit. In the sensing circuit, a pair of conductors including a first conductor and a second conductor are adapted to conduct a first differential signal having a small voltage difference and a second differential signal having a rail-to-rail voltage difference. A sense amplifier is coupled to the pair of conductors, the sense amplifier being operable to amplify the first differential signal into the second differential signal. The sensing circuit further includes a multiple conduction state field effect transistor or “multi-state FET” which has a source, a drain, and a gate operable to control conduction between the source and the drain.

Abstract: A bit-line sense amplifier is disclosed that includes switching elements to sequentially modify the sense amplifier to a negative feedback differential amplifier, a normal differential amplifier, a positive feedback differential amplifier, and a cross-coupled latch, in that order. The sense amplifier sensing data on a pair of bit-lines in a semiconductor memory; and a transistor is connected between one of the differential amplifiers and a common current source. The transistor has a resistance which is variable depending on a potential of an output of one of the differential amplifiers or remains constant by a different power source.

Abstract: Provided is a circuit for use in a semiconductor memory optimized to improve data read ability at low supply voltages. Circuit includes a direct sense AMP circuit, an input/output gate circuit, and an operation control unit. The direct sense AMP circuit transmits read data loaded in a bit line pair including first and second bit lines to a data input/output pair including first and second data input/output lines in response to a read command signal. The input/output gate circuit which, in response to a read/write signal, also passes the read data loaded in the bit line pair directly to the data input/output line pair, and passes write data loaded in the data input/output line pair directly to the bit line pair.

Abstract: Disclosed are a connecting method of a sense amplifier and a semiconductor memory device using the same. The semiconductor memory device comprises a memory cell array including a plurality of word lines connected respectively to a plurality of memory cell blocks, each of which is composed of a plurality of memory cells, in a row direction of the memory cells, and a plurality of pairs of bit lines connected respectively to the plurality of memory cell blocks in a column direction of the memory cells; and a plurality of sense amplifier arrays, each of which includes a plurality of sense amplifiers, each of which is connected to bit lines and complementary bit lines of the plurality of pairs of bit lines, for sensing a potential difference between the bit lines and the complementary bit lines.

Abstract: In a memory circuit, a transistor formed in the same process as that of a logic transistor is used for peripheral circuitry except for a region to be supplied with high voltage. Thus, the manufacturing process can be simplified and a logic-merged memory operating at a high speed is provided.

Abstract: A semiconductor memory device having a data read path maintains a higher power voltage supplied to an input/output sense amplifier in the input/output path, through which data passes during a data read operation, than the voltage supplied to other circuit components in the data read path, thereby achieving a high data read speed.

Abstract: Local bit line pairs in a domino SRAM include an amplifier to amplify the voltage differential across the bit lines during a read operation if a cell in the local group of cells has been identified as a slow to read cell. The amplifier includes a transistor switch that is turned on by a timing pulse during the read operation, but only if the Array Built In Self-Test (ABIST) has detected a slow to read cell in the local group. If there is no slow cell, the amplifier is not activated, and the domino read operation is carried out. The amplifier can be used globally across the SRAM or selectively in certain sub-arrays.

Abstract: A differential current evaluation circuit has a differential amplifier and a circuit for setting an input resistance of the current evaluation circuit. The circuit is connected to the outputs and the inputs of the differential amplifier and to signal lines. A sense amplifier circuit has a circuit section, in which a signal is available at an output in a temporally continuous manner even if, after the deactivation of the circuit connected upstream, a signal, in particular a signal supplied by the current evaluation circuit, is no longer present at its input. The differential current evaluation circuit and the sense amplifier circuit are disposed in a circuit configuration for reading out and evaluating a memory state of a semiconductor memory cell. The current evaluation circuit can be activated by a circuit section for automatic deactivation before a read operation and be automatically deactivated directly after the read operation has ended.

Abstract: A hierarchical memory structure having memory cells, and sense amplifiers and decoders coupled with the memory cells to form first tier memory module, and subsequent tiers being formed by having (n?1)-tier memory modules, which are coupled with (n)-tier sense amplifiers and (n)-tier decoders. Also provided are a single-ended sense amplifier having sample-and-hold reference, and a charge-share limited-swing-driver sense amplifier; an asynchronously-resettable decoder; a wordline decoder having row redundancy; a redundancy device having redundant memory cells operated by a redundancy controller; a diffusion replica delay circuit; a high-precision delay measurement circuit; and a data transfer bus circuit imposing a limited voltage swing on a data bus. Methods are provided for a write-after-read operation without an interposed precharge cycle, and write-after-write operation with an interposed precharge cycle are provided, either operation being completed in less than one memory access cycle.

Abstract: A wafer level burn-in method for static-random access memory. The SRAM memory has a plurality of word lines and a plurality of bit lines. The SRAM memory also has pull up circuits and equalizer circuits connected to various bit lines. All the word lines are switched on for testing any leakage in the gate dielectric layer. A high potential is applied to a bit line of every bit line pairs and a low potential is applied to the other bit line of the bit line pairs. The pull-up circuits and the equalizer circuits are shut down. The current at a steady state is used to judge the normality of an SRAM chip.

Abstract: A parallel sense amplifier includes a measuring branch for receiving an input current to be measured, a plurality of reference branches each one for receiving a reference current, and a plurality of comparators each one for comparing a voltage at a measuring node along the measuring branch with a voltage at a reference node along a corresponding reference branch; the amplifier further includes a multiple current mirror for mirroring the input current into each reference branch.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: Systems and methods to provide sense amplifiers for various applications. For example, in accordance with an embodiment of the present invention, a sense amplifier is disclosed having an associated precharge circuit and a read completion detection circuit.

Abstract: The present invention relates to a sense amplifier select circuit for use in a memory device consisting of cell arrays and sense amplifier arrays arranged in a shared sense amplifier mode. The sense amplifier select circuit includes a first controller for outputting a sense amplifier select signal in response to a block select signal and an operation control signal of a sense amplifier, and a second controller connected to the first controller to control the sense amplifier select signal, wherein the second controller applies an enable/disable signal when selection of a cell array is changed and keeps the enable/disable state when a sense amplifier to be sensed within a selected cell array is changed. As such, a corresponding cell array is continuously connected/disconnected to/from a bit line sense amplifier. As a result, it is possible to significantly reduce consumption of current occurring due to toggle of a sense amplifier select signal.

Abstract: A digital memory system (30) includes a memory cell (52), a bit line (50), a transfer gate (60) a reference voltage generator (40), a sense amplifier (70) and a control circuit (80). The control circuit precharges the bit line to a bit line precharge voltage, which is sampled and stored. A corresponding reference voltage is generated after the bit line is isolated. The bit line and reference voltage are coupled to the sense amplifier so that a voltage is received based on charge stored in the memory cell. The sense amplifier then is isolated from the bit line and reference voltage and the sense amplifier is energized so that an output voltage is derived from the charge and reference voltage.

Abstract: In a normal operation, an output of a differential amplifier for amplifying a difference between first and second bit cells is output as readout data. In a test mode, when a first control signal is set to be “H”, the output of the differential amplifier is fixed to be “H” and thus an output of the first bit cell is read out through gates.