Abstract: To fully evaluate a real signal line and a real memory cell adjacent to a dummy signal line and utilize dummy signal line as real signal line, a semiconductor memory includes at least one real signal line connected to real memory cells driven by a real driver and at least one dummy signal line outside the real signal line connected to dummy memory cells, driven by a dummy driver. Real driver and dummy driver drive the real signal line and the dummy signal line synchronous with a common timing signal generated by an operation control circuit. Consequently, a stress evaluation is also performable, e.g., on a real signal line outside of a memory cell array under the same condition of a real signal line on the inner side. Dummy signal line is driven using common timing signal and evaluated, thus being usable as a redundancy signal line to relieve failure.

Abstract: In a semiconductor memory device, a method for obtaining at least one reference cell adapted to be exploited as a generator of a reference signal, the reference signal depending on a value of an electrical characteristic of the at least one reference cell. The method includes providing a population of auxiliary cells, operating on said population of auxiliary cells for varying a value of the electrical characteristic thereof, in such a way that the varied values are statistically distributed in a range including a value of the electrical characteristic corresponding to the reference signal, and choosing the at least one reference cell, wherein choosing includes choosing at least one auxiliary cell in the population of auxiliary cells having the value of the electrical characteristic close to the value corresponding to the reference signal with a pre-defined tolerance.

Abstract: An embodiment of the invention relate to a memory device including a memory plane composed of memory cells located at the intersection of lines and columns, and a dummy path designed to output a signal to activate read amplifiers arranged at the bottom of the columns in the memory plane, said dummy path including dummy memory cells connected between two dummy bit lines means of selecting at least one dummy cell designed to discharge at least one of the dummy bit lines, and control means connected to the two dummy bit lines to generate said activation signal, characterized in that said device includes means of programming the number of selected cells to discharge at least said dummy bit line, to adjust the time at which said activation signal is output.

Abstract: A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element.

Abstract: A memory system is disclosed. In one embodiment, the memory system includes a first bitline, where the first bitline produces a first transient current. The memory system also includes a sense amplifier coupled to the first bitline. The memory system also includes a second bitline coupled to the sense amplifier, where the second bitline produces a second transient current that is equal to the first transient current. The sense amplifier enables the first and second transient currents to be canceled. According to the system disclosed herein, the state of a memory cell may be determined without being adversely affected by transient currents.

Abstract: A reference cell layout includes a plurality of active areas, in parallel to each other, and a first contact of the active areas, and a first gate, the first contact shorting the active areas. A memory device includes the reference cell layout and a corresponding array of memory cells having active areas sized substantially identical to the active areas of the reference cell layout and plural second contacts respectively contacting the active areas of the memory cells.

Abstract: A controlling method of a memory cell fuse circuit is provided. The memory cell fuse circuit at least includes a reference cell fuse circuit and a plurality of normal cell fuse circuit. The reference cell fuse circuit includes a reference fuse cell and each the normal cell fuse circuit includes a normal fuse cell. The controlling method includes steps of: power on read and sensing digits of the memory cell fuse circuit; detecting if any normal fuse cell is non blank as failed; programming the reference fuse cell if at least one normal fuse cell is failed until all normal fuse cells are blank; programming and reading the normal fuse cell of each the normal cell fuse circuit; and outputting data of each the normal fuse cell.

Abstract: A static random access memory (SRAM) macro includes: a cell array having one or more SRAM cells addressed by a plurality of bit lines and word lines; one or more reference cells coupled to at least one reference bit line and the word lines addressing the SRAM cells; and at least one sense amplifier having a first terminal receiving a sensing current generated by an SRAM cell selected from the cell array and a second terminal receiving a reference current generated by the reference cell controlled by the same word line coupled to the selected SRAM cell for comparing the sensing current to the reference current to generate an output signal representing a logic state of the selected SRAM cell.

Abstract: A memory comprises a bitline, an accessible memory element, an activable switch coupled between the bitline and the access node and a controller configured to activate the activable switch within a first activation period, to activate the activable switch within a second activation period and to deactivate the activable switch at least once when accessing to the accessible memory element during the same access operation.

Abstract: A multi-level semiconductor memory device for storing multi-level data having three or more values is implemented by utilizing a nonvolatile memory device for storing 2-valued data. Identification of successive 16-bit data externally applied is performed with external address bit AA [2], and a storage block is selected with external address bit AA [23]. Upper word data LW and lower word data UW are compressed into byte data of 8 bits, respectively, and stored in a memory cell array.

Abstract: A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.

Abstract: A storage device includes: a ferroelectric memory that temporarily stores data, wherein the ferroelectric memory stores an error correction code that is used for verifying the data by correcting errors possibly occurring on the data stored; a storage medium that has a plurality of storage regions and continually stores the data in one of the plurality of storage regions; and a control section that (1) writes the data and the error correction code to the ferroelectric memory, (2) writes the data written in the ferroelectric memory to one of the storage regions in the storage medium, (3) compares the data that is written in the ferroelectric memory and has been verified by using the error correction code written in the ferroelectric memory with the data written to the one of the storage regions in the storage medium, and (4) rewrites the data that has been verified to another one of the storage regions in the storage medium when both of the data do not match each other.

Abstract: A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit.

Abstract: A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.