Abstract: A device includes a first internal voltage generation circuit generating a first internal voltage in response to an external power supply voltage, a second internal voltage generation circuit generating a second internal voltage in response to the external power supply voltage, the second internal voltage being different in voltage level from the first internal voltage, and a preset signal generation circuit responding to a power-on of the external power supply voltage to the device and generating, independently of the first internal voltage, first and second preset signals that bring the first and the second internal voltage generation circuits into respective initial states, the preset signal generating circuit stopping generation of the first preset signal when the external power supply voltage reaches a first voltage level and stopping generation of the second preset signal when the external power supply voltage reaches a second voltage level different from the first voltage level.

Abstract: The memory system includes a semiconductor memory that has an internal circuit, which operates according to a first power supply voltage, and a memory input/output circuit coupled to the internal circuit and operates according to a second power supply voltage, a first control unit that includes a control input/output circuit, coupled to the memory input/output circuit and operates according to the second power supply voltage, a voltage generating unit that generates the second power supply voltage and changes the second power supply voltage according to a voltage adjustment signal, a clock generating unit that generates the clock signal and changes the frequency of the clock signal according to a clock adjustment signal, and a second control unit that generates the voltage adjustment signal and the clock adjustment signal according to an access state of the semiconductor memory by the first control unit.

Abstract: A switched current memory cell includes a current source 100 having one end connected to an operation power source (Vdd) stage, a current memory circuit unit 200 that stores an input current; which is inputted in a sampling mode of the current from the current source 100, during a hold mode, maintains the current value stored in the hold mode, and outputs the stored current in an output mode, an input switch SW10 that is turned on in the sampling mode to transfer an input current to the current memory circuit unit 200, and turned off in the hold mode, an output switch SW20 that is turned on in the output mode to output current from the current memory circuit unit 200, and a current cut circuit unit 300 that connects a current path between the operation power source Vdd stage and the current source 100 in the input mode and output mode, and separates the current path between the operation power source Vdd stage and the current source 100 in the hold mode.