Abstract: A device for protecting data stored in a static random access memory (SRAM) is provided. More particularly, a device for protecting SRAM data including an SRAM data erasing circuit, which erases memory stored in an SRAM at once when illegal separation from a system is detected. The device for protecting SRAM data includes: a power switching circuit for outputting electrical power supplied from an external power supply or a back-up battery power supply depending on whether the external power supply is supplying the electrical power or not; and an SRAM data erasing circuit for supplying the electrical power output from the power switching circuit to a power input terminal of a SRAM or grounding the power input terminal of the SRAM, in response to a connecter connection signal. The device can prevent illegal leakage of SRAM data by erasing the data stored in the SRAM when the SRAM is illegally separated from a system according to the switch setting of the SRAM data erasing circuit.

Abstract: A semiconductor device includes a fuse part including an antifuse that is connected between a first common node to which a high voltage that is higher than an internal boost voltage is applied and a first node. The fuse part is enabled in response to a program mode selection signal and an address signal so as to fuse the antifuse in response to the high voltage applied to the first common node and to set a voltage level of a second node. A latch circuit is configured to latch an output signal responsive to the voltage level of the second node when the fuse part is in a fused state. A protection circuit is configured to lower a voltage level at the first node when the fuse part is not enabled and the high voltage is applied to the first common node.

Abstract: A flash memory module includes an integral indicator light. The module alternatively includes a plurality electrical contacts which electrically interface to a host digital device. The module includes a plurality of flash memory cells. The cells are controlled by an integral controller. The indicator light is controlled by the controller. The indicator light indicates whether the flash memory module is being accessed. Alternatively, the indicator light indicates that the flash memory module should be replaced. A housing for the module is preferably light transmissive material, and preferably a transparent plastic. A proximal end of the module includes the electrical contacts and is inserted into the host. The indicator light is preferably a surface mount LED and is positioned adjacent the distal end of the flash memory module to be seen through the transparent plastic. Alternatively, the controller generates an electronic signal which is coupled to the host.

Abstract: A method of operating a non-volatile data storage device includes determining the type of the previous power off event when the non-volatile data storage device is rebooted; and selecting and performing a reboot sequence based upon the determined type of the power off event. Determining the type of the previous power off event may be performed by analyzing one or more metadata groups stored in the non-volatile data storage device. During normal operation of the data storage device a preamble (indicating that an operation of a data storage device started) and a postamble (indicating that an operation of the data storage device ended) are written in each group of metadata. If the power off event is a sudden (abnormal) power off event during a write operation, the postamble is not written, and its absence indicates that the power off event was a sudden (abnormal) power off event.

Abstract: A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as delay lock loops during row activations and read/write memory operations. A switch connects the array power bus to another separate power bus for a limited period of time during a DRAM refresh cycle to provide additional current to the DRAM arrays. The switch disconnects the array power bus from the other power bus preferably before the end of the refresh cycle.

Abstract: In a semiconductor memory device the power level of which is strengthened by using data input/output pads in a no connection state, and a method of strengthening the power of the semiconductor memory device at a stabilized power level, the semiconductor memory device comprises: a plurality of data input/output drivers; and a plurality of data input/output pads, each connected to a corresponding one of the plurality of data input/output drivers. A first subset of the data input/output pads are connected to respective data input/output pins of a package, and several or all of a remaining subset of the data input/output pads that are not connected to data input/output pins of the package are connected to power pins of the package.

Abstract: A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode.

Abstract: Control circuits for a voltage regulator of a semiconductor memory device include an option fuse circuit and a fusing control circuit. The option fuse circuit includes a plurality of fuses and a selection circuit that selects one of the plurality of fuses responsive to a control signal. An output voltage associated with the voltage reset circuit is adjusted responsive to a state of the selected one of the plurality of fuses. A fusing control circuit generates the control signal to allow multiple adjustments of the output voltage by the voltage reset circuit. The option fuse circuit may be a plurality of option fuse circuits and the output voltage may be adjusted responsive to the states of the respective selected ones of the plurality of fuses of the option fuse circuits.

Abstract: A projector 100 includes an image projection unit 6 that projects an image using light from a discharge lamp 1, a ballast 2 that controls a supply voltage supplied to the discharge lamp 1, a system controller 3 that controls a command signal outputted to the ballast 2, a volatile memory 31, a nonvolatile memory 32 that stores data stored in the volatile memory 31, and a power supply unit 4 that includes a capacitor 48 used for generating a supply voltage supplied from an external power supply to the ballast 2. The system controller 3 stores the data of the volatile memory 31 in the nonvolatile memory 32 using a voltage generated by accumulated charges of the capacitor 48 when the external power supply is cut off.

Abstract: A temperature sensor instruction signal generator, which may drive a temperature sensor, and a semiconductor memory device including the same. The temperature sensor instruction signal generator may generate an instruction signal that instruct the operation of the temperature sensor using at least one of a master clock (CLK) signal, a clock enable (CKE) signal, a row address selection (RAS) signal, a column address selection (CAS) signal, a write enable (WE) signal, and a chip selection (CS) signal, wherein the instruction signal may be enabled corresponding to at least one of a self refresh mode, an auto refresh mode, and a long tRAS mode. The semiconductor memory device may include a temperature sensor and the temperature sensor instruction signal generator.

Abstract: A delay selection circuit for use in a semiconductor memory device prevents a tAA from increasing at a read operation due to a delayed command type of signal. The delay selection circuit includes a delay line unit, a power supply voltage detection unit and a path selection unit. The delay line unit has two delay lines for delaying a command type of signal by different delay amounts. The power supply voltage detection unit detects a voltage level of a power supply voltage. The path selection unit selects one of each output of the two delay lines according to an output of the power supply voltage detection unit.

Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

Abstract: A device is provided including a memory cell, a first supply voltage generator, passively coupled to the memory cell, to provide the memory cell with a first supply voltage, and a second supply voltage generator, coupled to the memory cell, to provide the memory cell with a second supply voltage.

Abstract: A backup volatile state retention circuit is provided with low leakage current for employment with a volatile memory circuit to store the value of the latter during power down of the volatile circuit or during power-down or inactivation of neighboring or peripheral circuits or due to the loss of power of any of these circuits. An example of such a volatile circuit is a memory circuit having volatile memory cells such as employed in dynamic memory core, in particular, a random access memory (RAM) in CMOS circuitry.

Abstract: A semiconductor memory includes a plurality of memory cells, each of which includes a first inverter connected to one of high-data retaining supply lines which constitute one of high-data retaining supply line pairs corresponding to the memory cell and a second inverter connected to the other one of the high-data retaining supply lines which constitute the corresponding high-data retaining supply line pair, an input and output of the second inverter being connected to an output and input of the first inverter, respectively. A selected high-data retaining supply circuit receives a signal determined according to an input data signal and address signal without the intervention of any of the bit lines which constitute the bit line pairs to drive the connected high-data retaining supply lines such that it has a potential corresponding to the received signal.

Abstract: A method, apparatus and system are disclosed for sensing and reporting voltage levels in a semiconductor device. One such voltage sensor and reporting device is configured to sense and compare a reference voltage and an operating voltage. In one or more embodiments we voltage sensor is also configured to generate an alarm signal if the difference between the operating voltage and the reference voltage indicates the operating voltage is outside of a normal operating range.

Abstract: In an embedded system with a processor and an EEPROM that provides an EEPROM BUSY signal if the EEPROM is in a write mode, a block-before-write subroutine is used to hold the processor before a write operation to the EEPROM. A detector circuit finds read functions that are to be mapped into the EEPROM address space and suspends code execution if an EEPROM BUSY bit is asserted and the EEPROM is the read target. Code execution by the processor and processor access to memories other than the EEPROM is permitted while the EEPROM is being written. If any access is made by the processor to the EEPROM while the EEPROM BUSY bit is asserted, the processor enters a WAIT state to temporarily suspends execution of program code.

Abstract: To make it possible to reliably halt writing processing while restraining erroneous writing to the memory unit, present apparatus has a memory unit to which data is written for each write request; a voltage converting unit which converts a first power source voltage into a first operable voltage with which a write request issuing unit is operable, and supplies the first operable voltage to the write request issuing unit; a voltage monitoring unit, which outputs an issuance restraining signal which restrains issuance of the write request, when the first power source voltage becomes lower than a reference voltage; and an issuance restrain controlling unit which receives the issuance restrain signal, and then after completion of writing for each of the write request to write memory unit, which restrains the issuance of the write request by the write request issuance unit.

Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

Abstract: A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit a relatively slow refresh rate. When transitioning from the full density mode to the half density mode, data are copied from each row of memory cells storing data to an adjacent row of memory cells. The adjacent row of memory cells are made free to store data from an adjacent row by remapping the most significant bit of the row address to the least significant bit of the row address, and then remapping all of the remaining bits of the row address to the next highest order bit.

Abstract: Rank numbers specified by a second counter are refreshed in sequence by using a count value of a first counter which is initialized by a synchronous reset signal and counts timing for performing refresh, and the rank numbers specified by a refresh rank control unit are continuously refreshed in sequence in the case where the synchronous reset signal is active.

Abstract: According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M scan flip flops are able to save/restore the M bits of state data. Each group contains a merged scan flip flop coupled to a series of scan flip flops. The merged scan flip flop in each of the groups is coupled to a respective read port of a memory unit, and a final scan flip flop in each of the groups is coupled to a respective write port of the memory unit. The system enables the memory unit to save the M bits of state data in N clock cycles. Each merged scan flip flop has a read select input that enables restoring of the state data into the M scan flip flops in N clock cycles.

Abstract: A lock-out device is provided that determines whether to lock out a chip or not according to the result of operation voltage drop detected at a plurality of positions in a semiconductor integrated circuit device. As a result, unnecessary lock-out operations can be prevented and a program operation or an erase operation in a semiconductor memory device can be executed stably.

Abstract: The temperature for multiple devices of a memory module are determined. In one example a memory module includes a printed circuit board, a plurality of memory chips on the printed circuit board, each chip containing a plurality of memory cells and a thermal sensor, and a multiplexer on the printed circuit board, independent of the memory chips, coupled to each of the thermal sensors. A current source is coupled to the multiplexer to provide a current to each one of the thermal sensors, and a voltage detector is coupled to the multiplexer to detect a voltage from each of the thermal sensors when a current is applied. A temperature circuit is coupled to the voltage detector to determine a temperature for each memory chip based on the detected voltage.

Abstract: The present disclosure includes various method, device, and system embodiments for multilevel driving of rowlines and/or wordlines. One such method embodiment includes supplying a first power voltage (V1) and a second power voltage (V2) that is greater than V1, to the driver circuit. The method includes supplying a first boost voltage (V3), V3 being greater than V2, and a reference voltage (Vref) that is less than V1, to the driver circuit. The method includes coupling a level shifter to the driver circuit, the level shifter including a number of input signals configured to control a drive output of the driver circuit in order to switch the drive output successively from a voltage at or below Vref to at least one of V1, V2, and Vref prior to switching the driving output to V3.

Abstract: Provided is a high voltage generator for a flash memory device including a voltage pumping unit configured to generate a high voltage in response to a pumping clock signal, a transistor having a gate coupled to the high voltage and a source coupled to a program voltage, a voltage distributor coupled to the drain of the transistor, the voltage distributor configured to generate a distributor voltage, and a pumping clock controller configured to compare the distributor voltage to a reference voltage and to generate the pumping clock signal when the high voltage is less than a voltage substantially equal to the program voltage plus the threshold voltage of the transistor.

Abstract: A semiconductor memory device comprises a plurality of memory cells connected to a plurality of word lines grouped in word line sets. Each of the word line sets is connected to a word line enable signal generation unit which stores information indicating whether data has been written to any of the memory cells connected to the word line set. The word line enable signal generation unit controls refresh operations for memory cells connected to the word line set so that only word lines connected to memory cells that have been programmed are refreshed.

Abstract: A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.

Abstract: An internal power supply generating circuit has a control circuit for controlling a control node voltage of a driver circuit thereof. During an overdrive duration, the control node voltage is set at an appropriate level of an operation range by controlling the control node voltage by the control circuit. By setting the control node voltage at the appropriate level, the internal power supply generating circuit can supply an internal power-supply voltage without a dead band after the overdrive duration. With this structure, the internal power supply generating circuit without the dead band can be obtained and a semiconductor device operable at a high speed comprising the internal power supply generating circuit can be obtained.

Abstract: Integrated circuits are provided that have memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable logic including transistors with gates. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the programmable logic device to customize the programmable logic. To ensure that the transistors in the programmable logic are turned on properly, the memory elements are powered with an elevated power supply level during normal device operation. During data loading operations, the power supply level for the memory elements is reduced. Reducing the memory element power supply level during loading increases the write margin for the memory elements.

Abstract: There is provided a semiconductor device supplied with internal power generated by an internal power generation circuit to perform a stable operation and, also, suppress power consumption. A control circuit, a row/column decoder and a sense amplifier are driven by an internal buck voltage. On the other hand, a data path with high power consumption is driven by an external power supply voltage. A level conversion circuit receives an address signal or a command signal having a voltage level of the external power supply voltage, converts the voltage level to the internal buck voltage, and outputs a resultant signal to the control circuit. A level conversion circuit receives a control signal having a voltage level of the internal buck voltage from the control circuit, converts the voltage level to the external power supply voltage, and outputs a resultant signal to the data path.

Abstract: An electrically programmable and erasable non-volatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed in the non-volatile semiconductor memory, the operation currently being executed is discontinued and a write-back operation is carried out to change a threshold voltage of the memory cell in the reversed direction. In addition, the configuration also allows the number of charge-pump stages in an internal power-supply configuration to be changed in accordance with the level of a power-supply voltage so as to make the write-back operation correctly executable. As a result, no memory cells are put in deplete state even in the event of a power-supply cutoff in the course of a write or erase operation.

Abstract: An internal voltage generator maintains stable level of an internal voltage without increasing physical area. The internal voltage generator includes an active level detector for detecting a level of an internal voltage by comparing the level of the internal voltage and a level of a reference voltage to thereby output a first active driving signal, a first active driver for providing the internal voltage in response to the first active driving signal, a driving time controller for generating a time driving signal activated for a predetermined time, an active driving controller for activating a second active driving signal while the time driving signal is activated and for outputting the first active driving signal as the second active driving signal while the time driving signal is inactivated, and a second active driver for providing the internal voltage in response to the second active driving signal.

Abstract: An elastic power header device and methods of operation are provided to improve the read margin of static random access memory (SRAM) cells by increasing read stability, reducing read disturbance and improving the Signal to Noise Margin (SNM) figure of merit. For example, various implementations of an elastic power header device are utilized as programmable resistances to permit the power supply lines to reach a maximum voltage. Allowing the power supply lines to reach the reference voltage allows more flexibility in read margin and read stability. Furthermore, this additional flexibility can be controlled by means for adjusting a voltage. This adjustment voltage can fine-tune the programmable resistances so that the read margin can be more conveniently controlled.

Abstract: This invention discloses a power supply management circuit which comprises at least one switching circuit coupled between a power supply and a power recipient circuit, and at least one voltage booster circuit coupled between a control circuit and the power recipient circuit, wherein the control circuit is configured to turn on-or-off the switching circuit, and to activate or de-activate the voltage booster circuit.

Abstract: A buffer cache interposed between a non-volatile memory and a host may be partitioned into segments that may operate with different policies. Cache policies include write-through, write back and read-look-ahead. Write-through and write back policies may improve speed. Read-look-ahead cache allows more efficient use of the bus between the buffer cache and non-volatile memory. A session command allows data to be maintained in volatile memory by guaranteeing against power loss.

Abstract: Methods and arrangements to configure power management systems for integrated circuits are provided herein. A group of IC components that are functionally distinct or have mutually exclusive and/or quasi-mutually exclusive, (ME/QME) operating patterns (i.e. alternate or partially overlapping duty cycles) can be powered with a single power cell. An integrated circuit design tool can identified components in an integrated circuit design that have the ME/QME operating patterns. These cells can be collocated in close proximity to each other and power management system components can be placed in this area such that a multiple signal processing cells can share a single power line and a single power cell. Such a configuration can greatly reduce the size of a power management system for an integrated circuit.

Abstract: A semiconductor IC includes a logic block, and a voltage control circuit controlling an operating voltage supplied into the logic block. The voltage control circuit controls the operating voltage to be increased in a stepwise fashion during an initial operation of the logic block.

Abstract: In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.

Abstract: A power control circuit and related method providing power to an output terminal supplying a logic block within a semiconductor integrated circuit are disclosed. The power control circuit includes a power gating circuit providing a main power voltage to the output terminal during a normal operating mode and providing a retention voltage to the output terminal during a data retention mode characterized by the absence of the main power voltage from the logic block, wherein the retention voltage is minimally sufficient to retain data stored in the logic block during the data retention mode.

Abstract: A volatile semiconductor memory includes a self-test controller detecting a defect of a memory cell, and an address storage storing a defective address indicating an address of a defective memory cell, and a refresh adjust circuit setting a refresh cycle of a memory cell designated by the defective address to be shorter than a refresh cycle of a normal memory cell.

Abstract: A state machine implemented controller is provided in which a logic core 20 is reconfigurable in response to state data held within a memory 22. Thus, on transition from one state to a next state the data held within the memory 22 is used to reconfigure the operation of the logic core 20. This enables a relatively compact logic core 20 to be used time and time again, thereby avoiding the need to individually define a logic core appropriate to each individual one of the states that the state machine can enter into. This results in a controller which is much more compact on an integrated circuit die than is the case with prior art controllers.

Abstract: According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storage locations for the cache, a detector to measure a thermal environment of the processor, and circuitry to raise an operating voltage of the processor if the actual number of unreliable storage locations exceeds the acceptable number of unreliable storage locations, and if the thermal environment is acceptable.

Abstract: A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as delay lock loops during row activations and read/write memory operations. A switch connects the array power bus to another separate power bus for a limited period of time during a DRAM refresh cycle to provide additional current to the DRAM arrays. The switch disconnects the array power bus from the other power bus preferably before the end of the refresh cycle.

Abstract: An internal voltage generator maintains stable level of an internal voltage without increasing physical area. The internal voltage generator includes an active level detector for detecting a level of an internal voltage by comparing the level of the internal voltage and a level of a reference voltage to thereby output a first active driving signal, a first active driver for providing the internal voltage in response to the first active driving signal, a driving time controller for generating a time driving signal activated for a predetermined time, an active driving controller for activating a second active driving signal while the time driving signal is activated and for outputting the first active driving signal as the second active driving signal while the time driving signal is inactivated, and a second active driver for providing the internal voltage in response to the second active driving signal.

Abstract: A method and apparatus of dynamically storing critical data of a gaming machine by allocating and deallocating memory space in a gaming machine is disclosed. One or more embodiments describe downloading or removing a new game to a gaming machine such that all existing critical data in NV-RAM memory is left intact. In one embodiment, the invention discloses a method and apparatus for dynamically allocating and deallocating memory space to accommodate either permanent or temporary storage in an NV-RAM. A method and apparatus is provided to monitor available memory space and dynamically resize the memory in NV-RAM. In one embodiment, a method is disclosed for performing an integrity check of the NV-RAM and determining whether a critical data error has occurred. In one or more embodiments, methods of compacting and shifting contents of an NV-RAM are described to consolidate available memory space or to prevent unauthorized access of NV-RAM memory.

Abstract: A semiconductor memory device for consuming a uniform amount of current includes a memory cell block including a N normal wordline and a M preliminary wordline; a refresh address counting block for outputting a refresh address, having a plurality of bits, corresponding to the N normal wordline and the M preliminary wordline; a refresh counting control block for resetting the refresh address counting block when the refresh address counts a predetermined count during a test mode; and a row decoding block for refreshing unit cells coupled to the N normal wordline and unit cells coupled to the M preliminary wordline of the memory cell block according to the refresh address and a redundancy control signal outputted from the refresh counting control block, wherein M, N are positive integers.

Abstract: When it is detected that the voltage of a main power supply is reduced below a predetermined value during a normal operation, a power controller switches a power supply for a DRAM from the main power supply to a battery power supply and makes an instruction signal for instruction a self-refresh mode to a memory controller active. In response to this, the memory controller changes a clock enable signal for the DRAM to a low level to establish the self-refresh mode of the DRAM, and, after, the self-refresh mode of the DRAM is established, supplying of power to the memory controller is stopped. The clock enable signal for the DRAM is maintained to the low level by pull-down resistance even when the supplying of power to the memory controller is stopped from a condition that the signal is changed to the low level in the self-refresh mode, thereby maintaining the self-refresh mode of the DRAM.

Abstract: A system or method to partition data in a memory based at least in part to a data type, and to refresh the memory based at least in part to the data type.

Abstract: After a refresh operation, a word control circuit holds the selection state of a word line selection signal line selected in each memory block corresponding to a refresh address. Further, in response to an access request, the word control circuit unselects only a word line selection signal line of a memory block selected by an external address corresponding to this access request. In each memory block, the word line selection signal line once selected is not unselected until the access request is received, so that the frequency of unselection and selection of the word line selection signal lines can be lowered. Consequently, a charge/discharge current of the word line selection signal lines can be reduced, which can reduce current consumption of a semiconductor memory.