Abstract: A semiconductor integrated circuit device has an address decoder which is constructed of a plurality of MOSFETs implemented in a switch tree. The switch tree includes first and second switch tree portions which are controlled `on` and `off` by the same input signals. A first switch branch in the first switch tree portion, which is constructed of a comparatively small number of MOSFETs, and a second switch branch in the second switch tree portion, which is constructed of a comparatively large number of MOSFETs, are controlled `one` and `off` by the same input signal, while a second switch branch in the first switch tree portion, which is constructed of a comparatively large number of MOSFETs, and a first switch branch in the second switch tree portion, which is constructed of a comparatively small number of MOSFETs, are controlled `on` and `off` by the same input signal.

Abstract: A microcomputer comprises an address decoder (23) for providing address signals to a random access memory (21). The address decoder (23) is adapted to generate a plurality of address signals in accordance with one piece of instruction data obtained from an instruction register (10). On the other hand, a control circuit (11) is provided for generating change signals in response to the instruction data for controlling a T type flip-flop (24, 25 or 26). The address decoder is responsive to the signal from the T type flip-flop to select and provide one of the plurality of address signals. Accordingly, a plurality of addresses are designated in accordance with one piece of the instruction data, whereby one of them is selected by a change signal. Thus, a program for addressing a random access memory can be simplified.

Abstract: A cross bar multiplexer includes a plurality of small memory units addressable to indicate combinations of output conductors. The outputs of a plurality of memory units are ORed to provide the outputs for a full array.

Abstract: A memory circuit has a decoder circuit for receiving address signals and generating word designating signals. The decoder circuit has a plurality of decoder circuit blocks and includes a circuit for receiving some of the address signals and generating signals designating one of the decoder circuit blocks, whereby the current flowing in each of the decoder circuit blocks is reduced as long as the blocks are not designated.

Abstract: A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled driver transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.

Abstract: An integrated circuit wherein a gate circuit is provided on a bus line mounted on a semiconductor substrate. The gate circuit is used to separate an unused circuit block from other circuit blocks which are connected to a bus line through an input-output circuit for high speed data transmission, thereby reducing a parasitic capacity which might be imparted to the bus line by the separated circuit block. The input-output circuit is formed of a clocked inverter. The gate circuit is formed of a C.multidot.MOS transmission gate. The input-output circuit and gate circuit are so connected that where the gate of the inverter is opened, then the C.multidot.MOS transmission gate is closed; and where the gate of the inverter is closed, then the C.multidot.MOS transmission gate is opened.

Abstract: Disclosed is a memory device having a plurality of memory cells arranged in a matrix form; address buses connected to the memory cells and forming respective rows of the matrix; and data buses connected to the memory cells and forming respective columns of the matrix.The address buses or the data buses are formed by paired bus lines, and bridge lines are formed between one and the other of the paired bus lines.

Abstract: Apparatus for assembling binary data bits in parallel by groups in variable, selected locations in a shift register for subsequent serial readout. One or more shift registers are arranged in a matrix of rows and columns of storage cells and addressed along one coordinate while a plurality of data are applied in parallel along the orthogonal. Selector circuits are controlled to selectively shift a data word to enable the first bit in the word to be stored in any storage position within the addressed coordinate, with each remaining bit in the word stored in a correspondingly contiguous storage position in the matrix. Bit storage cells of the shift registers are of the set-reset latch type so that once set they cannot be changed by subsequent data bits until the entire array is reset. This enables the overwriting of successive data bytes.

Abstract: Semiconductor storage switching circuits and integrated circuit storage array devices that employ them are characterized by the fact that each individual cell of the storage array requires only a single active device, each such active device consisting of a three terminal, controlled-inversion device of metal, non-linear resistor, and semiconductor layers, the active device having controllable switching characteristics through the use of silicon dioxide, polycrystalline silicon, or nitrides of silicon in its non-linear resistive layer. Control circuits associated with the memory arrays make possible the unique selection of any one predetermined cell to write, erase, or read its content. Grounded base and grounded emitter forms of the storage devices are provided, as well as random access memory devices.

Abstract: A Y address decoder used in conjunction with an X-Y matrix array, high density read-only memory unit, that reduces the number of series FET stages in the electrical path needed to evaluate the logic state of an addressed cell location of such a read-only memory unit. The reduction is achieved by gating logic in which the signal stored in the evaluated cell location, is derived from the output terminals of a tier of decoders, the appropriate decoder being connected directly to an output driver by a gate-controlled switch. The gate signal to render each such switch conductive is generated by an AND-OR circuit in repsonse to a unique Y address code, thereby obviating the otherwise time-consuming requirement for the evaluation signal to flow through additional tiers of decoders.