Abstract: A semiconductor memory device includes: a memory cell array; a peripheral circuit connected to this memory cell array, the peripheral circuit outputting data in the memory cell array as a read data in response to input of a command set, the command set including a first command, address data, and a second command; a first electrode capable of being used in input of the command set and output of the read data; and a second electrode capable of supplying electric power to the peripheral circuit. A current flowing in the second electrode at a second timing is larger than a current flowing in the second electrode at a first timing, the first timing being a timing at which the first command is inputted, the second timing being a timing before which the input of the address data is started and after which an input of the second command is finished.

Abstract: A memory device includes receivers that use CMOS signaling levels (or other relatively large signal swing levels) on its command/address and data interfaces. The memory device also includes an asynchronous timing input that causes the reception of command and address information from the CMOS level receivers to be decoded and forwarded to the memory core (which is self-timed) without the need for a clock signal on the memory device's primary clock input. Thus, an activate row command can be received and initiated by the memory core before the memory device has finished exiting the low power state. Because the row operation is begun before the exit wait time has elapsed, the latency of one or more accesses (or other operations) following the exit from the low power state is reduced.

Abstract: A control circuit and a control method thereof adapted to a pseudo static random access memory are provided. The control circuit includes a write data determining circuit and a clock generating circuit. The write data determining circuit counts and compares data input times and actual data write times of the pseudo static random access memory to generate a write matching signal, and generates a write counting clock signal according to counting operation of the data input times of the pseudo static random access memory. The clock generating circuit generates a preamble signal according to the write matching signal and the write counting clock signal, and generates a column address strobe clock signal and a control signal according to the preamble signal. The clock generating circuit determines whether to dynamically delay the preamble signal to delay or omit a pulse of a column selection line signal.

Abstract: A dynamic random-access memory (DRAM) device includes memory banks configured to store data and provide access to the stored data; and a data control circuit coupled to the memory banks, the data control circuit configured to: determine a pointer based on a received command, wherein the pointer corresponds to a target memory bank associated with the received command, and route a set of bits to or from the target memory bank using the pointer. In the long burst length and page mode operations where the array access is targeted in certain Bank Group, the pointer is generated and then allow the groups of data bits flowing through the center freely. This pseudo flow through scheme is low power and fast speed by removing the control of gating commands at each stage of the data path during Read and Write operations.

Abstract: A method for writing a mode register in a semiconductor device, the method includes receiving a mode register command and a mode signal; generating a first mode register setting signal; delaying the first mode register setting signal in a first latency shifter to provide a second mode register setting signal; receiving a data signal in synchronization with the second mode register setting signal; and writing the mode signal to the mode register only if the received data signal has a first logic level.

Abstract: An output driver includes a pre-driver receiving a driver control code to generate a pull-up control signal or a pull-down control signal in response to data while a read operation is performed, an on-die termination controller receiving a first on-die termination control code to generate a first on-die termination control signal in response to an on-die termination enable signal while a write operation is performed, and a main driver including a pull-up n-channel metal-oxide-semiconductor (NMOS) driver generating high-level output data in response to the pull-up control signal while the read operation is performed, and terminating high-level input data with a first high voltage and terminating low-level input data with a first low voltage in response to the first on-die termination control signal while the write operation is performed, and a pull-down NMOS driver generating low-level output data in response to the pull-down control signal while the read operation is performed.

Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

Abstract: A circuit includes one or more memory cells, a data line associated with the one or more memory cells, one or more reference cells, a reference data line associated with the one or more reference cells, a first circuit coupled to the reference data line and the data line, and a second circuit. The first circuit is configured to output a first logical value based on a voltage level of the data line upon occurrence of a voltage level of the reference data line reaching a trip point. The second circuit is configured to output a second logical value based on the voltage level on the data line prior to the occurrence of the voltage level of the reference data line reaching the trip point, and to output the first logical value after the occurrence of the voltage level of the reference data line reaching the trip point.

Abstract: A method is provided for relaying data to a memory array operating in synchronization with a clock signal having a first transition edge. A data strobe signal having a second transition edge corresponding to the first transition edge is provided. A first signal is provided. The data is latched into the first signal at a first time point lagged behind the first transition edge by a first time interval until a second time point in response to the first transition edge for relaying the data of the first signal to the memory array when the second transition edge appears earlier than the first transition edge.

Abstract: A semiconductor memory device includes an internal address generating circuit; an internal command generating circuit; and a memory cell array including one or more memory bank groups. The semiconductor memory device is configured such that when a read command or a write command is input, if a first portion of a plurality of memory banks of a first memory bank group from among one or more memory bank groups of the memory cell array performs a read operation or a write operation, a second portion of the plurality of memory banks of the first memory bank group performs a refresh operation.

Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

Abstract: A semiconductor storage apparatus according to the present invention includes a plurality of memory cells, a plurality of word lines, a plurality of pairs of bit lines, a plurality of sense amplifiers, a pair of common data lines, a data-to-be-written output circuit configured to, in writing data, set voltages of the common data lines forming the pair, a column selection signal output unit configured to output a plurality of column selection signals, and a plurality of column selection gates, in which in writing the data, the column selection signal output unit selectively turns on one of the column selection gates by setting each of voltages of the column selection signals to one of a level of a higher-potential power supply voltage and a level of a lower-potential power supply voltage, before activating the sense amplifiers.

Abstract: An 8T memory bit cell receives a clock signal and read and write address signals. A read address latch/clock circuit receives the clock signal and the read address signals and initiates a read operation during a first clock cycle state. A write address flip-flop/clock circuit receives the clock signal and the write address signals and initiates a write operation during a second clock cycle state. An inverter receives and inverts the clock signal and applies the inverted clock signal to the write address flip-flop/clock circuit. The read address latch/clock circuit initiates a read word line precharge operation during the second clock cycle state and a write word line precharge operation during the first clock cycle state. The write address flip-flop/clock circuit may also include a loose self-timer to end a write cycle is a clock signal continues beyond a predetermined time.

Abstract: A non-volatile memory system evaluates user data before writing in order to potentially group addresses for writing within a cycle. The system can determine which sense amplifier addresses of a column address will be programmed in a column address cycle. The number of bits that will be programmed is compared with an allowable number of parallel bits. The system generates groups of sense amplifier addresses based on the comparison. The system generates groups that include a total number of bits to be programmed that is within the allowable number of parallel bits. Each group is programmed in one sense amplifier address cycle. Multiple sense amplifier addresses can be grouped for programming while still remaining within an allowable number of parallel programming bits. The system performs a read before write operation and generates bitmap data for the grouping information corresponding sense amplifier addresses.

Abstract: A write leveling calibration system and method for double data-rate dynamic random access memory includes performing write leveling at two different frequencies to determine to which of two successive rising clock cycle edges each data strobe signal would be aligned as a result of applying the write leveling delay determined by the write-leveling procedure. The determination can then be used to ensure that the data strobe signals of all source synchronous groups are aligned with the same edge of the clock signal.

Abstract: An on-die termination circuit including: a DQS circuit block configured to terminate a DQS pad in response to a first impedance adjustment signal which is transmitted through a global line; and a DQ circuit block configured to terminate a DQ pad in response to a second impedance adjustment signal which is generated by changing the first impedance adjustment signal or a value of the first impedance adjustment signal depending on whether a setup operation proceeds.

Abstract: A memory control module includes a read module configured to receive a first signal read from a first storage region of a memory cell, and receive a second signal read from a second storage region of the memory cell. A data detection module is configured to, based on a noiseless signal, detect respective data in each of the first storage region and the second storage region. The noiseless signal includes an ideal signal and an interference signal associated with at least one of the first signal and the second signal.

Abstract: Methods and systems for detection and correction of timing signal drift in memory systems are provided. A start time and an end time of a first time interval is determined with control circuitry such that a last falling edge in a first of a plurality of data strobe sequences received from the memory occurs outside of the first time interval. A start time and an end time of a close-enable time interval is adjusted based at least in part on determining whether a second of the plurality of data strobe sequences occurs within the first time interval. Sampling of data received from the memory is disabled in response to determining that the last falling edge in the second received data strobe sequence occurs within the close-enable time interval.

Abstract: A method and circuit for implementing faster-cycle-time and lower-energy write operations for Synchronous Dynamic Random Access Memory (SDRAM), and a design structure on which the subject circuit resides are provided. A first RAS (row address strobe) to CAS (column address strobe) command delay (tRCD) is provided to the SDRAM for a read operation. A second delay tRCD is provided for a write operation that is substantially shorter than the first delay tRCD for the read operation.

Abstract: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.

Abstract: A memory operative to provide concurrent two-port read and two-port write access functionality includes a memory array comprising first and second pluralities of single-port memory cells organized into a plurality of rows of memory banks, and multiple checksum modules. The second plurality of memory cells are operative as spare memory banks. Each of the checksum modules is associated with a corresponding one of the rows of memory banks. The memory further includes a first controller and multiple mapping tables. The first controller and at least a portion of the first and second pluralities of memory cells enable the memory array to support two-port read or single-port write operations. A second controller is operative to receive read and write access requests, and to map logical and spare memory bank identifiers to corresponding physical memory bank identifiers via the mapping tables to thereby emulate concurrent two-port read and two-port write access functionality.

Abstract: A memory interface circuit includes a gating circuit that starts detection of a logic level of a data strobe signal in accordance with a data read command. A clamp circuit clamps the data strobe signal to a first logic level after the data read command is issued. A detection circuit detects a logic level of the data strobe signal, which is driven by the memory, in accordance with the data read command.

Abstract: A system including a read module and a sequence detector module. The read module is configured to read a plurality of memory cells located along a bit line or a word line of a memory array and to generate a plurality of read signals. The sequence detector module is configured to detect a sequence of data stored in the plurality of memory cells based on (i) the plurality of read signals and (ii) a plurality of reference signals associated with the plurality of memory cells. One of the plurality of reference signals associated with a first memory cell of the plurality of memory cells includes (i) a first signal and (ii) a second signal. The first signal is free of interference from a second memory cell adjacent to the first memory cell along the bit line or the word line. The second signal includes interference from the second memory cell.

Abstract: Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous path and an asynchronous path. A Write-with-Autoprecharge signal is provided to the synchronous path, and various bank address signals are provided to the asynchronous path. In another embodiment, the initiation of the bank address signals may be provided asynchronously to the assertion of the Write-with-Autoprecharge signal.

Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

Abstract: Some embodiments include methods of reading memory cells. The memory cells have a write operation that occurs only if a voltage of sufficient absolute value is applied for a sufficient duration of time; and the reading is conducted with a pulse that is of too short of a time duration to be sufficient for the write operation. In some embodiments, the pulse utilized for the reading may have an absolute value of voltage that is greater than or equal to the voltage utilized for the write operation. In some embodiments, the memory cells may comprise non-ohmic devices; such as memristors and diodes.

Abstract: In a multi-level memory cell, when data to be programmed arrives, the cell is programmed to the lowest-charge state in which any bit position that is being programmed or has already been programmed has the correct value, regardless of the value in that state of any bit position that has not yet been programmed and is not being programmed. The programming of other bit positions based on subsequently arriving data should not then require a transition to an impermissible lower energy state. Although this may result in a transient condition in which some bits have the wrong value, by the time programming is complete, all bits would be expected to have the correct value. A cell may contain any number of bits equal to or greater than two, and programming may be performed cyclically (e.g., from LSB to MSB), anticyclically (e.g., from MSB to LSB), or in any random order.

Abstract: A synchronous type semiconductor storage device includes an array unit which includes a cell array and sense amplifiers. The synchronous type semiconductor storage device includes a read/write pulse generator which generates a read pulse signal and a write pulse signal according to a clock signal, the clock signal defining one cycle time of a read operation and a write operation with respect to the array unit as one cycle. The synchronous type semiconductor storage device includes a secondary amplifier which is activated according to the read pulse signal to read out data stored in the sense amplifiers through the read/write line. The synchronous type semiconductor storage device includes a write driver which is activated according to the write pulse signal to write data in the sense amplifiers through the read/write line.

Abstract: Described herein are embodiments of dynamic command slot realignment after clock stop exit. An apparatus configured for dynamic command slot realignment after clock stop exit may include memory including a first memory module configured to receive commands over a first channel via a first command slot and a second memory module configured to receive commands over a second channel via a second command slot, and a memory buffer configured to receive a clock sync command targeting the first command slot, and perform a write pointer exchange in response to detecting the clock sync command in the second command slot to realign the first command slot and the second command slot. Other embodiments may be described and/or claimed.

Abstract: An on-die termination circuit including: a DQS circuit block configured to terminate a DQS pad in response to a first impedance adjustment signal which is transmitted through a global line; and a DQ circuit block configured to terminate a DQ pad in response to a second impedance adjustment signal which is generated by changing the first impedance adjustment signal or a value of the first impedance adjustment signal depending on whether a setup operation proceeds.

Abstract: An on-die termination (ODT) circuit of a memory device comprising: a memory device having a memory core having a memory cell array; a data input/output pin connected to the memory core through a data buffer; and an on-die termination (ODT) circuit, comprising: a termination circuit configured to provide a termination impedance at the input/output data pin, the termination circuit having a switching device that selectively connects a termination impedance to the input/output data pin based on the presence of an asynchronous control signal (ACS), wherein the ACS is generated based on the presence of a memory WRITE command.

Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

Abstract: A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.

Abstract: Integrated circuits may communicate with off-chip memory. Such types of integrated circuits may include memory interface circuitry that is used to interface with the off-chip memory. The memory interface circuitry may be calibrated using a procedure that includes read calibration, write leveling, read latency tuning, and write calibration. Read calibration may serve to ensure proper gating of data strobe signals and to center the data strobe signals with respect to read data signals. Write leveling ensures that the data strobe signals are aligned to system clock signals. Read latency tuning serves to adjust read latency to ensure optimum read performance. Write calibration may serve to center the data strobe signals with respect to write data signals. These calibration operations may be used to calibrate memory systems supporting a variety of memory communications protocols.

Abstract: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.

Abstract: Methods and systems for detection and correction of timing signal drift in memory systems are provided. A start time and an end time of a first time interval is determined with control circuitry such that a last falling edge in a first of a plurality of data strobe sequences received from the memory occurs outside of the first time interval. A start time and an end time of a close-enable time interval is adjusted based at least in part on determining whether a second of the plurality of data strobe sequences occurs within the first time interval. Sampling of data received from the memory is disabled in response to determining that the last falling edge in the second received data strobe sequence occurs within the close-enable time interval.

Abstract: A non-volatile storage system reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. First, second and third sets of non-volatile storage elements are programmed in separate sequences, one after another, so that all program-verify operations occur for the first set, then for the second set, and then for the third set. Each non-volatile storage element in a set is separated from the next closest non-volatile storage element in the set at least two other non-volatile storage elements in the set.

Abstract: Low supply voltage memory apparatuses are presented. In one embodiment, a memory apparatus comprises a memory and a memory controller. The memory controller includes a read controller. The read controller prevents a read operation to a memory location from being completed, for at least N clock cycles after a write operation to the memory location, where N is the number of clock cycles for the memory location to stabilize after the write operation.

Abstract: A data input circuit includes a valid strobe signal generation circuit and a data strobe signal counter. The valid strobe signal generation circuit is configured to remove a pulse of an internal strobe signal generated and generate a valid strobe signal. The pulse may have been generated during a preamble period. The data strobe signal counter is configured to count the valid strobe signal according to burst length information and generate a write latch signal for aligning data at a time of a write operation.

Abstract: Selecting bins in a memory by receiving a target cost for performing writes at an analog memory that is capable of storing a range of values. Possible bins that may be created in the range of values and a cost associated with each possible bin are determined. Each possible bin includes one or more of the values. A group of bins are identified, the group of bins are among the possible bins with associated costs that are within a threshold of the target cost. A maximum number of bins are selected from the group of bins that have non-overlapping values. The selected bins are stored along with the values of the selected bins utilized to encode and decode contents of the analog memory.

Abstract: A non-volatile storage system reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. Alternate pairs of adjacent bit lines are grouped into first and second sets. Non-volatile storage elements of the first set of pairs are subject to program pulses and verify operations in each of a first number of iterations, after which non-volatile storage elements of the second set of pairs is subject to program pulses and verify operations in each of a second number of iterations.

Abstract: A memory controller includes a circuit to generate a strobe signal for write operations to a DDR SDRAM. The circuit efficiently generates a glitch free strobe signal for a group of data lines. In one implementation, the memory controller includes a write data generation circuits to each transmit a data signal to the memory on a data line, the write data generation circuits being controlled by write enable signals. A write strobe generation circuit generates the strobe signal and the write enable signals, the strobe signal including a preamble window to signal the beginning of the data burst, a data transfer window, and a postamble window to signal the end of the data burst, the write strobe generation circuit generating the write enable signals a half memory cycle early and terminating the write enable signals a half memory cycle late with respect to the data signals generated by the write data generation circuits.

Abstract: A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path.

Abstract: A semiconductor device including a plurality of memory cells arranged in a matrix pattern, a write amplifier which writes write data to the memory cell in synchronization with a clock, a sense amplifier which reads out the write data written in the memory cell in synchronization with the clock, a plurality of column select switches which connect the plurality of the memory cells with the sense amplifier and the write amplifier, a column address decoder which makes the column select switch corresponding to one column among the plurality of the memory cells a conductive state based on a column address, a row address decoder which activates the memory cell of one row based on a row address, and a test write circuit which writes data corresponding to a logical level of a test signal to the memory cell based on a test mode signal.

Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

Abstract: A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.

Abstract: In a non-volatile logic circuit, a first input electrode and a second input electrode are formed on a semiconductor layer and interposed between an electric current source electrode and an output electrode in a plan view. The first input electrode is next to the second input electrode along the a direction orthogonal to the direction between the electric current source electrode and the output electrode. A method of operating the non-volatile logic circuit includes a step of writing one state selected from four states by applying voltages to the first input electrode and the second input electrode, respectively, and a step of measuring current generated by applying the voltage between the electric current power electrode and the output electrode to determine on the basis of the current, which of the high or low resistant state the non-volatile logic circuit has.

Abstract: A method is provided for writing data to a memory array operating in synchronization with a clock signal having a transition edge. A data strobe signal having a transition edge corresponding to the transition edge of the clock signal is provided. The transition edge of the clock signal is used to relay the data corresponding to the transition edge of the data strobe signal if the transition edge of the data strobe signal is coming in earlier than the transition edge of the clock signal, wherein the clock signal has a rising edge and a falling edge, the data strobe signal has a rising edge and a falling edge respectively corresponding to the rising and the falling edges of the clock signal, and the transition edge of the clock signal is one of the rising and the falling edges of the clock signal.

Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.