Abstract: A memory array has a plurality of rows including a plurality of memory words. Each first bit of a plurality of first bits is associated with a memory word of the each row. A state of the each first bit indicates whether the associated memory word has had an error. Each redundancy row of a plurality of redundancy rows includes a plurality of redundancy words. Each redundancy word is associated with a memory word. A corrected data cache has at least one repair word configured to store corrected data and at least one status bit associated with the at least one repair word, the status bit indicating whether the corrected data stored in the repair word is a pending repair. The corrected data cache is configured to write the corrected data stored in the repair word to at least one of a counterpart memory word or a counterpart redundancy word.

Abstract: The invention combines several techniques applying high-resolution photosensitive emulsions for the long-term, archival storage of data, images and text. Data is stored as vertical interference patterns of multiple frequencies in a photographic emulsion. Read-out of the stored data uses a precision mechanism to locate and decode stored data.

Abstract: A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches.

Abstract: A memory system comprises a memory including a plurality of bits arranged as one or more words. Each bit in each word is capable of being programmed either to a particular logical state or to another logical state. A variable data width controller is in communication with the memory. The variable data width controller comprises an adder to determine a programming number of bits in a word to be programmed into a memory. Each bit to be programmed is in the particular logical state. A partitioning block divides the word in to two or more sub-words when the programming number exceeds a maximum number. A switch is in communication with the partitioning block. The switch sequentially provides one or more write pulses. Each write pulse enables a separate communication path between the memory and one of the word and the sub-words.

Abstract: A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages.

Abstract: In one embodiment, there is provided an electronic apparatus. The apparatus includes: a storage device including a plurality of blocks that are units of data erasure. Each of the blocks includes a plurality of pages that are units of data reading or writing. Each of the pages includes: a data area storing a data; and a redundant area storing order information indicating an order of the data stored in the data area.

Abstract: Embodiments of the inventive concept provide a nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a read/write circuit, and a backup circuit. The memory cell array includes a first memory block including a first word line having first memory cells and a second word line having second memory cells. Each of the first memory cells and second memory cells configured to store first-bit data and second-bit data. The read/write circuit is configured to program data into the first and second memory cells and read data stored in the first and second memory cells. The backup circuit is configured to, after first-bit data are programmed into the first word line, but before second-bit data are programmed into the first word line, store first-bit data stored in the second memory cells of the second word line.

Abstract: A memory device is provided. The memory device comprises a plurality of memory chips. The plurality of memory chips receive an input address code and alternately operate in an active mode. Each memory chip receives a selection signal and operates according to an internal address counter code. For each memory chip, the respective internal address counter code is initially set according to the input address code and the respective selection signal.

Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.

Abstract: A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches.

Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.

Abstract: There is provided an optical information detecting method. The method includes: detecting an image of a source data page coded with balanced codewords by the use of 1:N (where N is greater than 1) excessive detection pixels; determining a distribution pattern of valid detection pixels and invalid detection pixels to be corrected in the detected image by the use of a light intensity distribution of the detected image; and dividing the detected image into balanced codeword detecting areas corresponding to the balanced codewords and sampling data of the balanced codeword detecting areas by the use of the determined distribution pattern and an optical distribution characteristic of the balanced codewords. Accordingly, it is possible to efficiently detect optical information by the use of a 1:N over-sampling method. Specifically, the distribution pattern of valid detection pixels and invalid detection pixels in the detected image of a data page can be properly used to sample a balanced code.

Abstract: A data input circuit includes a first data input unit, a second data input unit, and a clock unit. The first data input unit is configured to receive external data at rising edges of a data strobe signal and output the external data as first internal data in response to an internal clock. The second data input unit is configured to receive the external data at falling edges of the data strobe signal and output the external data as second internal data in response to the internal clock. The clock unit is configured to generate the internal clock using an external clock signal.

Abstract: Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.

Abstract: A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches.

Abstract: A nonvolatile memory device comprises a page buffer unit, first to kth logic combination units, and a control unit. The page buffer unit includes first to Nth page buffer blocks. N and k are natural numbers. Each of the first to Nth page buffer blocks comprises m page buffers, divided into first to kth page buffer groups, and first to kth pass/fail check units configured to output respective verification signals, each indicative of a program pass or a program fail, according to data stored in latches of the page buffers included in each of the page buffer groups. The first to kth logic combination units are each configured to output respective first to kth pass/fail determination signals.

Abstract: Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.

Abstract: A page buffer includes a first ground voltage supply unit for applying a ground voltage to first and second registers according to a level of a sense node, and a second ground voltage supply unit for applying the ground voltage to the first and second registers irrespective of a level of the sense node. A method of programming a non-volatile memory device includes storing a high-level data in a first node of a first register of a plurality of page buffers, precharging a sense node with a high level, resetting the data stored in the first node of the first register according to a voltage level of the sense node, precharging the sense node with a high level, storing external data in the first node according to a voltage level of the sense node, and performing a program operation according to the data stored in the first node.

Abstract: A voltage supply circuit includes a voltage generator and a controller. The voltage generator is configured to pump an externally input voltage and store the pumped external voltage as a first voltage having a set voltage level, before power-up begins, or pump the external voltage, add the pumped voltage to the stored voltage, and output the added voltage as an operating voltage. The controller is configured to output a first control signal to drive the voltage generator or stop operation of the voltage generator, according to an operating state.

Abstract: Data hologram recycling systems, methods and computer program products are configured to arrange data for storage in the intermediate data storage as data segments which are replicas of holographic storage segments for destaging to the holographic data storage, and to determine retrieval for recycling of the destaged holographic storage segments to which aggregated requests for deletion are directed. The retrieval determination may be based on a plurality of policies.

Abstract: A printed circuit board may include a memory controller, a plurality of synchronous data memory devices, each synchronous memory device including at least one data pin and at least one address/command pin, an ECC memory device including at least one ECC data pin and at least one ECC address/command pin, and at least one surface. The plurality of synchronous data memory devices may be arranged around a central location on the at least one surface and each synchronous data memory device may be oriented such that the at least one data pin is further from the memory controller than the at least one address/command pin.

Abstract: Data for storage by holographic data storage is arranged in an intermediate data storage as data segments which are replicas of holographic storage segments. Files of data are aggregated into the data segments, and a destaging control determines the destaging of the data segments to the holographic data storage in accordance with a plurality of policies, such as whether a segment is full, a time threshold has been reached, or whether a threshold number of segments are “open”. The intermediate data storage may be arranged into a number of partitions at least equal to the number of sources having input to the data destaging system, the partitions comprising integral multiples of the data segments.

Abstract: Data for storage by holographic data storage is arranged in an intermediate data storage as data segments which are replicas of holographic storage segments. Files of data are aggregated into the data segments, and a destaging control determines the destaging of the data segments to the holographic data storage in accordance with a plurality of policies, such as whether a segment is full, a time threshold has been reached, or whether a threshold number of segments are “open”. The intermediate data storage may be arranged into a number of partitions at least equal to the number of sources having input to the data destaging system, the partitions comprising integral multiples of the data segments.

Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.

Abstract: A memory system including a nonvolatile semiconductor memory device and a controller. The memory device includes a plurality of word lines; and a plurality of memory cells each connected to a corresponding one of the word lines and each having N threshold voltages for storing multi-valued level, where N is a natural number of 4 or greater; wherein stored data in each of the plurality of memory cells constitutes a plurality of pages, at least only a part of multi-value level is used for storing data, a data “1” is always written to a lower page, a “0” or “1” binary data is written to an upper page, the same data is written in each of the pages when writing in the nonvolatile memory device, and only part of the pages to which the same data is written is accessed when reading out the nonvolatile memory device.

Abstract: Circuits and methods are provided for controlling multi-page erase operations in flash memory. The page address of each address of a multi-page erase operation is latched in wordline decoders. A page select reset generator circuit processes the block addresses of each address of the multi-page erase operation. In the event the addresses relate to pages in different blocks, then previously latched page addresses are reset. This avoids the incorrect circuit operation that will result should a multi-page erase operation include multiple pages in different blocks.

Abstract: A memory mapping method is provided for writing block data composed of a plurality of lines in first and second memories, each memory including at least two banks of the same number. The method maps the memories such that continuous even-numbered lines are written in different banks of different memories, and continuous odd-numbered lines are written in different banks of different memories when the block data is motion-compensated in a frame mode or a field mode. Accordingly, bank interleaving can be carried out in the respective memories and two memory channels can be simultaneously used to improve bus utilization efficiency and memory channel utilization efficiency.

Abstract: A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline driver. These wordline drivers have a subset of the global wordlines as inputs. The desired wordline driver is selected by an appropriate select signal from a block decoder and an indication on an appropriate global wordline. This causes the wordline driver to generate a local wordline to the desired block with the reallocated page to be accessed.

Abstract: A bit line resetting signal is supplied to the gate of an nMOS transistor (or a precharge circuit) which connects a bit line with a precharge voltage line. The high-level voltage of the bit line resetting signal is retained at a first voltage during the precharge operation after a refresh operation, and is retained at a second voltage higher than the first voltage during the precharge operation after an access operation. In the precharge operation after the refresh operation, therefore, the second voltage is not used so that the current consumption of the generating circuit of the second voltage is reduced. Thus, it is possible to reduce the current consumption (or the standby current) during the standby period for which the internal refresh requests continuously occur.

Abstract: Methods for setting a read voltage in a memory system which comprises a flash memory device and a memory controller for controlling the flash memory device, comprise sequentially varying a distribution read voltage to read page data from the flash memory device; constituting a distribution table having a data bit number and a distribution read voltage, the data bit number indicating an erase state among the page data respectively read from the flash memory device and the distribution read voltage corresponding to the read page data; detecting distribution read voltages corresponding to data bit numbers each indicating maximum points of possible cell states of a memory cell, based on the distribution table; and defining new read voltages based on the detected distribution read voltages.

Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number of threshold voltage ranges. One method includes programming a lower page of a first wordline cell to increase a threshold voltage (Vt) of the first wordline cell to a first Vt within a lowermost Vt range. The method includes programming a lower page of a second wordline cell prior to programming an upper page of the first wordline cell. The method includes programming the upper page of the first wordline cell such that the first Vt is increased to a second Vt, wherein the second Vt is within a Vt range which is then a lowermost Vt range and is positive.

Abstract: A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches.

Abstract: A flash memory device comprises an array of memory cells capable of storing different numbers of bits per cell. A page buffer circuit for the flash memory device comprises a plurality of page buffers, each operating during programming, erasing, and reading operations of the memory cells. A control logic unit controls functions of the page buffers in accordance with the number of bits stored in corresponding memory cells.

Abstract: In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified will be to estimate the initial value of a starting programming voltage for the page. The estimation is further refined by using the estimate from a first pass in a second pass. Also, when the test is over multiple blocks, sampling of word lines based on similar geometrical locations of the blocks can yield a starting programming voltage optimized for faster programming pages.

Abstract: A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline driver. These wordline drivers have a subset of the global wordlines as inputs. The desired wordline driver is selected by an appropriate select signal from a block decoder and an indication on an appropriate global wordline. This causes the wordline driver to generate a local wordline to the desired block with the reallocated page to be accessed.

Abstract: A semiconductor integrated circuit device has a page buffer, several memory cells to which data is written in accordance with write data stored in the page buffer, and an accumulating counter. The accumulating counter accumulates and stores a number of program loops spent for data write to several memory cells, and outputs the accumulated and stored number of program loops.

Abstract: A Fast Fourier Transform (FFT) apparatus for selectively performing Fast Hadamard transform (FHT), and a complementary code keying (CCK) modulation/demodulation apparatus using the same. An OFDM module and CCK module are integrated as one module having lower complexity compared to conventional scheme by embodying the CCK modulation using FFT structure in the OFDM module, and embodying the suboptimal and the optimized CCK modulations using FFT structure in OFDM module. CDMA, OFDM, CCK modules may be integrated as single module.

Abstract: A method for implementing a counter in memory, e.g., non-volatile memory such as flash memory. A first number of first binary values indicating a first portion of a current number of the counter in a binary field may be stored in a portion of memory. Storing the first number may also include increasing the number of first binary values in the binary field. Additionally, a second number indicating a second portion of the current number of the counter may be stored in another portion of memory. The second number may specify the number of times the first binary values has comprised the entirety of the binary field. Thus, the first number and second number may specify the current number of the counter. Storing the first and second number may be performed a plurality of times to implement a counting function of the counter.

Abstract: A page access circuit of a semiconductor memory device comprises a page address detecting unit configured to detect transition of a page address in response to a page address control signal so as to generate a page address detecting signal, a page control unit configured to control the page address control signal depending on transition of a sense detecting signal for notifying end of operation of a bit line sense amplifier, and a column control unit configured to generate a column selecting signal in response to the page address control signal when the page address detecting signal is activated.

Abstract: A flash memory system capable of inputting/outputting data in units of sectors at random. The flash memory system includes a flash memory (a cell array), a buffer memory, a random data input/output circuit, and a control circuit. The random data input/output circuit receives data in units of sectors from the buffer memory or outputs the data in units of sectors to the buffer memory. The control circuit controls the order and the number of times of inputting/outputting data between the buffer memory and the random data input/output circuit.

Abstract: A page access circuit of a semiconductor memory device is normally operated even when a page address toggles at any timing in a page mode. The page access circuit comprises an address buffer, a column control unit, a page control unit, a pre-active unit and a precharge unit. The column control unit is controlled by the page address control signal. The page control unit controlled by a sense detecting signal is adapted and configured to generate the page address control signal. The pre-active unit controlled by the page address control signal is adapted and configured to generate a mode identification signal in response to the page address transition detecting signal. The precharge unit is adapted and configured to perform a selective precharge operation in response to the mode identification signal.

Abstract: The present invention relates to a memory in integrated circuit comprising a central Flash-type memory comprising memory cells forming pages, a buffer memory capable of storing binary words, and a sequencer for executing an instruction for saving, in a target page of the Flash memory, a series of external words received at an input terminal of the memory. According to the present invention, the sequencer is arranged for, after saving the series of external words in the buffer memory, saving, in the buffer memory, internal words present in the target page and corresponding, due to their address in the page, to locations of words in the buffer memory that have not received any external words, then erasing the target page and saving in the erased page the words present in the buffer memory.

Abstract: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction.

Abstract: Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., ½ ¼, ?, or 1/16) of one or more selected memory banks comprising a cell array in a semiconductor memory device. In one aspect, a PASR operation is performed by (1) controlling the generation of row addresses by a row address counter during a self-refresh operation and (2) controlling a self-refresh cycle generating circuit to adjust the self-refresh cycle output therefrom. The self-refresh cycle is adjusted in a manner that provides a reduction in the current dissipation during the PASR operation. In another aspect, a PASR operation is performed by controlling one or more row addresses corresponding to a partial cell array during a self-refresh operation, whereby a reduction in a self-refresh current dissipation is achieved by blocking the activation of a non-used block of a memory bank.

Abstract: The present invention relates to a composite memory device comprising first through third memory devices, a memory bus, and first through third memory controllers. The first memory device is an asynchronous memory device, the second memory device is a synchronous memory device configured to operate in a page mode, and the third memory device is a synchronous memory device configured to operate in a burst mode. The first through the third memory controllers are configured to control data transfer operation between the memory bus and the first through the third memory devices, respectively. The first through the third memory devices are controlled by an external memory controller to exchange data with an external system bus, and when one of the first through the third memory devices exchanges data with the external system bus, the rest two memory devices are allowed to exchange data via the memory bus.

Abstract: A semiconductor memory device is provided, which comprises a memory array comprising a plurality of memory cells, a page buffer section for temporarily storing data to be written into the memory array, and a masking section for masking at least a portion of data read from the page buffer section.

Abstract: An integrated circuit memory includes a FLASH memory including a circuit for recording a word presented on its input without the possibility of recording simultaneously several words in parallel. The integrated circuit memory may include a buffer memory with a sufficient capacity to store a plurality of words, the output of which is coupled to the input of the FLASH memory. A circuit is also included for recording into the buffer memory a series of words to be recorded into the FLASH memory and recording into the FLASH memory the words first recorded into the buffer memory.

Abstract: The invention provides a method of programming in a nonvolatile semiconductor memory device, having a plurality of memory cell strings connected to a plurality of bitlines and constructed of a plurality of memory cell transistors whose gates are coupled to a plurality of wordlines, and a plurality of registers corresponding to the bitlines. The method involves applying a first voltage to a first one of the bitlines and applying a second voltage to a second one of the bitline, the first bitline being adjacent to the second bitline, the first and second voltages being supplied from the registers; electrically isolating the first and second bitlines from their corresponding registers; charging the first bitline up to a third voltage higher than the first voltage and lower than the second voltage; and applying a fourth voltage to a wordline after cutting off current paths into the first and second bitlines.

Abstract: An efficient invention for opening two pages of memory for a DRAM are discussed.

Abstract: A first address subset is allocated as a first column address in a nonvolatile semiconductor memory. In addition, a second address subset higher in order than the first address subset is allocated as a first row address. Furthermore, a third address subset higher in order than the second address subset is allocated as a second column address.