Abstract: An SPS CCD memory using two phase clocking in the serial registers and ripple clocking in the parallel registers with interlacing transfer of charge in the parallel registers to the output serial registers. First alternate parallel registers are coupled to the output register through first transfer gates and first storage gates, and second alternate parallel registers are coupled to the output register through second transfer gates and second storage gates. Third storage gates are provided with each third storage gate alternately receiving charge from a first storage gate and a second storage gate with the third gate delivering the charge to the same storage element of the output register. By linearly staggering the endmost gates of the first alternate parallel registers and the second alternate parallel registers, the interlacing of charge occurs at the endmost gate of the parallel registers.

Abstract: A recirculating loop memory array is disclosed adapted for the parallel as well as serial fetching and storing of data while requiring only a single input and single output data terminal. Each loop of the array is provided with a shift register stage for parallel data accessing. A particular recirculating bit in all of the loops can be fetched in parallel into their respective shift register stages and, conversely, the bits stored in the shift register stages can be loaded in parallel into predetermined recirculating bits of their respective loops. The shift register is operated at high speed so that it may be completely loaded or unloaded during the interval between successive steppings of the loops.

Abstract: A memory system for a data processing apparatus including a stack and a stack image memory which provides either sequential or simultaneous access to information contained on the stack. A stack control logic unit is responsive to a stack instruction so that information written into the stack is simultaneously written into one or more random access memory units. Moreover, a sequence of information items read sequentially from the stack may be read simultaneously from different random access memory units. The memory address unit is preferably implemented with programmable read-only memories.

Abstract: A serial-parallel converter for storing sequentially a serially input digital signal in a predetermined number of elements and producing the stored data at one time as a parallelly output digital signal. The serially input digital signal is sequentially written in memory cells having addresses designated by an address counter adapted to count the write-in timing pulses. Upon completion of the write-in operation to all the memory cells, contents stored in all the memory cells are read out at one time as a parallelly output signal.

Abstract: A semiconductor memory device, comprising N memory cell arrays each of which includes a plurality of memory cells, is arranged to enable the use of said semiconductor memory device in the form of both one-bit-per-word N-bits-per-word. Two separate sets of output gates are provided, together with an additional input line for selecting between the two sets of gates. One set of gates is connected to provide one-bit output, and the other set of gates is connected to provide N-bit output.

Abstract: Monolithically integrated semiconductor memory including memory cells disposed in parallel rows and parallel columns transverse to the rows, and electric lines connecting the memory cells of the respective rows and columns to one another, the memory cells individually being constructed as clock-controlled shift register cells.

Abstract: An SPS CCD memory system is provided wherein a single tap, preferably a storage node, on an input serial or shift register is connected to the input of a plurality of parallel shift registers through a fan out circuit and the output of the plurality of parallel shift registers is connected to a single tap, preferably a storage node, on an output serial or shift register through a fan in circuit.

Abstract: Two-dimensional analog memory monolithically integrated with insulated-gate field-effect transistors, operating on the charge-transfer, and more particularly on the bucket-brigade principle, for temporarily storing the signals originating with the two half pictures of a (TV) video signal.

Abstract: System for handling and distributing of data comprising a local ordering and memorizing center connected by a common line to a plurality of peripheral user equipments, wherein said peripheral user equipments are provided each with a memory unit adapted to receive and store all the information contained in the local memorizing center, the memory unit of the peripheral user equipment being arranged so as to allow its use independently upon the operation of the ordering center, means being provided for updating the information stored in the memory equipment of the peripheral users.

Abstract: A charge transfer memory has a read-in chain, and assigned parallel chain and a read-out chain, each consisting of charge transfer elements. An additional parallel chain of charge transfer elements stores bias charges which are fed into the read-in chain, after the transfer of information charges from the read-in chain into the parallel chain, before a renewed serial input of information charges into the read-in chain. The read-out chain has a circuit arrangement assigned thereto which fills the output chain with bias charges upon the serial read-out of charges which characterize the information. The read-out chain has assigned thereto a further parallel chain of charge transfer elements with which the bias charges are removed from the output chain before the renewed delivery of charges characterizing information from the parallel chain.

Abstract: Disclosed is an electronic data storage of the type wherein data is entered and read out serially. In a conventional serial-parallel-serial configuration, data is serially entered into an input register and then transferred and stored in parallel through the main section of the storage until data is transferred in parallel to the output register from which the data is read serially. In a conventional line-addressable configuration, data is entered into and read from columns of shift registers where each column is addressable. The disclosed array combines the conventional serial-parallel-serial and the line-addressable structures into one array. This permits serial data to be read one row at a time as well as one column at a time.

Abstract: Disclosed is an electronic data storage of the type wherein data is entered and read out serially. In a conventional serial-parallel-serial configuration, data is serially entered into an input register and then transferred and stored in parallel through the main section of the storage until data is transferred in parallel to the output register from which the data is read serially. In a conventional line-addressable configuration, data is entered into and read from columns of shift registers where each column is addressable. The disclosed array combines the conventional serial-parallel-serial and the line-addressable structures into one array. By utilizing three phase clock lines and an inhibit line for each cell, the disclosed structure can be fabricated with two levels of gate electrodes.

Abstract: A stored-program control system for a telephone exchange or the like comprises processing units coupled to several main memories and to several mass memories. Each mass memory includes one or more memory modules each with one or more rows of shift registers of the charge-coupled type, operating in a serial-parallel-serial mode, and a control module equipped with a self-correcting logic and a microprogrammed time base.

Abstract: A variable length delay line comprises a random-access-memory (RAM) device in which a selected shift between read and write addresses establishes the desired amount of delay.

Abstract: A memory array having improved cross coupled cells arranged in rows and columns and provided with means that permit the speedy direct transfer of data from one cell in the array into another cell in the array while simultaneously reading the data. Each of the cells is provided with a pair of read transistors and is coupled between a pair of bit sense lines. A different pair of bit sense lines is associated with each column of cells. Each cell is, in turn, provided with a pair of write transistors and is coupled between a pair of write lines. A different pair of write lines is associated with each column of cells in parallel to the bit sense lines. Read and write decodes are coupled to rows of cells arranged orthogonal to the columns of cells.

Abstract: A memory addressing device for a memory divided in a plurality of elements each storing a plurality of information words. Each address for the memory comprises a first part which controls addressing means which address all the words of the memory elements stored in the address identified by said first part. All the addressed words are stored in corresponding output registers of the memory elements. The second part of the address enables the selection of the output register associated therewith. Consequently the reading operation for a block of information requires only one memory access time plus the read time of the output registers.

Abstract: An organization of serial-parallel-serial (SPS) charged-coupled-device (CCD) memory arrays or blocks into a memory system is disclosed. Each memory block is comprised of an N-bit input register, an N-bit output register, N S-bit parallel registers and an N-bit I/O register. Data is bit-serially entered into the input register at a frequency F.sub.0 is bit-parallelly shifted through the parallel registers and simultaneously into the output register and the I/O register at a frequency F.sub.0 /N. Addressed read data are captured by the I/O register and are circulated continuously therein independently of the recirculation process performed by the output register, input register such that if I/O transfer rates are lower than the allowable refresh frequency of the charged-coupled-devices of the memory block, and if one or more refresh cycles are utilized, the addressed read data always remains available in the I/O register.

Abstract: A memory and control circuit for the memory with a memory including a first memory plane area having a plurality of memory cells arranged in a matrix array and a plurality of second memory plane areas each having a plurality of nonvolatile memory cells arranged in a matrix array, the first memory plane area being arranged in a superposed relation to the second memory plane area and the memory cell in the first memory plane area being connected to the corresponding memory cell in the second memory plane area; first control lines connected to the second memory plane areas; a first control circuit for selectively driving the control lines to energize the memory cells in the corresponding second memory plane area; a second control line connected to the first memory plane area; and a second control circuit adapted to selectively energize the memory cells of the first memory plane area through the second control line to permit data transfer between the selected memory cell in the first memory plane area and that co

Abstract: A memory apparatus comprises a plurality of memory cells each having a bistable circuit comprising a pair of field effect transistors, a pair of switching transistors connected between a power supply and each output terminal of said paired field effect transistors, and a plurality of pairs of variable threshold insulated gate field effect transistors connected in parallel with the pair of switching transistors, the variable threshold insulated gate field effect transistors in pair constituting a non-volatile memory cell element, and a plurality of gate control lines connected in common to the gates of the paired variable threshold insulated gate field effect transistors.

Abstract: A solid state imaging device capable of converting one-dimensional or two-dimensional optical information into an electrical signal is disclosed. A signal charge stored in each of a plurality of photo-electric converter elements, which is proportional to the amount of incident light, is read into a corresponding stage of a charge transfer device through a switching transistor under the control of a read control pulse. The read control pulse is applied through a clock line of the charge transfer device so that the clock line is used both for read-in and for transfer. In this manner, one picture element of the imaging device is constructed of one photo-cell and two transistors whereby a high integration density of the solid state imaging device is attained.

Abstract: The disclosed random access memory (RAM) for digital data includes the normal data input circuit, a memory matrix for storing applied data, address control circuits for selectively addressing any cell of the memory matrix, and a data output circuit for selectively applying digital data stored in the memory matrix to a data output line. To achieve a high digital data output rate, a rate substantially higher than the rate at which the cells of the memory can be addressed, the improved RAM includes a data output register having a multiplicity of data storage elements and means for simultaneously reading digital data stored in the memory matrix in parallel into the data storage elements of the output register. This data then is selectively applied to the data output line while new data is being addressed in the memory matrix.

Abstract: A storage arrangement for use with CCD storage devices, the storage area having an input shift register and an output shift register each of m bits. 2m shift registers, each of length n bits and constructed using the electrode-per-bit principle connect the input shift register to the output shift register. A circular shift register of length n bits being connected to the gate input of n switching transistors each of which is connected between a supply potential and one of n pulse train lines of the storage area. A circulating charge in the circular shift register is the means whereby each one of the n switching transistors cyclically connects one of the n pulse train lines to the supply potential.

Abstract: A memory system for analogue data includes a plurality of semiconductor charge device shift registers integrated on a semiconducor substrate. In one embodiment analogue data is serially inputed into a charge-coupled device (CCD) shift register. The serial data is converted to parallel and propagates at a substantially slower speed through a plurality of shift registers. A parallel-to-serial conversion provides a serial readout of the data. The serial-parallel-serial arrangement of the memory significantly reduces the number of transfers required to propagate one bit of data through the memory and provides correspondingly improved outputs. In a different aspect of the invention, a plurality of bits of digital data are transformed into a single analogue signal effecting a reduction in size of the memory for equal storage capability.