Abstract: A method, system, and apparatus magnetically coupled electrostatically shiftable memory device and method are disclosed. In one embodiment, a method includes electrostatically decoupling a separate structure and a surface that are magnetically coupled (e.g., an electrostatic force to decouple the separate structure and the surface is generated with an electrode), shifting the separate structure between the surface and a other surface with the electrostatic force (e.g., shifting the separate structure moves the entire separate structure), and magnetically coupling the separate structure to the other surface.

Abstract: The present invention provides a magnetic memory device capable of providing high-speed access without increasing an array area. Gate word lines are respectively linearly disposed between source impurity regions and drain impurity regions within a memory cell array area. Gate word line protrusions are respectively provided at boundary regions of memory cell forming regions. Contacts relative to the gate word line protrusions are respectively provided at boundary regions of memory cells at adjacent columns. The drain impurity regions are respectively disposed with being shifted from the centers of the memory cell forming regions in such a manner that spaces between the drain impurity regions become large in the regions in which the protrusions are disposed.

Abstract: A system includes a continuous thin-film ferromagnetic layer, N magnetic tunnel junction (MTJ) devices, and N write structures. The continuous thin-film ferromagnetic layer includes N modified regions. Each of the N modified regions is configured to stabilize a magnetic domain wall located in the continuous thin-film ferromagnetic layer. Each of the N MTJ devices includes one of N portions of the continuous thin-film ferromagnetic layer. Adjacent MTJ devices of the N MTJ devices are separated by one of the N modified regions. Each of the N write structures is configured to receive current and generate a magnetic field that magnetizes a different one of the N portions of the continuous thin-film ferromagnetic layer. N is an integer greater than 2.

Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element.

Abstract: A storage element includes a storage layer having a magnetization perpendicular to a layer surface and storing information according to a magnetization state of a magnetic material; a fixed magnetization layer having the magnetization as a reference of the information of the storage layer and perpendicular to the layer surface; an interlayer formed of a nonmagnetic material and interposed between the storage layer and the fixed magnetization layer; a coercive force enhancement layer adjacent to the storage layer, opposite to the interlayer, and formed of Cr, Ru, W, Si, or Mn; and a spin barrier layer formed of an oxide, adjacent to the coercive force enhancement layer, and opposite to the storage layer.

Abstract: A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.

Abstract: Provided are nonvolatile memory devices and program methods thereof, an integrated circuit memory system includes a memory array comprising at least one magnetic track, each of the at least one magnetic track including a plurality of magnetic domains and at least one read/write unit coupled thereto, decoding circuitry coupled to the memory array that is operable to select at least one of the magnetic domains, a read/write controller coupled to the memory array that is operable to read data from at least one of the plurality of magnetic domains and to write data to at least one of the plurality of magnetic domains via the at least one read/write unit coupled to each of the at least one magnetic track, and a domain controller coupled to memory array that is operable to move data between the magnetic domains on each of the at least one magnetic track.

Abstract: A magnetic device includes a magnetic reference layer with a fixed magnetization direction located either in the plane of the layer or perpendicular to the plane of the layer, a magnetic storage layer with a variable magnetization direction, a non-magnetic spacer separating the reference layer and the storage layer and a magnetic spin polarizing layer with a magnetization perpendicular to that of the reference layer, and located out of the plane of the spin polarizing layer if the magnetization of the reference layer is directed in the plane of the reference layer or in the plane of the spin polarizing layer if the magnetization of the reference layer is directed perpendicular to the plane of the reference layer. The spin transfer coefficient between the reference layer and the storage layer is higher than the spin transfer coefficient between the spin polarizing layer and the storage layer.

Abstract: A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each including a storage element and a switching element which are connected in series between adjacently paired ones of the bit lines. Gates of the switching elements of the memory cells connected between one of the adjacently paired ones of the bit lines are respectively connected to different ones of the word lines. A plurality of the storage elements and a plurality of the switching elements of the adjacent memory cells are alternately connected in series.

Abstract: A storage circuit includes a volatile storage portion in which storage of a data signal is controlled by a clock signal and an inverted clock signal, and a nonvolatile storage portion in which a data signal supplied to the volatile storage portion can be held even after supply of power supply voltage is stopped. A wiring which supplies a power supply voltage and is connected to a protective circuit provided for a wiring for supplying the clock signal is provided separately from a wiring which supplies a power supply voltage and which is connected to the storage circuit. The timing of stop and restart of supply of the power supply voltage supplied to the wiring which is connected to the protective circuit is different from that of stop and restart of supply of the power supply voltage supplied to the wiring which is connected to the storage circuit.

Abstract: To provide a magnetic memory device that can suppress the reduction of function of a magnetic memory element, and a manufacturing method thereof. A magnetic memory device includes a magnetic memory element capable of holding data based on a magnetized state thereof, and a digit line and a bit line which are capable of changing the magnetized state of the magnetic memory element by a magnetic field generated. The magnetic memory element is disposed above the digit line and the bit line at an intersection part of the digit line and the bit line. The digit line has a first width at the intersection part, and the bit line has a second width at the intersection part. The first width is larger than a third width of the magnetic memory element, and the second width is smaller than a fourth width of the magnetic memory element.

Abstract: A horizontally disposed elliptical or rectangular magnetic memory cell includes at least two conductive lines to carry current and a magnetic element disposed between the conductive lines. The current through the conductive lines induces a magnetic field, such that the magnetic element is directly accessible. The magnetic memory cell can be sensed with a GMR head.

Abstract: Apparatus and methods are disclosed that enable writing data on, and reading data of, multi-state elements having greater than two states. The elements may be made of magnetoplastic and/or magnetoelastic materials, including, for example, magnetic shape-memory alloy or other materials that couple magnetic and crystallographic states. The writing process is preferably conducted through the application of a magnetic field and/or a mechanical action. The reading process is preferably conducted through atomic-force microscopy, magnetic-force microscopy, spin-polarized electrons, magneto-optical Kerr effect, optical interferometry or other methods, or other methods/effects. The multifunctionality (crystallographic, magnetic, and shape states each representing a functionality) of the multi-state elements allows for simultaneous operations including read&write, sense&indicate, and sense&control.

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract: A memory is provided that simplifies a fabrication process and structure by reducing the number of source lines and bitlines accessible to circuitry outside of the memory array. The memory has first and second row groups comprising a plurality of memory elements each coupled to one each of a plurality of M bit lines; first and second local source lines and first and second word lines, each coupled to each of the plurality of memory elements; and circuitry coupled to the first and second word lines and configured to select one of the first and second row groups, and coupled to the plurality of M bit lines and configured to apply current of magnitude N through the memory element in the selected row group coupled to one of the plurality of M bit lines by applying current of magnitude less than N to two or more of the remaining M-1 bit lines.

Abstract: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.

Abstract: Spin torque magnetic logic devices that function as memory devices and that can be reconfigured or reprogrammed as desired. In some embodiments, the logic device is a single magnetic element, having a pinned layer, a free layer, and a barrier layer therebetween, or in other embodiments, the logic device has two magnetic elements in series. Two input currents can be applied through the element to configure or program the element. In use, logic input data, such as current, is passed through the programmed element, defining the resistance across the element and the resulting logic output. The magnetic logic device can be used for an all-function-in-one magnetic chip.

Abstract: A magnetic memory device includes a free layer and a guide layer on a substrate. An insulating layer is interposed between the free layer and the guide layer. At least one conductive bridge passes through the insulating layer and electrically connects the free layer and the guide layer. A diffusion barrier may be interposed between the guide layer and the insulating layer. The device may further include a reference layer having a fixed magnetization direction on a side of the free layer opposite the insulating layer and a tunnel barrier between the reference layer and the free layer. Related fabrication methods are also described.

Abstract: The present invention provides a magnetic memory device capable of providing high-speed access without increasing an array area. Gate word lines are respectively linearly disposed between source impurity regions and drain impurity regions within a memory cell array area. Gate word line protrusions are respectively provided at boundary regions of memory cell forming regions. Contacts relative to the gate word line protrusions are respectively provided at boundary regions of memory cells at adjacent columns. The drain impurity regions are respectively disposed with being shifted from the centers of the memory cell forming regions in such a manner that spaces between the drain impurity regions become large in the regions in which the protrusions are disposed.

Abstract: Spin torque magnetic integrated circuits and devices therefor are described. In an example, a spin torque magnetic device for a logic circuit includes a majority gate structure. An output is coupled to the majority gate structure. Three inputs are also coupled to the majority gate structure.

Abstract: Spin torque magnetic logic device having at least one input element and an output element. Current is applied through the input element(s), and the resulting resistance or voltage across the output element is measured. The input element(s) include a free layer and the output element includes a free layer that is electrically connected to the free layer of the input element. The free layers of the input element and the output element may be electrically connected via magnetostatic coupling, or may be physically coupled. In some embodiments, the output element may have more than one free layer.

Abstract: A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing a plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a magnetization pair detection sensor including a MTJ (Magnetic Tunnel Junction) or GMR (Giant Magnetoresistive) device, a magnetoresistive sensor including a MTJ device and a magnetic material (current line), a dielectric constant sensor including a sensing capacitor and a switching device, a magnetization hole detection sensor including a MTJ or GMR device, a current line, a free ferromagnetic layer and a switching device, and a giant magnetoresistive sensor including a GMR device, a switching device and a magnetic material (or forcing wordline).

Abstract: Systems and methods for realizing reference currents to improve reliability of sensing operations of segmented semiconductor memory arrays have been achieved. Preferred embodiments of the invention comprise MRAM arrays but the invention could be applied to any other memories requiring access on small, segmented arrays. All embodiments of the invention comprise a folded bit lines scheme, either in adjacent bit lines or in segment-to-segment folded bit lines. In two embodiments alternate strapping of Poly-Si Word Lines in every second segment is achieved by metal layer of Read Word Line and Write Select Line. An embodiment has stored 1 and 0 cells on both sides of a selected segment to be read.

Abstract: A method and system for providing a magnetic junction usable in a magnetic memory are described. The magnetic junction includes first and second pinned layers, first and second nonmagnetic spacer layers, and a free layer. The first pinned layer has a first pinned layer magnetic moment and is nonmagnetic layer-free. The first nonmagnetic spacer layer resides between the first pinned and free layers. The free layer resides between the first and second nonmagnetic spacer layers. The second pinned layer has a second pinned layer magnetic moment and is nonmagnetic layer-free. The second nonmagnetic spacer layer resides between the free and second pinned layers. The first and second pinned layer magnetic moments are antiferromagnetically coupled and self-pinned. The magnetic junction is configured to allow the free layer to be switched between stable magnetic states when a write current is passed through the magnetic junction.

Abstract: A heterostructure of multiferroics or magnetoelectrics (ME) was disclosed. The film has both ferromagnetic and ferroelectric properties, as well as magneto-optic (MO) and electro-optic (EO) properties. Oxide buffer layers were employed to allow grown a cracking-free heterostructure a solution coating method.

Abstract: A method for forming a magnetic tunnel junction (MTJ) for magnetic random access memory (MRAM) using two masks includes depositing over an interlevel dielectric layer containing an exposed first interconnect metallization, a first electrode, a fixed magnetization layer, a tunneling barrier layer, a free magnetization layer and a second electrode. An MTJ structure including the tunnel barrier layer, free layer and second electrode is defined above the first interconnect metallization by a first mask. A first passivation layer encapsulates the MTJ structure, leaving the second electrode exposed. A third electrode is deposited in contact with the second electrode. A second mask is used to pattern a larger structure including the third electrode, the first passivation layer, the fixed magnetization layer and the first electrode. A second dielectric passivation layer covers the etched plurality of layers, the first interlevel dielectric layer and the first interconnect metallization.

Abstract: At least one junction diode fabricated in standard CMOS logic processes can be used as program selectors for the memory cells that can be programmed based on the directions of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a resistive element coupled to the P terminal of the first diode and to the N terminal of a second diode. The diodes can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diodes. By applying a high voltage to a resistive element and switching the N terminal of the first diode to a low voltage while disabling the second diode, a current flows through the memory cell can change the resistance into one state. Similarly, by applying a low voltage to a resistive element and switching the P terminal of the second diode to a high voltage while disabling the first diode, a current flows through the memory cell can change the resistance into another state.

Abstract: A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell array is provided. The STT-MRAM array includes a STT-MRAM bit cell and an input net coupled to the STT-MRAM bit cell. The STT-MRAM array includes a pulse signal input pad and a buffer coupled between the pulse signal input pad and the input net. In an aspect, the input net is one of a bit line, a word line, and a source line.

Abstract: Spin torque magnetic integrated circuits and devices therefor are described. A spin torque magnetic integrated circuit includes a first free ferromagnetic layer disposed above a substrate. A non-magnetic layer is disposed above the first free ferromagnetic layer. A plurality of write pillars and a plurality of read pillars are included, each pillar disposed above the non-magnetic layer and including a fixed ferromagnetic layer.

Abstract: An information storage device includes a magnetic structure having a buffer track and a plurality of storage tracks connected to the buffer track. A write/read unit is disposed on the magnetic structure, and a plurality of switching devices are respectively connected to the buffer track, the plurality of storage tracks, and the write/read unit. The switching devices that are respectively connected to the buffer track and the storage tracks. The information storage device further includes a circuit configured to supply current to at least one of the magnetic structure and the write/read unit.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: In the data read operation, a memory cell and a dummy memory cell are respectively coupled to two bit lines of a selected bit line pair, a data read current is supplied. In the selected memory cell column, a read gate drives the respective voltages on a read data bus pair, according to the respective voltages on the bit lines. A data read circuit amplifies the voltage difference between the read data buses so as to output read data. The use of the read gate enables the read data buses to be disconnected from a data read current path. As a result, respective voltage changes on the bit lines are rapidly produced, and therefore, the data read speed can be increased.

Abstract: Each layer in the magnetic multilayer film is a closed ring or oval ring and the magnetic moment or flux of the ferromagnetic film in the magnetic unit is in close state either clockwise or counterclockwise. A metal core is put in the geometry center position in the close-shaped magnetic multilayer film. The cross section of the metal core is a corresponding circular or oval. A MRAM is made of the closed magnetic multilayer film with or without a metal core. The close-shaped magnetic multilayer film is formed by micro process method. The close-shaped magnetic multilayer film can be used broadly in a great variety of device that uses a magnetic multilayer film as the core, such as MRAM, magnetic bead in computer, magnetic sensitive sensor, magnetic logic device and spin transistor.

Abstract: A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions.

Abstract: An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets the other end of the selected bit line and the other end of the current return line to one and the other of a power supply voltage and a ground voltage in accordance with a level of write data via one of first and second data buses and an inverted data bus, respectively.

Abstract: Between the value of an electric current and the supply duration for which the electric current is supplied that cause magnetization reversal, there is the relation of monotonous decrease. This means that, as the supply duration is shortened, the threshold current value for causing the magnetization reversal is larger. Therefore, in terms of suppressing occurrence of read disturb, the read current supply duration may be shortened to increase the threshold value of the current causing the magnetization reversal and thereby ensure a sufficient read disturb margin. Therefore, the read current supply duration may be shortened relative to the write current supply duration ensure the read disturb margin and suppress occurrence of read disturb.

Abstract: Spin torque magnetic logic devices that function as memory devices and that can be reconfigured or reprogrammed as desired. In some embodiments, the logic device is a single magnetic element, having a pinned layer, a free layer, and a barrier layer therebetween, or in other embodiments, the logic device has two magnetic elements in series. Two input currents can be applied through the element to configure or program the element. In use, logic input data, such as current, is passed through the programmed element, defining the resistance across the element and the resulting logic output. The magnetic logic device can be used for an all-function-in-one magnetic chip.

Abstract: Spin torque magnetic logic device having at least one input element and an output element. Current is applied through the input element(s), and the resulting resistance or voltage across the output element is measured. The input element(s) include a free layer and the output element includes a free layer that is electrically connected to the free layer of the input element. The free layers of the input element and the output element may be electrically connected via magnetostatic coupling, or may be physically coupled. In some embodiments, the output element may have more than one free layer.

Abstract: A ferroelectric semiconductor storage device includes: a block having a plurality of ferroelectric memory cells connected in series, each of the plurality of ferroelectric memory cells including a ferroelectric capacitor and a transistor connected in parallel to both ends of the ferroelectric capacitor; a word line connected to each of the transistors; a selection transistor connected to one end of the block; a bit line connected to the selection transistor; and a plate line connected to the other end of the block. The number of ferroelectric memory cells connected in each block in the ferroelectric semiconductor storage device is odd.

Abstract: A ferromagnetic thin-film based digital memory having bit structures therein with a magnetic material film in which a magnetic property thereof is maintained below a critical temperature above which such magnetic property is not maintained, and may also have a plurality of word line structures each with heating sections located across from the magnetic material film in a corresponding one of the bit structures. These bit structures are sufficiently thermally isolated to allow selected currents in the adjacent word lines or in the bit structure, or both, to selectively heat the bit structure to approach the critical temperature. Such bit structures may have three magnetic material layers each with its own critical temperature for maintaining versus not maintaining a magnetic property thereof.

Abstract: A semiconductor memory device includes first to third resistive memory elements, a first transistor having a first gate electrode, first and second source/drain electrodes, the first source/drain electrode being connected to one terminal of the first resistive memory element, and the second source/drain electrode being connected to one terminal of the third resistive memory element, a second transistor having a second gate electrode, third and fourth source/drain electrodes, the third source/drain electrode being connected to one terminal of the second resistive memory element, and the fourth source/drain electrode being connected to one terminal of the third resistive memory element, a first bit line connected to the other terminal of the third resistive memory element, a second bit line connected to the other terminal of each of the first and second resistive memory elements, and first and second word lines connected to each of the first and second gate electrodes.

Abstract: A memory apparatus having at least one memory cell set comprising a first spin torque memory cell electrically connected in series to a second spin torque memory cell, with each spin torque memory cell configured to switch between a high resistance state and a low resistance state. The memory cell set itself is configured to switch between a high resistance state and a low resistance state. The memory apparatus also has at least one reference cell set comprising a third spin torque memory cell electrically connected in anti-series to a fourth spin torque memory cell, with each spin torque memory cell configured to switch between a high resistance state and a low resistance state. The reference cell set itself has a reference resistance that is a midpoint of the high resistance state and the low resistance state of the memory cell set.

Abstract: Embodiments of the present invention disclose an MRAM device having a plurality of magnetic memory cells grouped into words, and write conductors for carrying write currents to write to the memory cells, wherein at least some of the write conductors have a reduced cross-sectional area in the vicinity of a group of memory cells.

Abstract: A semiconductor memory device includes first to third wiring layers formed above a semiconductor substrate, extending in a first direction, and sequentially arranged in a second direction perpendicular to the first direction, a plurality of active areas formed in the semiconductor substrate, and extending in a direction oblique to the first direction, first and second selection transistors formed in each of the active areas, and sharing a source region electrically connected to the second wiring layer, a first magnetoresistive element having one terminal electrically connected to a drain region of the first selection transistor, and the other terminal electrically connected to the first wiring layer, and a second magnetoresistive element having one terminal electrically connected to a drain region of the second selection transistor, and the other terminal electrically connected to the third wiring layer.

Abstract: A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.

Abstract: Apparatus and methods are disclosed that enable writing data on, and reading data of, multi-state elements having greater than two states. The elements may be made of magnetoplastic and/or magnetoelastic materials, including, for example, magnetic shape-memory alloy or other materials that couple magnetic and crystallographic states. The writing process is preferably conducted through the application of a magnetic field and/or a mechanical action. The reading process is preferably conducted through atomic-force microscopy, magnetic-force microscopy, spin-polarized electrons, magneto-optical Kerr effect, optical interferometry or other methods, or other methods/effects. The multifunctionality (crystallographic, magnetic, and shape states each representing a functionality) of the multi-state elements allows for simultaneous operations including read&write, sense&indicate, and sense&control.

Abstract: Between the value of an electric current and the supply duration for which the electric current is supplied that cause magnetization reversal, there is the relation of monotonous decrease. This means that, as the supply duration is shortened, the threshold current value for causing the magnetization reversal is larger. Therefore, in terms of suppressing occurrence of read disturb, the read current supply duration may be shortened to increase the threshold value of the current causing the magnetization reversal and thereby ensure a sufficient read disturb margin. Therefore, the read current supply duration may be shortened relative to the write current supply duration ensure the read disturb margin and suppress occurrence of read disturb.

Abstract: A memory element including a memory layer that retains information based on a magnetization state of a magnetic material is provided. In the memory element, a magnetization pinned layer is provided for the memory layer through an intermediate layer, the intermediate layer is formed of an insulator, spin-polarized electrons are injected in a stacking direction to change a magnetization direction of the memory layer, so that information is recorded in the memory layer. Also, a ferromagnetic layer forming the memory layer has a magnetostriction constant of 1×10?5 or more.

Abstract: A magnetic memory is provided in which the margin between a write current and a read current can be reduced. A magnetic storage element includes: a first magnetic layer in which the direction of magnetization can be reversed; a second magnetic layer in which the direction of magnetization is fixed; and a non-magnetic layer which is interposed between the first and second magnetic layers. The write current and the read current are supplied to the magnetic storage element in the stacking direction thereof through a read-write line. Moreover, a bias line which can apply a bias magnetic field to the first magnetic layer during a reading operation is disposed in the vicinity of the magnetic storage element.

Abstract: The present subject matter allows non-orthogonal lines to be formed at the same thickness as the orthogonal lines so as to promote compact designs, to be formed with even line edges, and to be formed efficiently. Various method embodiments relate to forming a magnetic random access memory (MRAM) array. Various embodiments include forming a first wiring layer of approximately parallel conductors, a second wiring layer of approximately parallel conductors and a third wiring layer of approximately parallel conductors such that the first, second and third wiring layers cross at a number of intersections. At least one of the first, second and third wiring layers are formed so as to be non-orthogonal with respect to a remaining at least one of the first, second and third wiring layers. The method further includes forming a layer of magnetic storage elements proximately located to the intersections. Other aspects are provided herein.