Abstract: A semiconductor memory includes a first conductive layer including a first pair of bit lines coupled to a first bit cell and a second conductive layer including a second pair of bit lines coupled to the first bit cell. The first and second conductive layers are vertically separated from each other.

Abstract: A semiconductor memory device is provided which includes a sense amplifier, a bit line connected to a plurality of memory cells of a first memory block, a complementary bit line connected to a plurality of memory cells of a second memory block, a first switch configured to connect the bit line to the sense amplifier, and a second switch configured to connect the complementary bit line to the sense amplifier. The first switch is configured to electrically separate the bit line from the sense amplifier when the second memory block performs a refresh operation.

Abstract: A low-power programmable LSI that can perform configuration (dynamic configuration) at high speed and can quickly start is provided. The programmable LSI includes a plurality of logic elements and a memory element for storing configuration data to be input to the plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements in accordance with the configuration data stored in the configuration memory. The memory element is formed using a storage element including a transistor whose channel is formed in an oxide semiconductor layer and a node set in a floating state when the transistor is turned off.

Abstract: The present invention generally relates to the three-dimensional arrangement of memory cells. This 3D arrangement and orientation is made with macro cells that enable the programming, reading and/or querying of any memory cell in the 3D array without the need for overhead wiring or by utilizing a minimal amount of overhead wiring. The individual macro cells are electrically coupled together such that a single transistor on the substrate can be utilized to address multiple macro cells. In such an arrangement, all the auxiliary circuits for addressing memory elements are simplified thereby diminishing their integrated circuit area.

Abstract: A memory cell includes six transistors. The first and second P-type transistors have the sources coupled to a first voltage. The first and second N-type transistors have the drains coupled to drains of the first and second P-type transistors, respectively; the sources coupled to a second voltage; and the gates coupled to gates of the first and second P-type transistors, respectively. The third N-type transistor has the drain coupled to a write word line; the source coupled to drain of the first N-type transistor and gate of the second N-type transistor; and the gate coupled to a first write bit line. The fourth N-type transistor has the drain coupled to the write word line; the source coupled to drain of the second N-type transistor and gate of the first N-type transistor; and the gate coupled to a second write bit line. A memory cell array is also provided.

Abstract: A semiconductor device includes a plurality of word lines; a plurality of bit lines; and a plurality of bit line node contacts. The plurality of word lines extend in a first direction in or on a substrate. The plurality of bit lines crosses over the plurality of word lines. Each of the plurality of bit line node contacts connects a corresponding bit line to the substrate, and each of the plurality of bit line node contacts has a width substantially equal to a width of the corresponding bit line.

Abstract: The present technology includes a semiconductor memory device and a method of manufacturing the same. The semiconductor device includes insulation patterns and cell word lines alternately stacked on a substrate. A cell channel layer is formed through the insulation patterns and the cell word lines. A select channel layer is connected to the cell channel layer, and the select channel layer has a resistance higher than a resistance of the cell channel layer. A select line surrounds the select channel layer.

Abstract: A stacked memory device for a configurable bandwidth memory interface includes a first number of contact pads arranged in a pattern on a first surface of the memory device and a second number of contact pads arranged in the same pattern on a second surface. Each of the second contact pads may be electrically coupled to a corresponding contact pad on the first surface using a via. When the memory device is oriented in a first orientation and stacked in vertical alignment and electrical connection upon a second memory device having the same pattern of contact pads, each data signal of the memory bus is coupled to a corresponding data signal of both the memory devices. When the memory device is oriented in a second orientation, a given data signal of the memory bus is coupled to the corresponding data signal of only one of the memory devices.

Abstract: A non-volatile storage system is disclosed that includes a plurality of blocks of non-volatile storage elements, a plurality of word lines connected to the blocks of non-volatile storage elements such that each word line is connected to adjacent blocks of non-volatile storage elements, a plurality of bit lines connected to the blocks of non-volatile storage elements, multiple sets of word lines drivers such that each set of word line drivers is positioned between two adjacent blocks for driving word lines connected to the two adjacent blocks, global data lines, local data lines in selective communication with the bit lines, one or more selection circuits that selectively connect the global data lines to selected local data lines and connect unselected local data lines to one or more unselected bit line signals and control circuitry in communication with the one or more selection circuits and the global data lines.

Abstract: Methods and apparatus for providing single finFET and multiple finFET SRAM arrays on a single integrated circuit. A first single port SRAM array of a plurality of first bit cells is described, each first bit cell having a y pitch Y1 and an X pitch X1, the ratio of X1 to Y1 being greater than or equal to 2, each bit cell further having single fin finFET transistors to form a 6T SRAM cell and a first voltage control circuit; and a second single port SRAM array of a plurality of second bit cells, each second bit cell having a y pitch Y2 and an X pitch X2, the ratio of X2 to Y2 being greater than or equal to 3, each of the plurality of second bit cells comprising a 6T SRAM cell wherein the ratio of X2 to X1 is greater than about 1.1.

Abstract: A method is provided for programming a memory cell in a memory array. The memory cell includes a resistivity-switching layer of a metal oxide or nitride compound, and the metal oxide or nitride compound includes exactly one metal. The method includes programming the memory cell by changing the resistivity-switching layer from a first resistivity state to a second programmed resistivity state, wherein the second programmed resistivity state stores a data state of the memory cell. Numerous other aspects are provided.

Abstract: According to example embodiments of inventive concepts, a semiconductor memory devices includes: a plurality of memory blocks that each include a plurality of stack structures, global bit lines connected in common to the plurality of memory blocks, block selection lines configured to control electrical connect between the global bit lines and one of the plurality of memory blocks, and vertical selection lines configured to control electrical connected between the global bit lines and one of the plurality of stack structures. Each of the plurality of stack structures includes a plurality of local bit lines, first vertical word lines and second vertical word lines crossing first sidewalls and second sidewalls respectfully of the plurality of stack structures, first variable resistive elements between the plurality of stack structures and the first vertical word lines, and second variable resistive elements between the plurality of stack structures and the second vertical word lines.

Abstract: A device includes first and second regions including first and second amplifiers, respectively and a memory cell array region formed between the first and second regions and includes first and second conductive layers each extending in a first direction, and a plurality of first pillar elements arranged in line in the first direction on the first conductive layer, each of the first pillar elements being coupled to the first conductive layer at one end thereof, and the first pillar elements comprising a plurality of first elements and a second element, and a plurality of second pillar elements arranged in line in the first direction on the second conductive layer, each of the second pillar elements being coupled to the second conductive layer at one end thereof, and the second pillar elements comprising a plurality of third elements and a fourth element.

Abstract: A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline (“BL”) and the gate of the first FET being in signal communication with a write wordline (“WLw”), and the source of the gated diode being in signal communication with a read wordline (“WLr”).

Abstract: A data retention period of a memory circuit is lengthened, power consumption is reduced, and a circuit area is reduced. Further, the number of times written data can be read to one data writing operation is increased. A memory circuit has a first field-effect transistor, a second field-effect transistor, and a third field-effect transistor. A data signal is input to one of a source and a drain of the first field-effect transistor. A gate of the second field-effect transistor is electrically connected to the other of the source and the drain of the first field-effect transistor. One of a source and a drain of the third field-effect transistor is electrically connected to a source or a drain of the second field-effect transistor.

Abstract: A low-power programmable LSI that can perform configuration (dynamic configuration) at high speed and can quickly start is provided. The programmable LSI includes a plurality of logic elements and a memory element for storing configuration data to be input to the plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements in accordance with the configuration data stored in the configuration memory. The memory element is formed using a storage element including a transistor whose channel is formed in an oxide semiconductor layer and a node set in a floating state when the transistor is turned off.

Abstract: A non-volatile memory device includes an array of memory units, each having resistive memory cells and a local word line. Each memory cell has a first and a second end, the second ends are coupled to the local word line of the corresponding memory unit. Bit lines are provided, each coupled to the first end of each resistive memory cell. A plurality of select transistors is provided, each associated with one memory unit and having a drain terminal coupled to the local word line of the associated memory unit. First and second global word lines are provided, each coupled to a control terminal of at least one select transistor. First and second source lines are provided, each coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all resistive memory cells in one selected memory unit in a read operation.

Abstract: Memory cells adjacent to each other in a second direction are formed in a first p-type well region, a first n-type well region, and a second p-type well region arranged in a first direction. Each memory cell includes a first transfer transistor and a first driver transistor formed in the first p-type well region, a second transfer transistor and a second driver transistor formed in the second p-type well region, and first and second load transistors formed in the first n-type well region. In an SRAM, gate electrodes of the first and second transfer transistors of the memory cells adjacent to each other in the second direction are electrically connected to first and second word lines, respectively. The first and second word lines are electrically connected to the first and second p-type well regions, respectively.

Abstract: A circuit on an end column of a divided memory array is formed by a block selection transistor having the same shape as that of a memory cell transistor. As the pattern of the connecting section between the main bit line and the sub-bit line is made in the same shape as that of the memory cell, it is possible to realize a pattern uniformity and to eliminate the need for using memory array dummy patterns.

Abstract: Memory devices, memory arrays, and methods of operation of memory arrays with segmentation. Segmentation elements can scale with the memory cells, and may be uni-directional or bi-directional diodes. Biasing lines in the array allow biasing of selected and unselected select devices and segmentation elements with any desired bias, and may use biasing devices of the same construction as the segmentation elements.

Abstract: A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type.

Abstract: Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line; a reading circuit comparing a potential of a bit line and a reference potential; and a potential generating circuit generating the writing potential and the reference potential. One of the memory cells includes: a first transistor connected to the bit line and a source line; a second transistor connected to the first and second signal line; and a third transistor connected to the word line, bit line, and source line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor is connected to one of source and drain electrodes of the second transistor.

Abstract: According to various embodiments, a variable resistance memory element and memory element array that uses variable resistance changes includes a select device, such as an ovonic threshold switch. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element.

Abstract: The semiconductor device includes a memory cell including a first transistor including a first channel formation region, a first gate electrode, and first source and drain regions; a second transistor including a second channel formation region provided so as to overlap with at least part of either of the first source region or the first drain region, a second source electrode, a second drain electrode electrically connected to the first gate electrode, and a second gate electrode; and an insulating layer provided between the first transistor and the second transistor. In a period during which the second transistor needs in an off state, at least when a positive potential is supplied to the first source region or the first drain region, a negative potential is supplied to the second gate electrode.

Abstract: A semiconductor device includes a nonvolatile memory cell including a writing transistor including an oxide semiconductor, a reading transistor including a semiconductor material different from that of the writing transistor, and a capacitor. Data is written to the memory cell by turning on the writing transistor so that a potential is supplied to a node where a source electrode of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor so that a predetermined potential is held in the node. Data is read out from the memory cell by supplying a precharge potential to a bit line, stopping the supply of the potential to the bit line, and determining whether the potential of the bit line is kept at the precharge potential or decreased.

Abstract: An object of one embodiment of the present invention is to miniaturize a semiconductor device. Another object of one embodiment of the present invention is to reduce the area of a driver circuit of a semiconductor device including a memory element. A plurality of cells in which the positions of input terminals and output terminals are fixed is arranged in a first direction, wirings each of which is electrically connected to the input terminal or the output terminal of each cell are stacked over the plurality of cells, and the wirings extend in the same direction as the first direction in which the cells are arranged; thus, a semiconductor device in which a driver circuit is miniaturized is provided.

Abstract: A four transistor (4T) memory device is provided. The device includes a first cell transistor and a second cell transistor, the first and second cell transistors coupled to each other and defining latch circuitry having at least one multi-stable node. The device further includes a first access transistor and a second access transistor, the first and second access transistors coupling the at least one multi-stable node to at least one bit-line. In the device, each of the first and second cell transistors and each of the first and second access transistors is a unidirectional field effect transistor configured for conducting current in a first direction and to be insubstantially incapable of conducting current in a second direction.

Abstract: A semiconductor memory device includes a plurality of functional bit lines, at least one dummy bit line, and a dummy bit line selection unit. The at least one dummy bit line is adjacent to an outermost bit line of the functional bit lines. The dummy bit line selection unit activates the at least one dummy bit line in response to a selection control signal of one of the plurality of functional bit lines that is not adjacent to the at least one dummy bit line. The semiconductor memory device may ensure a photo margin, so that the pattern size of the functional bit lines can be made uniform.

Abstract: A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.

Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

Abstract: Provided is a stacked semiconductor device including n stacked chips. Each chip includes “j” corresponding upper and lower electrodes, wherein j is a minimal natural number greater than or equal to n/2, and an identification code generator including a single inverter connecting one of the j first upper electrode to a corresponding one of the j lower electrodes. The upper electrodes receive a previous identification code, rotate the previous identification code by a unit of 1 bit, and invert 1 bit of the rotated previous identification code to generate a current identification code. The current identification code is applied through the j lower electrodes and corresponding TSVs to communicate the current identification code to the upper adjacent chip.

Abstract: An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile semiconductor memories which do not require specific erasing operation and do not suffer from damages due to repeated writing operation. Furthermore, the semiconductor device is well adapted to store multivalued data. Manufacturing methods, application circuits and driving/reading methods are explained in details in the description.

Abstract: An object is to provide a semiconductor device in which lower power consumption is realized by lowering voltage for data writing without increase in types of power supply potentials. Another object is to provide a semiconductor device in which threshold voltage drop of a selection transistor is suppressed without increase in types of power supply potentials for data writing. A diode-connected transistor is electrically connected in series with a word line electrically connected to a gate of an n-channel selection transistor. A capacitor is provided between the word line and a bit line electrically connected to one of a source and a drain of the selection transistor; alternatively, the capacitance between the bit line and the word line is used. In data writing, the timing of selecting the word line is earlier than the timing of selecting the bit line.

Abstract: A device includes a first region including a plurality of first memory elements and a plurality of first vertical transistors, the first vertical transistors comprising a plurality of first selective transistors and a first switching transistor, each of the first selective transistors including an upper electrode coupled to a corresponding one of the first memory elements and a lower electrode, the first switching transistor including an upper electrode and a lower electrode coupled in common to the lower electrodes of the first selective transistors through a first signal line, a second region arranged to make a first line with the first region in a first direction and including a plurality of second memory elements and a plurality of second vertical transistors, the second vertical transistors comprising a plurality of second selective transistors and a second switching transistor, and a third region sandwiched between the first and the second regions.

Abstract: A semiconductor memory device includes: a first n-type transistor; a first p-type transistor; a first wiring layer having a first interconnecting portion for connecting a drain of the first n-type transistor and a drain of the first p-type transistor; and a second wiring layer having a first conductive portion electrically connected to the first interconnecting portion.

Abstract: Representative implementations of memory devices have transistors between memory cells of a memory device. Memory devices may be arranged in memory arrays. The use of transistors may include alternately providing electrical isolation or current paths between pairs or groups of memory cells in a memory array.

Abstract: A static random access memory (SRAM) cell having a dedicated read port separated from a write port comprises a first and a second bit-line placed in parallel forming a complimentary bit-line pair for the dedicated read port, a first and second metal line adjacently flanking in both side of and in parallel to the first bit-line, the first and second metal line being formed in the same metal layer as the first bit-line and having a first and second predetermined distance to the first bit-line, respectively, and a third and fourth metal line adjacently flanking in both side of and in parallel to the second bit-line, the third and fourth metal line being formed in the same metal layer as the second bit-line and having a third and fourth predetermined distance to the second bit-line, respectively, wherein the first predetermined distance is equal to the third distance and the second predetermined distance is equal to the fourth distance for keeping the first and second bit-lines having balanced capacitance loading

Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line.

Abstract: A system includes a plurality of memory devices arranged in a fly-by topology, each of the memory devices having on-die termination (ODT) circuitry for connection to an address and control (RQ) bus. The ODT circuitry has at least one input for controlling termination of one or more signal lines of the RQ bus. Application of a first logic level to the at least one input enables termination of the one or more signal lines. Application of a second logic level to the at least one input disables termination of the one or more signal lines.

Abstract: In a memory cell, a transistor with extremely high off-resistance is used as a write transistor; a drain and a source of the write transistor are connected to a write bit line and an input of an inverter, respectively; and a drain and a source of a read transistor are connected to a read bit line and an output of the inverter, respectively. Capacitors may be intentionally disposed to the source of the write transistor. Alternatively, parasitic capacitance may be used. Since the data retention is performed using charge stored on these capacitors, a potential difference between power sources for the inverter can be 0. This eliminates leakage current between the positive and negative electrodes of the inverter, thereby reducing power consumption.

Abstract: Provided are a non-volatile memory device and a cross-point memory array including the same which have a diode characteristic enabling the non-volatile memory device and the cross-point memory array including the same to operate in a simple structure, without requiring a switching device separately formed so as to embody a high density non-volatile memory device. The non-volatile memory device includes a first electrode; a diode-storage node formed on the first electrode; and a second electrode formed on the diode-storage node.

Abstract: To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an SRAM provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions. The first data holding portion is electrically connected to the fourth data holding portion through a transistor. The second data holding portion is electrically connected to the third data holding portion through a transistor. While the SRAM holds data, the transistor is on so that both the SRAM and the non-volatile memory hold the data. Then, the transistor is turned off before supply of power is stopped, so that the data becomes non-volatile.

Abstract: To provide a semiconductor device with high reliability in operation, in which data in a volatile memory can be saved to a non-volatile memory. For example, the semiconductor device includes an SRAM provided with first and second data storage portions and a non-volatile memory provided with third and fourth data storage portions. The first data storage portion is electrically connected to the fourth data storage portion through a transistor, and the second data storage portion is electrically connected to the third data storage portion through a transistor. The transistors are turned off when the SRAM operates, and the transistors are turned on when the SRAM does not operate, so that data in the SRAM is saved to the non-volatile memory. Precharge is performed when the SRAM is restored.

Abstract: A semiconductor device having hierarchical bit lines is disclosed, which comprises: a first global bit line; first and second local bit lines coupled in common to the first global bit line; first and second power lines; a first transistor coupled between the first local bit line and the first power line; a second transistor coupled between the second local bit line and the second power line; a third transistor coupled between the first and second power lines.

Abstract: According to an embodiment, a method of manufacturing a semiconductor device including a memory array provided on a substrate, and a control circuit provided on a surface of the substrate between the substrate and the memory array, includes steps of forming, in an insulating layer covering a p-type semiconductor region and an n-type semiconductor region of the control circuit, a first contact hole communicating with the p-type semiconductor region; forming a contact plug, in contact with the p-type semiconductor region, within the first contact hole; forming, in the insulating layer, a second contact hole communicating with the n-type semiconductor region; and forming an interconnection contacting the contact plug and the n-type semiconductor region exposed within the second contact hole.

Abstract: A memory cell 6 includes a M3 metal layer which incorporate continuous word lines 12 and power conductors formed of a plurality of separate power line sections 14 running parallel to the word lines. Interstitial gaps between the separate power line sections are larger in size than the power line sections themselves. The power line sections are disposed in a staggered arrangement either side of the word lines.

Abstract: Disclosed herein is a semiconductor device that includes a plurality of memory cells; a local bit line coupled to the memory cells; a global bit line; and a first switch circuit coupled between the global bit line and the local bit line, the first switch circuit electrically connecting the local bit line to the global bit line when at least one of first and second control signals is in an active state, and the first switch circuit electrically disconnecting the local bit line to the global bit line when both of the first and second control signals are in an inactive state.

Abstract: An SRAM-type memory cell that includes a semiconductor on insulator substrate having a thin film of semiconductor material separated from a base substrate by an insulating layer; and six transistors such as two access transistors, two conduction transistors and two charge transistors arranged so as to form with the conduction transistors two back-coupled inverters. Each of the transistors has a back control gate formed in the base substrate below the channel and able to be biased in order to modulate the threshold voltage of the transistor, with a first back gate line connecting the back control gates of the access transistors to a first potential and a second back gate line connecting the back control gates of the conduction transistors and charge transistors to a second potential. The first and second potentials can be modulated according to the type of cell control operation.

Abstract: A column of a memory includes a first edge cell and at least one memory cell. The first edge cell is located at a first edge of the column and includes a first edge cell reference node and a second edge cell reference node. Each of the at least one memory cells includes a first memory reference node. The first edge cell reference node is coupled to respective first memory reference nodes of the at least one memory cell. The second edge cell reference node serves as second memory reference nodes of the at least one memory cell. Front-end layers of the first edge cell are the same as front-end layers of a memory cell of the at least one memory cell.

Abstract: A vertical non-volatile memory device is structured/fabricated to include a substrate, groups of memory cell strings each having a plurality of memory transistors distributed vertically so that the memory throughout multiple layers on the substrate, integrated word lines coupled to sets of the memory transistors, respectively, and stacks of word select lines. The memory transistors of each set are those transistors, of one group of the memory cell strings, which are disposed in the same layer above the substrate. The word select lines are respectively connected to the integrated word lines.