Abstract: A drive circuit, for example a gate line drive circuit for a TFT liquid-crystal display, having a circuit size smaller than in the past. A TFT drive circuit has the shifting direction of drive data sequentially shifted through shift registers (SR116-R60) and is further inverted by a control signal (SEL_SFT), and the data are shifted in the opposite direction, from the first shift register (SR61) to the second shift register (SR116). At this time, the upper group of switching circuits (SW1-SW56) or the lower group of switching circuits (SW116-SW61) is enabled and the other group is disabled by control signals (SEL_UP, SEL_LO). Once the drive data are shifted to the bits of the shift registers, a voltage selection signal generated by a decoder (DEn) is inputted to an output circuit via an effective switching circuit, and a drive signal for a TFT gate is outputted. The number of circuits is reduced because the shift registers (SR61-SR116) and decoders (DE61-DE116) are shared by two outputs.

Abstract: Disclosed is a cross-tie wall memory system for the generating, propagating and detecting of binary data represented by the presence or absence of cross-tie, Bloch-line pairs along a cross-tie wall in a thin magnetic layer. The system includes a three-level structure comprised of the following superposed layers: a straight-edged current conductive stripline; a serrated-edged thin magnetic layer data track, and a wide-narrow-edged current conductive stripline terminated on one end by a cross-tie, Bloch-line pair generator and on the other end by a cross-tie detector.