Abstract: An electronic device includes an indicator that generates an indication of an event responsive to an indicator control signal from an indicator control circuit coupled between a processor and the indicator. The processor generates an indicator off-time value and an indicator on-time value when an indication is desired, and the indicator control circuit receives the indicator off-time value and the indictor on-time value from the processor. More particularly, the indicator control circuit includes an off-time register, an on-time register, and an indicator control circuit. The off-time register stores the off-time value generated by the processor, and the on-time register stores the on-time value generated by the processor.

Abstract: The present invention provides a byte-switching arithmetic unit comprising at least three stages, each of which has a plurality of two-input selectors operable in a predetermined minimum bit width unit, the byte-switching arithmetic unit having two inputs of a predetermined input bit width, wherein a first stage has a first number of first stage two-input selectors where the first number corresponds to a quotient of a division to the predetermined input bit width by the predetermined minimum bit width unit, wherein a second stage has a second number of second stage two-input selectors where the second number corresponds to a half of the first number so that the second stage two-input selectors receive a half of outputs from the first stage two-input selectors, and wherein a third stage has a third number of third stage two-input selectors where the third number also corresponds to the half of the first number so that the third stage two-input selectors receive both a half of outputs from the second stage two-

Abstract: An image communication apparatus capable of a parallel processing of image storage and transmission is provided with a memory device for storing a criterion value for a remaining storage capacity of an image storage device. A control device determines if the remaining storage capacity of the image storage device is larger than the criterion value, and the parallel storage and transmission processing is executed only when the remaining storage capacity is larger than the criterion value.

Abstract: The present invention allows for the simultaneous transmission of two digital signals from one integrated circuit to another. The two digital signals are encoded utilizing a voltage divider circuit and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded digital signal to further decode the second digital signal.