Abstract: A method for tuning an analog front end response is provided. The method includes determining a peaking control value for an analog front end (AFE) of a receiver, determining an attribute corresponding to the peaking control value, selecting the peaking control value as the operating peaking control value for the AFE based on the attribute being determined to be higher than a previous attribute, and performing a receiver adaptation using the peaking control for a one or more transmitter configurations.

Abstract: Methods and apparatus are disclosed to determine a power state of a device. An example apparatus includes a chart generator to determine respective counts for a plurality of measurements during a calibration period, the measurements indicative of an amount of power drawn by the device, a calculator to determine a first threshold and a second threshold based on at least one of the counts, the first threshold determined using most frequently logged measurement values, the most frequently logged measurement values based on counts performed after expiration of the calibration period, and a comparator to compare a measurement to the first threshold and to the second threshold.

Abstract: An operation method is implemented by a receiver device. The operation method includes following steps: detecting a signal on a transmission line; performing a channel estimation to acquire a length of the transmission line; comparing the length with at least one length threshold value to generate a comparison result; and adjusting a depth of a FIFO process according to the comparison result.

Abstract: Various embodiments provide a data sampling circuit comprising a first sampling module configured to respond to a signal from the data signal terminal and a signal from the reference signal terminal and to act on the first node and the second node; a second sampling module configured to respond to the signal from the first node and the signal from the second node and to act on the third node and the fourth node; a latch module configured to input a high level to the first output terminal and input a low level to the second output terminal; and an offset compensation module connected in parallel to the second sampling module and configured to compensate an offset voltage of the second sampling module.

Abstract: Methods and systems are disclosed for using a common frequency spectrum for simultaneous upstream and downstream communications in a network by implementing directional diversity techniques. Non-reciprocal coupling devices, such as circulators, may be configured in the network to provide unidirectional transmission of each signal to prevent interference. In some embodiments, feed-forward interference cancellation is utilized to increase signal isolation of upstream and downstream signals.

Abstract: A wireless signal interference reduction device includes a digital signal converter, an output device, a first adjustable resistor, and a second adjustable resistor. The wireless signal interference reduction device records an initial SNR value, records an SNR value of wireless reception in real-time at a preset interval when wired data transmission is turned on, determines whether a difference between the initial SNR value and the real-time SNR value is less than a preset value, continuously obtains the real-time SNR value at the preset interval to obtain the difference between the initial SNR value and the real-time SNR value if the difference between the initial SNR value and the real-time SNR value is less than the preset value, and reduces the wired transmission bandwidth by one step value if the difference between the initial SNR value and the real-time SNR value is not less than the preset value.

Abstract: An electronic circuit receives transmission signals from three or more communication lines. The electronic circuit includes a clock-data recovery circuit and a control value generation circuit. The clock-data recovery circuit outputs a recovered clock based on a transition generated in reception signals. The clock-data recovery circuit outputs recovered signals based on the recovered clock and the reception signals. The recovered clock has a first edge in response to the transition generated in the reception signals. The recovered clock has a second edge in response to a reset signal generated based on a delay of the recovered clock. The delay of the recovered clock is adjusted based on a control value provided from the control value generation circuit. The control value is adjusted based on change of a communication condition.

Abstract: For each unit transmission block having a pixel data block including at least one pixel data piece, clock data is added contiguously to a head of the pixel data block. If no data transition has occurred at a boundary between the clock data and the pixel data block, logic inversion is performed on the pixel data piece. Thereafter, a transmission image data signal in which unit transmission blocks, each constituted by adding an inversion flag immediately before the clock data, are consecutively arranged is transmitted to a display panel driver. The driver generates a clock signal on the basis of the clock data included in the received signal and takes in the pixel data piece or the resultant obtained by inverting the logic level of this pixel data piece in accordance with the clock signal on the basis of the inversion flag.

Abstract: The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for regulating a voltage for a high speed serializer/deserializer (SerDes) device. But it will be recognized that the technique can be used for regulating memory devices (e.g., DDR 4 SDRAM devices, DDR4 register devices, DDR4 controller devices), and other high speed data applications. In various embodiments, phase-interpolator is implemented in conjunction with a delay-lock loop (DLL) and an SR latch, where one or more outputs of the DLL is used by the SR latch. Additionally, such techniques can be used for a variety of applications such as network and/or computer storage systems, computer servers, hand held computing devices, portable computing devices, computer systems, network appliances and/or switches, routers, and gateways, and the like.

Abstract: The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for regulating a voltage for a high speed serializer/deserializer (SerDes) device. But it will be recognized that the technique can be used for regulating memory devices (e.g., DDR 4 SDRAM devices, DDR4 register devices, DDR4 controller devices), and other high speed data applications. In various embodiments, phase-interpolator is implemented in conjunction with a delay-lock loop (DLL) and an SR latch, where one or more outputs of the DLL is used by the SR latch. Additionally, such techniques can be used for a variety of applications such as network and/or computer storage systems, computer servers, hand held computing devices, portable computing devices, computer systems, network appliances and/or switches, routers, and gateways, and the like.

Abstract: Methods and systems for amplitude estimation and gain adjustment using noise as a reference are described. An example receiver can include an antenna and a front end amplifier coupled to the antenna. The receiver can also include a detector circuit coupled to the front end amplifier. The receiver can be configured to determine a power of a received signal at the antenna based on a gain of the receiver. The gain of the receiver can be determined based on a noise figure of the front end amplifier and a noise amplitude.

Abstract: An 8.1 nJ/bit 2.4 GHz receiver with integrated digital baseband supporting Q-QPSK DSSS modulation compliant with the IEEE 802.15.4 standard is presented that targets short-range, Internet of Things applications (IoTs). The sensitivity of a wireless communication receiver in general trades with power consumption. This receiver exploits this tradeoff to achieve a total power consumption of 2.02 mW including ADCs and digital baseband processing, at a sensitivity of ?52.5 dBm at 250 Kbps. The energy-efficiency of the radio frequency (RF) front-end alone is nearly two times better than the prior art. The receiver was fabricated in 65 nm CMOS with an area of 0.86 mm2.

Abstract: Methods and systems for amplitude estimation and gain adjustment using noise as a reference are described. An example receiver can include an antenna and a front end amplifier coupled to the antenna. The receiver can also include a detector circuit coupled to the front end amplifier. The receiver can be configured to determine a power of a received signal at the antenna based on a gain of the receiver. The gain of the receiver can be determined based on a noise figure of the front end amplifier and a noise amplitude.

Abstract: A system includes a full-duplex driver to drive signals on a load. A hybrid element connected with the full-duplex driver controls a flow of transmission and receipt of the signals. A gain control element connected with the full-duplex driver tunes a transconductance of the full-duplex driver to match an impedance of the load. The controlled gain is based on a leakage voltage value of the full-duplex driver.

Abstract: An integrated duplexer based on electrical balance is described. The duplexer module includes a hybrid transformer. The hybrid transformer includes a primary coil and a secondary coil. The primary coil is coupled between an output of a power amplifier and an antenna. The secondary coil is coupled between an input of a low noise amplifier and ground. The duplexer also includes a balancing impedance that is coupled between the primary coil and the secondary coil.

Abstract: An Ethernet cable connection system is disclosed. The system includes a magnetic package having a line interface to couple to a plurality of Ethernet line conductors, and a PHY interface to couple to a plurality of transceiver circuits corresponding to the line conductors. The magnetic package is operable to isolate the line conductors from the corresponding transceiver circuits. The system also includes a termination impedance network and a common-mode detection circuit. The termination impedance network is coupled to the magnetic package line interface. The common-mode detection circuit includes a sense impedance coupled to the termination impedance network that is operable to detect a common-mode signal associated with at least one of the plurality of Ethernet line conductors. A bypass path feeds the detected common-mode signal to the plurality of transceiver circuits without isolation by the magnetic package.

Abstract: A high and low speed serial interface multiplexing circuit includes a low speed transceiver, a high speed transceiver, an inductor coupled to a communication interface port of the low speed transceiver, a capacitor coupled to a communication interface port of the high speed transceiver, and a transformer coupled to the communication interface port of the high speed transceiver.

Abstract: A packet based display interface arranged to couple a multimedia source device to a multimedia sink device is disclosed that includes a transmitter unit coupled to the source device arranged to receive a source packet data stream in accordance with a native stream rate, a receiver unit coupled to the sink device, and a linking unit coupling the transmitter unit and the receiver unit arranged to transfer a multimedia data packet stream formed of a number of multimedia data packets based upon the source packet data stream in accordance with a link rate between the transmitter unit and the receiver unit.

Abstract: A new design configuration of an RF-transceiver front end is proposed. The Power Amplifier (PA) output stage of the transceiver comprises a cascode circuitry of N-type transistors with open-drain-configuration. The cascode-transistor is acting as a common-gate-transistor, whose gate is controlled to block the transmitting-(TX) path. The Low Noise Amplifier (LNA) input stage uses a common-gate configuration of a p-channel MOS-transistor that is controlled by the voltage at the bulk terminal. Lifting the bulk potential of this PMOS-transistor above its source potential disables the receiving-(RX)-path. This design allows low cost implementation for TDMA-RF-transceivers especially for Bluetooth-Solutions. The number of external components is reduced. No additional TX/RX switch is required. The same port and the same matching elements for the antenna's bandwidth adaptation are used for both the TX-path and the RX-path.

Abstract: An RF (radio frequency) signal is generated at a first communication device and is modulated. A second RF signal provided to the first communication device from the second communication device is demodulated. The second RF signal is detected. The generating is actuated to initiate an active or a passive mode communication, when the detecting does not detect the second RF signal at a level of a first threshold or more, the active mode including a transmission of modulated data at the first communication device and the second communication device, the passive mode providing load modulated communication from the second communication device to the first communication device. When the first communication device receives an indication to start a communication of the active mode from the second communication device, the demodulating receives data at a level of a second threshold or higher, the second threshold being higher than the first threshold.

Abstract: A circuit for serializing bits including a clock circuit and a serializer. The clock circuit may be configured to generate a plurality of clock signals from a received master clock signal. A plurality of bits may be transmitted to the serializer in response to a transition of a first clock signal. The serializer may comprise a system of latches and a rotary circuit. The system of latches may be configured to receive a first half of the plurality of bits in response to a first transition of a second clock signal and to receive a second half of the plurality of bits in response to a transition of a third clock signal. The rotary circuit may be configured to receive the plurality of bits from the system of latches and to output each bit at a particular time based on a plurality of rotary clock signals.

Abstract: Aspects of a method and system for symmetric transmit and receive latencies in an energy efficient PHY are provided. In this regard, a delay introduced by a PHY of a network device for outbound traffic and a delay introduced by the PHY for inbound traffic may be controlled such that a transmit delay of the network device is equal, within a tolerance, to a receive latency of the network device. The delays may be controlled based on whether one or more energy efficiency features are enabled in the PHY. The delay introduced by the PHY for outbound traffic may be controlled based on an amount of buffered inbound traffic. The delay introduced by the PHY for inbound traffic may be controlled based on an amount of buffered outbound traffic. The delays may be controlled such that said receive latency and the transmit latency are approximately constant regardless of a mode of operation of the network device.

Abstract: Hybrid frequency compensation is provided. Hybrid circuits are used to subtract the transmit signal from the receive signal in a full duplex communication system. Since the hybrid circuit and the main line driver are exposed to different loads, accurate subtraction is difficult to achieve. A frequency dependent network is used to match the loading seen by the driver and the hybrid. The compensation network can be based on active and/or passive components.

Abstract: A bidirectional communications interface is provided that connects a transmitter and a receiver, or a transceiver, to a transmission line. Under an embodiment, the bidirectional interface generates positive and negative polarity data signals using two separate differential amplifiers that receive differential signal pairs from each side of a differential link to the transmission line and the transmitter. The bidirectional interface controls common mode rejection in each of the separate differential amplifiers using bias signals generated in response to an output common mode feedback voltage from each of the differential amplifiers. An output amplifier combines the positive and negative polarity data signals to form single-ended output logic signals. The output logic signals represent data received on the transmission line, and are provided to the receiver.

Abstract: A wireless receiver generates quadrature baseband signals which are sampled by a high speed analog to digital converter (IQ ADC) and also uses a receive signal strength indicator (RSSI) which is sampled by an RSSI analog to digital converter (RSSI ADC). The RSSI ADC signal is processed in combination with an end of packet signal to generate a first threshold from the average RSSI signal after the end of packet with the receive amplifiers set to a comparatively high level. A second threshold is generated by adding a threshold increment to the first threshold, and when the RSSI crosses the second threshold, the IQ ADC is taken out of a standby mode and placed in an active mode for the duration of the packet. The RSSI ADC is enabled from end of packet until packet detection by the baseband processor, and placed in standby at other times.

Abstract: An adaptive electronic transmission signal cancellation circuit for separating transmit data from receive data in a bidirectional communication system operating in full duplex mode is disclosed. The output of a main transmitter responsive to a first bias current is connected to the output of a receiver through an internal resistor. A first replica transmitter responsive to a second bias current and matched to the main transmitter current gain and rise/fall time characteristics is connected to the input terminal of the receiver, and produces a cancellation voltage between the output terminal of the main transmitter and the input terminal of the receiver as a function of the second bias current and the internal resistor.

Abstract: A relatively low frequency signal—e.g. RS-232—is coupled to and extracted from a communication link that carries both a high frequency continuous signal and burst mode signal having bursts occurring at one or more frequencies—e.g. SAS with OOB signaling. The communication link has a differential coupling which differentially couples onto a first pair of conductors a continuous signal at a continuous rate and a burst mode signal having bursts occurring at one or more frequencies. The communication link also has a common mode coupling which common mode couples a second signal onto the first pair of conductors. A high pass filter coupled to the first pair of conductors extracts the continuous signal and the burst mode signal from the first pair of conductors. A low pass filter coupled to the first pair of conductors extracts the second signal from the first pair of conductors.

Abstract: A time shared bi-directional serial signaling system providing a differential signal with apparent duplex signal operation for higher and lower bandwidth data signals in a forward direction and another lower bandwidth data signal in a return direction.

Abstract: A data sampler including a first stage and a second stage. The first stage is configured to receive differential signals and provide a first edge rate in a first output signal and a second edge rate in a second output signal based on the differential signals. The second stage is configured to amplify the difference between the first output signal and the second output signal to provide regenerated output signals. The second stage provides a third edge rate in a first internal signal and a fourth edge rate in a second internal signal based on the first edge rate and the second edge rate.

Abstract: A predistorter for reducing spurious emissions in an amplified signal including a first path configured to generated memory-less distortion correction and one or more second paths configured to generate memory distortion correction. The paths contain one or more dynamically controllable delay circuits that are configured such that the memory-less and memory distortion correction remains independent irrespective of frequency of use of the predistorter.

Abstract: A bidirectional communications interface is provided that connects a transmitter and a receiver, or a transceiver, to a transmission line. Under an embodiment, the bidirectional interface generates positive and negative polarity data signals using two separate differential amplifiers that receive differential signal pairs from each side of a differential link to the transmission line and the transmitter. The bidirectional interface controls common mode rejection in each of the separate differential amplifiers using bias signals generated in response to an output common mode feedback voltage from each of the differential amplifiers. An output amplifier combines the positive and negative polarity data signals to form single-ended output logic signals. The output logic signals represent data received on the transmission line, and are provided to the receiver.

Abstract: A time shared bi-directional serial signaling system providing a differential signal with apparent duplex signal operation for higher and lower bandwidth data signals in a forward direction and another lower bandwidth data signal in a return direction.

Abstract: An acoustic resonator and a communication device with an acoustic resonator are described.

Abstract: Systems and methods for extended reach low differential latency optical networking with optical amplifiers and dispersion compensation modules configured to minimize latency between transmit and receive paths are provided. Additionally, systems and methods are provided for incorporating absolute time references wherein the relative accuracy of clock time between various servers used in various multi-site enterprises is required. The transport systems and methods are used in conjunction with low differential latency systems. The transport systems and methods provide that the differential latency between transmit and receive directions is maintained within about +/?5 microseconds of the transmit/receive path differential delay requirement in order to perform within the overall parameters of the low differential latency system architecture.

Abstract: Systems and methods for serial data transmission having at least two different operating modes dependent on the connected signaling device. For instance, one exemplary method involves monitoring at least one line of an interface comprising at least four differential data line pairs, detecting signals indicative of the presence of a connected device at the interface, selecting one of a predefined set of operating modes dependent on detected signals on the monitored line(s), and receiving and/or transmitting signals on at least one of the differential data line pairs, where the received signals and/or signals to be transmitted are processed in combination or independently for each data line pair, dependent on the selected operating mode.

Abstract: An apparatus comprises a transmitter, a receiver, an antenna and a signal cancellation circuit. The transmitter is configured to send a transmitter signal associated with a frequency. The receiver is associated with the frequency. The antenna is coupled to the transmitter and the receiver. The signal cancellation circuit is coupled to the transmitter, the receiver and the antenna. The signal cancellation circuit is configured to phase shift a first portion of the transmitter signal to produce a phase-shifted signal. The signal cancellation circuit is configured to combine the phase-shifted signal with a second portion of the transmitter signal to produce a combined signal. The second portion of the transmitter signal is associated with a reflection of a third portion of the transmitter signal from the antenna. The first portion, the second portion and the third portion of the transmitter signal are different from each other.

Abstract: In various exemplary embodiments, the present invention provides transport systems and methods incorporating absolute time references, such as global positioning system (GPS) time references and/or the like, and selective buildout delays, such as first-in, first-out (FIFO) buildout delays and/or the like. In one exemplary embodiment, the transport systems and methods of the present invention are used in conjunction with the International Business Machine Corporation (IBM) Geographically-Dispersed Parallel Sysplex (GDPS) integrated, automated application and data availability solution to meet and/or exceed the associated 10 microseconds transmit/receive path differential delay requirement. Other comparable uses are also contemplated herein, as will be obvious to those of ordinary skill in the art.

Abstract: The invention is directed to techniques for discovering a powerability condition of a computer network such as the existence of a remotely powerable device attached to a connecting medium of the computer network. Such detection can then control whether a remote power source (e.g., a data communications device such as a switch) provides remote power (e.g., phantom power) to the computer network. One arrangement of the invention is directed to an apparatus for discovering a powerability condition of a computer network. The apparatus includes a signal generator, a detector and a controller which is coupled to the signal generator and the detector. The controller configures the signal generator to provide a test signal to a connecting medium of the computer network, and configures the detector to measure a response signal from the connecting medium of the computer network.

Abstract: A bidirectional communications interface is provided that connects a transmitter and a receiver, or a transceiver, to a transmission line. Under an embodiment, the bidirectional interface generates positive and negative polarity data signals using two separate differential amplifiers that receive differential signal pairs from each side of a differential link to the transmission line and the transmitter. The bidirectional interface controls common mode rejection in each of the separate differential amplifiers using bias signals generated in response to an output common mode feedback voltage from each of the differential amplifiers. An output amplifier combines the positive and negative polarity data signals to form single-ended output logic signals. The output logic signals represent data received on the transmission line, and are provided to the receiver.

Abstract: A system generally having a first circuit, a second circuit, and a pair of non-crossing conductive paths. The first circuit may be configured to convert between (i) a serial signal on a first differential interface and (ii) a parallel signal. The pair of non-crossing conductive paths may connect the first differential interface with a second differential interface. The second circuit may be configured to invert the parallel signal in response to a control signal in an inverting state.

Abstract: A serial link circuit includes a transmitter which multiplexes the circuit's input signals together and uses a single processing circuit to generate a multiplexed output to be transmitted. The multiplexing is done with a limited voltage swing prior to preamplification. In this way, clock loading (and hence clock buffer area), power and jitter are significantly reduced. The complementary link receiver includes a demultiplexer implemented with sense amplifiers that are digitally unbalanced using trimmer capacitors to cancel the receiver's offset voltage. This allows the receiver to be implemented using very small elements to save power, and enables the link to operate reliably with a very low signal swing.

Abstract: In an electronic system having logic agents that communicate with each other through one or more signal lines, a method for testing high speed digital signaling on the signal lines is disclosed. The method involves sensing a first crosstalk signal induced by a first digital signal. The first digital signal is driven by a first logic agent into a signal line to communicate with a second agent. The second agent is coupled to receive the first digital signal from the signal line. A logic waveform that represents the digital signal is recorded and/or displayed, based upon the crosstalk signal. The technique may also be used for testing simultaneous bidirectional signaling on the same signal line.

Abstract: A simultaneous bidirectional port circuit includes a current mode output driver for driving an output node and a current mode return driver for driving a differential receiver. Variable impedance termination devices are included to provide terminations for both the current mode output driver and current mode return driver. A control circuit and method set the impedance value of the variable impedance termination devices by comparing voltage values at the output of the current mode output driver and current mode return driver.

Abstract: A system for ink short protection for signaling to inkjet printheads includes a differential signaling driver having a first and a second terminal, a differential signaling receiver having a first and a second terminal, a first capacitor in series between the first terminals, a second capacitor in series between the second terminals, and circuitry for reducing charge accumulation on the capacitors. A method for ink short protection and a printing mechanism having such an ink short protection system are also provided.

Abstract: A first comparator makes a comparison between potentials on paired signal lines connected with the secondary winding of a transformer to produce a signal indicating whether data of a first value has been received or not. A second comparator makes a comparison between potentials on the paired signal lines to output a signal indicating whether data of a second value has been received or not. A first detector samples the output signal of the first comparator at regular sampling intervals to produce a signal indicating whether an output signal indicating the reception of data of the first value has been produced from the first comparator. A second detector samples the output signal of the second comparator at the regular sampling intervals to produce a signal indicating whether an output signal indicating the reception of data of the second value has been produced from the second comparator.

Abstract: An arrangement for implementing a network in an ISDN-BASED customer premises having a 4-wire ISDN S0 bus. The ISDN-BASED customer premises includes a Network Termination Basic Access (NTBA) that interfaces between the residential customer premises and the public switched telephone network by mapping the 2-wire ISDN signal onto the 4-wire bus. A low pass filter is added to the 2-wire send path to eliminate high frequency noise caused by harmonic reflections of the ISDN-based signals on the 4-wire bus. The filter also provides a delay between the zero crossing of the ISDN-based signals and the transmitted network signals, minimizing the effect of the ISDN zero crossings on the home network signal.

Abstract: A system for ink short protection for signaling to inkjet printheads includes a differential signaling driver having a first and a second terminal, a differential signaling receiver having a first and a second terminal, a first capacitor in series between the first terminals, a second capacitor in series between the second terminals, and circuitry for reducing charge accumulation on the capacitors. A method for ink short protection and a printing mechanism having such an ink short protection system are also provided.

Abstract: The present invention provides a method of controlling a call between nodes in a distributed node exchange network having interconnections of plural exchanges, wherein a distributed node has a channel switch, a subscriber circuit, a trunk circuit accommodating local lines and private lines and a processor for controlling a call of the nodes. In a case of connections between the nodes, the node call control processor accommodating call extension lines and the other node call control processor accommodating receiving extension line in correspondence to the call extension lines carry out distributed processings of the call control for providing substantially the same connection services as the interconnection in the node.

Abstract: A receiver for bidirectional signal transmission, where signals are sent and received in both directions over a signal transmission line, has a signal line, a first hold capacitor, a signal line voltage buffer circuit, a hybrid circuit, and a decision circuit. The signal line is connected to the signal transmission line, the first hold capacitor is used to hold a signal, and the signal line voltage buffer circuit is used to buffer a voltage of the signal line. Further, the hybrid circuit is used to output a received signal by separating the received signal from the signal line voltage buffered by the buffer circuit, and the decision circuit is used to make a decision on the logic value of the received signal separated and output by the hybrid circuit.

Abstract: The system preferably includes a unique transmitter that sends both clock and data signals over the same transmission line. The receiver uses the same transmission line to send data signals back to the transmitter. The transmitter comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge. The falling edge position is decoded by the receiver to extract data from the clock signal. The receiver comprises a clock re-generator, a data decoder and a return channel encoder. The clock re-generator monitors the transmission line, receives signals, filters them and generates a clock signal at the receiver from the signal on the transmission line. The return channel encoder generates signals and asserts them on the transmission line. The signal is asserted or superimposed over the clock & data signal provided by the transmitter.