Abstract: Low spike count ring buffer mechanisms on neuromorphic hardware are provided. A ring buffer comprises a plurality of memory cells. The plurality of memory cells comprises one or more neurosynaptic core. A demultiplexer is operatively coupled to the ring buffer. The demultiplexer is adapted to receive input comprising a plurality of spikes, and write sequentially to each of the plurality of memory cells. A plurality of output connectors is operatively coupled to the ring buffer. Each of the plurality of output connectors is adapted to provide an output based on contents of a subset of the plurality of memory cells.

Abstract: A method of operating a network subscriber comprises receiving an input-data stream containing an input-transmission frame according to a field-bus protocol, where the input-data stream is received in chronologically successive data units having a defined processing width, decoding fields of the input-transmission frame by a plurality of field-processing units arranged in series, each field-processing unit decoding a predetermined field of the input-transmission frame, and generating an output-data stream comprising an output transmission frame according to the field-bus protocol from the input-data stream.

Abstract: A method includes detecting an open in a first IO element of a first bank of IOs and not in a second bank of IOs. The first and second banks of IOs are in a channel of a first die. The method includes shifting a first connection between the first IO element and a first core fabric of the first die to second connection between a second IO element and the first core fabric. The second IO element is in the first bank of IOs. The method includes shifting a third connection between a third IO element and a second core fabric of a second die to fourth connection between a fourth IO element and the second core fabric. The third and fourth IO elements are in a third bank of IOs of the second die. The method includes not shifting connections in the second and fourth banks of IOs.

Abstract: Technologies for controlling jitter at network packet egress at a source computing device include determining a switch time delta as a difference between a present switch time and a previously captured switch time upon receipt of a network packet scheduled for transmission to a target computing device and determining a host scheduler time delta as a difference between a host scheduler timestamp associated with the received network packet and a previously captured host scheduler timestamp. The source computing device is additionally configured to determine an amount of previously captured tokens present in a token bucket, determine whether there are a sufficient number of tokens available in the token bucket to transmit the received packet as a function of the switch time delta, the host scheduler time delta, and the amount of previously captured tokens present in the token bucket, and schedule the received network packet for transmission upon a determination that sufficient tokens in the token bucket.

Abstract: An integrated circuit including a functional circuit including at least one swapping circuit node, multiple duplicate electronic circuits, and a switch circuit. The duplicate electronic circuits are integrated in close proximity with each other each including at least one electronic device that is susceptible to RTN. The switch circuit electrically couples a different selected subset of at least one of the duplicate electronic circuits to the at least one swapping circuit node for each of successive switching states during operation of the functional circuit. A method of reducing noise including selecting a subset of the duplicate electronic circuits, electrically coupling the selected duplicate electronic devices to at least one swapping circuit node of a functional circuit, and repeating the selecting and electrically coupling in successive switching states during operation of the functional circuit for different subsets of the duplicate electronic circuits.

Abstract: The invention relates to a computer comprising: a plurality of processing units each having instruction storage holding a local program, an execution unit executing the local program, data storage for holding data; an input interface with a set of input wires, and an output interface with a set of output wires; a switching fabric connected to each of the processing units by the respective set of output wires and connectable to each of the processing units by the respective input wires via switching circuitry controllable by each processing unit; a synchronisation module operable to generate a synchronisation signal to control the computer to switch between a compute phase and an exchange phase, wherein the processing units are configured to execute their local programs according to a common clock, the local programs being such that in the exchange phase at least one processing unit executes a send instruction from its local program to transmit at a transmit time a data packet onto its output set of connection

Abstract: The invention relates to a computer comprising: a plurality of processing units each having instruction storage holding a local program, an execution unit executing the local program, data storage for holding data; an input interface with a set of input wires, and an output interface with a set of output wires; a switching fabric connected to each of the processing units by the respective set of output wires and connectable to each of the processing units by the respective input wires via switching circuitry controllable by each processing unit; a synchronisation module operable to generate a synchronisation signal to control the computer to switch between a compute phase and an exchange phase, wherein the processing units are configured to execute their local programs according to a common clock, the local programs being such that in the exchange phase at least one processing unit executes a send instruction from its local program to transmit at a transmit time a data packet onto its output set of connection

Abstract: The object is to simplify the configuration of a filter in a reception apparatus. The reception apparatus includes a filter. The filter provided in the reception apparatus selects a signal transmission characteristic that is one of a band stop characteristic or a low pass characteristic. Further, selection of the signal transmission characteristic in the filter provided in the reception apparatus is performed in response to a desired signal and an interference signal. In the filter provided in the reception apparatus, passage of the desired signal and attenuation of the interference signal based on the selected signal transmission characteristic are executed.

Abstract: In implementations of anomaly detection for incremental application deployments, one or more computing devices of a system implement an evaluation module for anomaly detection. An error record of a legacy version of a software application is generated, as well as an error record of an incremental version of the application. Data in the error record of the legacy version of the application is organized and grouped into one or more groups, each group having a membership criterion. Data in the error record of the incremental application is organized and compared to the one or more groups of the legacy application error record data based on the membership criterion for each group. If an organized data of the incremental application does not belong to any of the groups, then the organized data is identified as an anomaly.

Abstract: A messaging meta broker gateway for publish-subscribe messaging environments can provide connectivity, message routing, and subscription management between large numbers of clients and large numbers of brokers. The messaging meta broker gateway can provide access to large numbers of brokers to a client through a single connection. To a broker, the messaging meta broker gateway provides extremely wide fan-in and fan-out to gateway clients. To a service provider, the messaging meta broker gateway is a single system providing easy scaling with lightweight replication of instances, and shared, private, or virtual messaging environments supporting multiple customers and applications. The meta broker gateway can also connect gateway clients with other clients of the brokers, and also with archiving facilities. Protocol translation, security, and statistics logging are supported. The messaging meta broker gateway is suitable for cloud-based Internet-of-Things environments.

Abstract: A packet data network traffic management device comprises a plurality of ports comprising at least a first port, a second port, and a third port; and a plurality of deterministic multi-threaded deterministic micro-controllers, each of the micro-controllers associated with a corresponding one of the ports to control packet data through the corresponding port; and the plurality of multi-threaded deterministic micro-controllers cooperatively operate to selectively communicate data packets between the plurality of ports.

Abstract: A bandwidth throttling method is provided. The method includes receiving by a receiver from a QD Vcel cannon, a plurality of multi-frequency light pulses via a plurality of channels. The receiver determines that the plurality of multi-frequency light pulses comprises an out of band (OOB) signal transmitted over a first channel of the plurality of channels. The receiver receives from a first laser device of the QD Vcel cannon, a first light pulse of the plurality of multi-frequency light pulses. The first light pulse includes a first frequency for testing a visibility of the first light pulse at the receiver. The receiver determines if the first light pulse is visible at the receiver.

Abstract: A network node (bridge, switch, router) and method for traffic interconnection in a communication network. The node includes an interconnection network or switch fabric having ingress and egress ports in communication with the input and output ports of the node. The interconnection network also includes an interconnector having a retiming module, a permutation module, and a re-alignment module. Data arriving at the node input ports is provided to the ingress queues of the interconnection network where it is queued, if necessary, and then processed through the interconnector so that it can be provided to an appropriate egress port. Data at the egress ports is then provided to output ports for transmission toward its intended destination.

Abstract: Backwards compatibility may be achieved by transmitting an alternating pattern of uplink TPC commands in uplink timeslots. In one example, a served user equipment (UE) receives a downlink TPC command from a serving base station during a downlink timeslot in a sequence of downlink timeslots, and generates an uplink TPC command based on a received power level of the downlink TPC command. The served UE may then transmit the uplink TPC command in an uplink timeslot mapped to the downlink timeslot in which the downlink TPC command was received, as well as transmit an alternating pattern of uplink TPC commands in other uplink timeslots. The alternating pattern of uplink TPC commands may cause a neighboring base station to effectively maintain its transmit power level.

Abstract: A device that includes a plurality of transceivers configurable to simultaneously operate with a combination of bonded and unbonded transceivers. A first transceiver of the plurality of transceivers is operable at a first data rate, and a second transceiver of the plurality of transceivers is simultaneously operable at a second data rate that is different than the first data rate. The first and second transceivers are operable as bonded transceivers and wherein a third transceiver, of the plurality of transceivers, is simultaneously operable at a third data rate and the third transceiver is not bonded with any other transceiver.

Abstract: In a connection-oriented network a point-to-multipoint working path is established between a source node and a plurality of destination nodes using a number of working path intermediate nodes. A point-to-multipoint protection path is established for possible points of failure in the working path. Each protection path connects a first working path intermediate node upstream of a point of failure and destination nodes of the working path downstream of the first working path intermediate node. The point-to-multipoint protection path only connects to destination nodes of the working path and working path intermediate nodes which must be transited to reach the destination nodes of the working path.

Abstract: An integrated circuit includes a programmable logic device and optionally a control circuit coupled to the programmable logic device (PLD). The control circuit may detect that a reconfiguration criterion is satisfied. Responsive to the reconfiguration criterion being satisfied, the control logic may configure, using one or more randomizations, the PLD to implement a secret operation, wherein a first randomized configuration of the PLD results in a first circuit implementation that is different from, but functionally equivalent to, a second circuit implementation that results from a second randomized configuration of the PLD.

Abstract: A method for a terminal receiving a guaranteed time slot (GTS) allocation in a wireless personal area network (WPAN), according to one embodiment in the present specification, comprises the steps of: deciding a GTS allocation interval based on characteristic information of the terminal; and transmitting a GTS request to a WPAN coordinator, wherein the GTS request comprises the GTS allocation interval which is decided by the terminal; and receiving the GTS allocation information from the WPAN coordinator, wherein the GTS allocation information comprises the GTS allocation interval which is decided by the WPAN coordinator based on the GTS request that is transmitted by the terminal.

Abstract: A method for node communication for use in a rack system is provided. The method includes providing a detecting unit for connecting to the nodes via a circuit switching device; predefining a linked list in which a limit of times for the detecting unit to communicate with each of the nodes is set; sequentially selecting one node of the nodes so that the detecting unit is connected to the one node via the circuit switching device; adding an assigned communication parameter between the detecting unit and the one node selected to the linked list, wherein a number of times of communication corresponding to the assigned communication parameter is not greater than the limit of times; and performing communication between the detecting unit and the one node selected in accordance with the assigned communication parameter in the linked list.

Abstract: A network switch includes a first queue that receives a first packet. A second queue receives a second packet. A queue control module determines a desired output time slot of the first packet based on an arrival time and an output rate associated with the first packet, determines a length and a scheduled output time slot of the second packet, and selectively outputs the first packet before the second packet based on the desired output time slot, the length, and the scheduled output time slot.

Abstract: Disclosed is device-to-device communication based on a cellular communication network. A method of operating a terminal capable of supporting D2D (device to device) communication based on a cellular communication network may include: determining whether to perform central control D2D communication or distributed control D2D communication; and performing the distributed control D2D communication, or requesting a setting for the central control D2D communication to a base station on the basis of the determination. With the D2D communication based on the cellular communication network, the cellular communication, the central control D2D communication, or the distributed control D2D communication may flexibly and selectively operate in the cellular network.

Abstract: A time-space switch in a ring architecture includes input circuitry including N links each receiving M timeslots, a two-dimensional matrix of a plurality of switching circuits, the two-dimensional matrix is configured to receive from the input circuitry each of the M timeslots from the N links in a pipelined manner, and output circuitry including N links configured to receive any of the M timeslots from any of the N links from the two-dimensional matrix. The input circuitry, the two-dimensional matrix, and the output circuitry are arranged in a ring architecture therebetween. A link encoding protocol method performed in electrical circuitry includes receiving a plurality of time slots, grouping the plurality of time slots into time slot groups, performing a cyclic redundancy check between adjacent time slot groups, 64/65B encoding the time slot groups, and forward error correction encoding a plurality of 65B codewords from the 64/65B encoding.

Abstract: The present invention relates to a protocol accelerator module for a data transmission protocol level of a transceiver, particularly but not exclusively for rapid forwarding of data packets in wireless sensor networks using the time-division multiple access method according to the IEEE 802.15.4 standard. The invention also relates to a method of transceiver operation for rapid forwarding of data packets, likewise particularly, but not exclusively, in wireless sensor networks using the time-division multiple access method according to the IEEE 802.15.4 standard. The core of the invention is a reference table which stores references from identifiers of second transceivers to identifiers of third transceivers as well as references from specific messages to identifiers of third transceivers. A transceiver can check during reception of a data packet whether it is a data packet to be forwarded, and can take appropriate precautions for rapid sending of a data packet to be forwarded.

Abstract: A method is provided for managing transmissions among nodes communicating over a shared communication medium. The method includes: transmitting a frame from a sender node to a plurality of receiver nodes, the frame including at least a portion of a data packet and control information associated with accessing the communication medium; transmitting over the communication medium information indicating an end of a time window allocated for transmission of acknowledgement signals to the sender node from at least some of the plurality of receiver nodes; assigning each of a plurality of time slots in the time window to different subsets of the plurality of receiver nodes; and for a given receiver node, transmitting an acknowledgement signal from the given receiver node to the sender node during a time slot assigned to the given receiver node, the acknowledgement signal responsive to at least the frame.

Abstract: The embodiments of the present invention disclose a backplane and backplane system. The backplane includes at least two service slots with the same function and an exchange slot. Among the pins of different service slots with the same function respectively connected to the exchange slot, at least two pins are arranged to resemble a stepped form. When arranged in this manner, the distribution and orientation of the connection lines connecting the pins of the service slots with the same function to the exchange slot may be adjusted, and wiring density within a single wiring layer may be increased, which therefore enables the connection lines between the service slots and the exchange slot to be staggered from each other in less wiring layers or even one wiring layer, and as a result, decreases the number of the wiring layers to be used, and reduces the costs of the backplane.

Abstract: A physical layer device including a plurality of ports and a clock synchronization module. Each port of the plurality of ports is programmable to receive a grandmaster clock. The clock synchronization module is configured to i) receive the grandmaster clock from a first port of the plurality of ports (wherein the first port has been programmed to receive the grandmaster clock), and ii) clean up the grandmaster clock, wherein cleaning up the grandmaster clock includes one or more of removing jitter from the grandmaster clock, controlling a voltage swing or the grandmaster clock, or establishing fixed edge rates of the grandmaster clock. Other ones of the plurality of ports, not including the first port, are programmed to receive the cleaned up grandmaster clock for use when transmitting data.

Abstract: An Automatic Repeat reQuest (ARQ) transmitter for use in a wireless communication system and method for its operation are provided. The method includes determining unutilized capacity of an ARQ receiver buffer in an ARQ receiver, determining if the ARQ receiver buffer can support an ARQ block to be transmitted based on the determined unutilized capacity of the ARQ receiver buffer, and if it is determined that the ARQ receiver buffer can support the ARQ block to be transmitted, transmitting the ARQ block to the ARQ receiver.

Abstract: A computer-implemented method may include receiving at a wireless device one or more beacon packets sent by a communication base station, determining a delay period at the wireless device, wherein the delay period is determined so that a delay for the wireless device is different than a delay for another wireless device, sending a first association request from the wireless device after waiting for the delay period, and establishing communication with the base station if an association response is received from the base station within a determined time period. The first association request may include information identifying the wireless device and an association code.

Abstract: Disclosed herein are methods and systems for dynamically selecting a paging-concatenation level for a page based on one or more properties of the page. An exemplary method involves, at a wireless communication network that is configured to provide service to at least one wireless-communication device, using at least one property of a page record as a basis for selecting a paging-concatenation level for the page record, and paging the wireless-communication device by transmitting a page message that includes the page record, wherein the page message is of the selected paging-concatenation level. Various properties of the page record, such as the paging-attempt status and/or the target mobile station of the page, among others, may be used to select the paging-concatenation level.

Abstract: An apparatus that includes W interfaces to a circuit-switched network, where W is an integer number that equals the product of smaller integer numbers X and N. The apparatus also includes X discrete switching apparatus each having N ones of the W network interfaces, as well as a plurality of switching-expansion interconnects each interconnecting ones of the X switching apparatus, such that the W network interfaces are collectively interconnected in a non-blocking manner.

Abstract: A method is proposed for supporting downlink JD (joint detection) in a TDD CDMA communication network system, comprising steps of: judging whether the CAI (code allocation information) in a downlink timeslot will change in the next TTI (transmission time interval); if the CAI will change, inserting the changed CAI as a specific control information into a specified field in the traffic burst in the downlink timeslot corresponding to current TTI; sending the traffic burst containing the specific control information to each UE (user equipment) in the downlink timeslot via a downlink channel.

Abstract: A method and an apparatus for reducing power consumption and digital logic noise in a time division multiplexed memory switch. The method is embodied in an egress selection switch (ESS) block architecture. The ESS block includes a data disable block which prevents the propagation of data, in particular ingress grains, to a given group of egress ports if the data is not selected by any of the egress ports in a given group. While the ingress data disable method partitions ports into groups and saves power by disabling the fanout tree from the root on a port group basis, the egress data disable method saves power on a port group basis by disabling the fanout tree from the tail end in addition to applying the ingress data disable method. The ESS block also includes an grain select block for selecting and storing a given ingress grain for eventual output to an egress port.

Abstract: When being blended particularly in a color toner, a barium titanate external additive for toner enhances the toner fluidity, electrical properties, and other relevant performance; concurrently achieves high image density and reduced background fog in a color printer using the toner; and further retains high image quality even under a high-temperature high-humidity environment and a low-temperature low-humidity environment. An industrially advantageous producing method of the barium titanate external additive for toner is also provided. The external additive for toner of the present invention includes spherical barium titanate having undergone coating treatment with a hydrophobicizing agent.

Abstract: The present disclosure provides a structured, pipelined large time-space switch and method of operation resolving interconnect complexity. The time-space switch results in an interconnect complexity that does not grow as the spatial dimension is increased and results in a reduction of long high fan-out nets, a quicker layout, and improved clock speed. With respect to time-space switch fabric implementation, the present invention improves the maximum clock frequency of the switch fabric, and improves integrated circuit layout time by eliminating long high fan-out nets. Certain high-speed large switch fabrics may not be realizable without this implementation, and it significantly reduces implementation time (and cost).

Abstract: A beacon slot position control section of a radio communication apparatus constituting a radio network system which detects whether empty beacon slots are present in a beacon period. When an empty beacon slot is present before the period in which the radio communication apparatus transmits a beacon, a movable counter starts counting a specified number of super frames. When the count is completed, the radio communication apparatus transmits a beacon of the radio communication apparatus at the earlier empty beacon slot. Consequently, since the empty beacon slots are eliminated and the beacon period is compacted, even if the number of radio communication apparatuses joining the radio network system fluctuates dynamically, the radio communication apparatus can perform radio communication with high efficiency and less waste of consumed electricity.

Abstract: A beacon slot position control section of a radio communication apparatus constituting a radio network system which detects whether empty beacon slots are present in a beacon period. When an empty beacon slot is present before the period in which the radio communication apparatus transmits a beacon, a movable counter starts counting a specified number of super frames. When the count is completed, the radio communication apparatus transmits a beacon of the radio communication apparatus at the earlier empty beacon slot. Consequently, since the empty beacon slots are eliminated and the beacon period is compacted, even if the number of radio communication apparatuses joining the radio network system fluctuates dynamically, the radio communication apparatus can perform radio communication with high efficiency and less waste of consumed electricity.

Abstract: Systems and methods for burden sharing in satellite based communication systems are disclosed. One or more users in a satellite based communication system may experience signal degradation or signal fading that can occur for an extended period of time, such as when the fade is due to rain fade. The system can improve a communication link with a particular user by varying the data rate. The data rate can be varied by reducing a coding rate to compensate for low signal quality. In a time multiplexed communication system where multiple users time multiplex the available communication bandwidth, the system can concurrently adjust a time allocated to a user based in part on the coding rate. The time allocated to a user can be increased for decreased coding rates in order to maintain a substantially stable symbol rate to the user for each time multiplex cycle of users.

Abstract: An example embodiment includes determining a cut of a graph to obtain a bi-partite sub-graph, where the graph represents a plurality of nodes and links between the plurality of nodes in a wireless mesh network. A channel is assigned to the bi-partite graph, and the obtained bi-partite subgraph is removed from the graph. The determining, assigning and removing steps are repeated until the graph has been divided into k bi-partite subgraphs, where k is the number of channels being used for scheduling.

Abstract: A communications system and protocol for a radio communications network including a number of transceiver devices. The protocol ensures that network variables to be shared by all devices are correctly received and updated by all devices. The protocol also provides for accurately detecting the transition from one time slot to another, in a given data transaction.

Abstract: A telecommunication system (1) provides bi-directional communication between TDM signals on one side and ATM signals on the other. An ATM aggregate (10) receives and transmits ATM signals, and a TDM interface (2) receives and transmits TDM signals. A format converter has an ATM bus (9) and a TDM bus (4) connected to their respective interfaces. Service-specific adapters (5-8) are connected between the buses.

Abstract: In accordance with the invention, time slot interchange switches (“TSIS”) with bit error rate testing are described. The bit error rate testing includes creating a channel of data appropriate for bit error rate testing and monitoring the bit error rate testing on that channel.

Abstract: A system and method for transmitting/receiving a signal in a communication system are provided, in which a transmitter determines to change a transmission time of a superframe header, when a structure of a superframe is changed, determines the transmission time of the superframe header according to a result of the determination to change the transmission time of the superframe header, transmits information about the determined transmission time to a receiver, and transmits the superframe header at the determined transmission time.

Abstract: A modular optical switch includes a set of optical switch modules connected in a mesh, a master controller for the whole optical node and a switch-module controller for each of the optical switch modules. The optical switch modules receive optical signals from, and transmit optical signals to, edge nodes based on connection requests received from the edge nodes. The master controller acts to select a path, using a simple or compound time-slot matching process, through the mesh of switch modules for each optical signal related to a connection request. Advantageously, the optical switch modules are fast switching, enabling the use of time-sharing schemes such as TDM, and the modular optical core node is made practical by efficient path selection at the master controller. A hybrid modular switch may include both optical and electronic switch modules, a master controller, and a switch-module controller for each of the switch modules.

Abstract: Disclosed are an apparatus and method for removing noise contained within a usable frequency band of a mobile communication terminal. The apparatus includes a multiplier for multiplying a main clock of the mobile communication terminal by a predetermined integer to generate a reference signal; a multiplexer for multiplexing parallel signals, the parallel signals being transmitted to a peripheral device inside the mobile communication terminal, using the reference signal, and converting the parallel signals into serial signals; a demultiplexer for demultiplexing the serial signals to convert the serial signals into parallel signals; and a frequency divider for recovering the reference signal of the serial signals transmitted from the demultiplexer into the main clock.

Abstract: A method and apparatus for transceiving multiple service data from multiple communication services to a SONET/SDH communication system or network is provided. A SONET/SDH universal framer (SURF) bidirectionally provides communication between a SONET/SDH communication port and multiple service communication ports using their native data format. A provisioning register stores provisioning information describing the communication system and the communication ports. A SONET/SDH byte engine processes complex hierarchical SONET/SDH frames storing intermediate states when it changes to process a byte of data of a different STS-1 equivalent frame in a SONET/SDH STS-N frame. A service byte engine processes the multitude of service data formats and generally its intermediate states are restored, processed, and saved when it changes to process a different data stream or a different frame of data of a given service.

Abstract: An apparatus and method for adjusting transmission phasing in a point-to-point communication link is disclosed. The relative phases of the transmissions from each antenna are adjusted before transmission to give optimum gain when received by two or more antenna elements and a signal combining element. The signal includes a data component, consisting of a subset of the subcarriers modulated with the input data, which is common to transmissions from all antenna elements; and a phase reference component consisting of a subset of the subcarriers that are modulated with a predetermined phase. The signal combining element is operable to receive the components and extract phase information.

Abstract: Whether the reception electric field level of the antenna #1 is higher than the predetermined level is judged. If the reception electric field level of the antenna #1 is not higher than the predetermined level, the communication mode is to be set to the multi-slot mode, and then whether the reception electric field level of the antenna #1 is higher is judged by comparison of the reception electric field level of the antenna #1 and the reception electric field level of the antenna #2. If the reception electric field level of the antenna #1 is higher, the call mode is to be set to the antenna #1 for executing transmission and reception, or if the reception electric field level of the antenna #1 is not higher, the communication mode is to be set to the antenna #2 for executing transmission and reception.

Abstract: A network device for processing packets. The network device includes a memory management unit for storing packets and performing resource checks on each packet and an egress module for performing packet modification and transmitting the packet to a destination port. The memory management unit includes a timer for indicating that a free space should be created on a bus slot between the memory management unit and the egress module, wherein the free space is used for transmitting CPU instructions from the memory management unit to the egress module.

Abstract: A circuit and method are presented for signal processing and routing of digital voice telephony signals, using a specialized high-density integrated circuit voice processor. The voice processor performs several essential functions required for telephony processing, including echo cancellation, protocol conversion, and dynamic range compression/expansion. These functions are traditionally performed by multiple circuits or modules. By combining these capabilities in a single device, power and circuit board area requirements are reduced. The embodiment of the circuit and method disclosed herein include novel implementations of a time-slot interchange circuit and a telephony signaling circuit. Both of these circuits are designed to minimize demands on the signal processing engines incorporated within the voice processor, and account for very little of the on-chip circuitry.

Abstract: A shared memory stores packets for a packet processor. The shared memory is arranged into banks that are word-interleaved. All banks may be accessed in parallel during each time-slot by different requesters. A staggered round-robin arbiter connects requesters to banks in a parallel fashion. Requestor inputs to the arbiter are staggered to allow access to different banks in a sequential order over successive time-slots. Multi-processor tribes have many processors that generate random requests to the shared memory. A slot scheduler arranges these random requests into a stream of sequential requests that are synchronized to the staggered round-robin arbiter. A packet interface requestor stores incoming packets from an external network into the shared memory. The packet's offset within pages of the shared memory is determined by the first available bank that the packet can be written to, eliminating delays in storing incoming packets and spreading storage of frequently-accessed fields.