Abstract: An access classification device includes: a processor configured to: construct a plurality of trees in each of which at least a first destination and a second destination are set as nodes, content information corresponding to the nodes is added to the nodes, and an instruction to transfer an access from the first destination to the second destination is set as an edge; associate nodes of the plurality of trees with each other for the plurality of trees constructed, based on similarity between local structures of the trees; calculate similarity between the nodes associated with each other in the plurality of trees, based on the content information added to the nodes, and calculate similarity between the plurality of trees using the calculated similarity between the nodes associated with each other; and classify the access into a set with similar features, based on the similarity calculated.

Abstract: A method, computer program product, and system are provided for associating one or more memory buffers in a computing system with a plurality of memory channels. The method can include associating a first memory buffer to a first plurality of memory banks, where the first plurality of memory banks spans over a first set of one or more memory channels. Similarly, the method can include associating a second memory buffer to a second plurality of memory banks, where the second plurality of memory banks spans over a second set of one or more memory channels. The method can also include associating a first sequence identifier and a second sequence identifier with the first memory buffer and the second memory buffer, respectively. Further, the method can include accessing the first and second memory buffers based on the first and second sequence identifiers.

Abstract: A method of generating a high-power Radio-Frequency ultrashort waveform comprising the steps of generating an input waveform at a relatively low power level from an impulse response characteristic of a reverberant cavity via one-bit quantization and time reversal; generating an amplified input waveform of a power higher than the input waveform via feeding the input waveform into one or more amplifiers; generating a compressed ultrashort pulse having a high power relative to the amplified input waveform via feeding the amplified input waveform into the reverberant cavity.

Abstract: A method for monitoring a network. The method includes generating a measurement value of network traffic processed by a component of a number of components of a network device. Based on the measurement value meeting a pre-determined criterion, a threshold-crossing event of the component is detected. In response to the threshold-crossing event, a number of time series of measurement values of the network traffic are generated. In particular, each time series is generated by one of the number of components. Accordingly, a combination of the number of time series is sent as a telemetric data stream by the network device to a network management system of the network.

Abstract: The invention provides for a broadcast channel transmission method comprising delivering broadcast channel data as a series of blocks (1-16), each series being provided in a segment (1-16) of the system bandwidth (20), and distributing the broadcast channel data within each series of blocks (1-16) such that user equipment capable of receiving more than one segment (1-16) receives different blocks from different segments within a time period which is a multiple of the time period (T) for receipt of all blocks within one segment.

Abstract: A system for pre-fetching a data frame from a system memory to a cache memory includes a processor, a queue manager, and a pre-fetch manager. The processor issues a de-queue request associated with the data frame. The queue manager receives the de-queue request, identifies a frame descriptor associated with the data frame, and generates a pre-fetch hint signal. The pre-fetch manager receives the pre-fetch hint signal and generates a pre-fetch signal and enables the cache memory to pre-fetch the data frame. Subsequently, the queue manager de-queues the frame descriptor. The processor receives the frame descriptor and reads the data frame from the cache memory.

Abstract: Techniques for performing duplicate detection and re-ordering for a HARQ transmission are described. For duplicate detection, a receiver determines whether a decoded packet x for an ARQ channel y is a duplicate packet based on packet x and a prior decoded packet for ARQ channel y. For re-ordering, the receiver determines whether an earlier packet is still pending on any other ARQ channel based on prior decoded packets for the ARQ channels and forwards packet x only if there are no pending earlier packets. There are no pending earlier packets on another ARQ channel z if (1) a decoded packet was received on ARQ channel z at a designated time or later or (2) a decoded packet was not received on ARQ channel z within a time window from current time.

Abstract: In a media access control (MAC) processor, a programmable controller is configured to execute machine readable instructions for implementing MAC functions corresponding to data received by a communication device. A tightly coupled memory is associated with the programmable controller. A system memory is coupled to the programmable controller via a system bus, and a hardware processor is coupled to the system bus and the tightly coupled memory. The hardware processor is configured to implement MAC functions on data received in a communication frame, store, in the tightly coupled memory, processed data corresponding to data in the communication frame that indicates a structure of downlink data in the communication frame, and store, in the system memory, processed data corresponding to other data in the communication frame.

Abstract: Various embodiments of systems and methods for memory access are provided. In one embodiment, a data segment is stored in a plurality of memory segments of at least one memory bank. The data segment stored in the memory segments is selected, where the data segment has a bit boundary that is arbitrarily misaligned with at least one memory segment boundary of the memory segments.

Abstract: A circuit arrangement for signal pick-up and signal generation and a method for operating this circuit arrangement. The circuit has at least one timer module for providing a time basis to a plurality of time control modules connected to it, and has a time routing unit, which is connected to it for the interconnection of the named modules and their signals.

Abstract: A routing method of a wireless communication system is provided implementing advantageous features of both the tree routing and the link state routing. In the routing method, the system generates an adaptive tree table which defines a network in a tree structure of at least one branch with at least one node and each node generates a link state table which includes information on neighbor nodes, such that the packets are routed on the basis of the adaptive tree table and the link state table. Advantageous mechanisms of the tree routing and the link state routing are combined, thereby it is possible to eliminate most single point of failures of conventional tree routing and provide shorter paths compared with conventional tree routing.

Abstract: A method, an apparatus, and an information recording medium for storing and reproducing an interactive service capable of efficiently storing and processing interactive signaling information are provided. The information recording medium has recorded thereon interactive signaling information of a digital broadcast and includes a first region storing information on a time when the interactive signaling information occurs, a second region storing a type of the interactive signaling information and identification information; and a third region storing signaling items of the interactive signaling information. In the method and apparatus, filtering and monitoring using hardware or software to acquire interactive signaling information on a service stream for reproducing an interactive service is unnecessary because the signaling information is separately stored.

Abstract: A wireless base station apparatus performing wireless communication with a mobile station apparatus includes: a transmission unit to transmit data to the mobile station apparatus; a reception unit to receive a delivery result for the data from the mobile station apparatus; and a control unit to determine whether reception processing through a first channel is performed or parallel reception processing through the first channel and a second channel is performed on the basis of a radio line quality between the wireless base station apparatus and the mobile station apparatus or an amount of processing in the reception unit if the transmission unit transmits a permission notification permitting the transmission through the first channel to the mobile station apparatus, where the reception unit performs the reception processing in accordance with the result of the determination to receive the delivery result transmitted through the first channel or the second channel.

Abstract: A shared memory switch and switch fabric architecture are described which employ partitions of the shared memory to implement multiple, independent virtual congestion domains, thereby allowing congestion to be handled for different classes of traffic independently.

Abstract: Management of congestion level, in a computer-related context, is disclosed. Also disclosed is a system generating a plurality of computer network-related tables during system operation. A number of the tables are each separately indexed by a different index. The system includes at least one tangible computer-readable medium adapted to store, at each indexed location, a swap count providing an indication of the congestion level of the indexed location. The system also includes insert logic stored as instructions on the at least one medium for execution. When executed, the insert logic is operable to: i) insert, when a predetermined condition has been satisfied, a new entry by overwriting the current entry stored in the indexed location having the lowest swap count; and ii) update the swap counts in each of the indexed locations in a manner that maintains the total swap count at least substantially constant over time.

Abstract: A media access control (MAC) processor includes a programmable controller and a memory coupled to the programmable controller to store machine readable instructions for implementing MAC functions corresponding to data received by a communication device. A hardware processor is coupled to the programmable controller. The hardware processor includes a processing engine configured to implement MAC functions on the data received by the communication device. The hardware processor additionally includes a context memory coupled to the processing engine to store state information of the processing engine corresponding to one or more contexts, and context switch logic coupled to the processing to determine when the processing engine should switch contexts.

Abstract: An apparatus and a method for load balancing across multiple routes using an indirection table and hash function during a process of packet classification are disclosed. A network device such as a router includes a memory, a hash component, and a result memory. The memory is referred to as an indirection random access memory (“RAM”), is capable of storing information regarding number of paths from source devices to destination devices. The memory, in one embodiment, provides a base index value and a range number indicating the number of paths associated with the base index value. The hash component generates a hash index in response to the base index value and the range number. Upon generation of hash index, the result memory identifies a classification result in response to the hash index.

Abstract: The present invention relates to a wireless communication system to properly switch over a transmission method of radio signals corresponding to a configuration of a receiver. The wireless communication system according to the present invention includes a transmitting device having a plurality of antennas and capable of transmitting radio signals different from each other from these antennas, and a receiving device having at least one antenna and receiving the radio signals transmitted from the transmitting device. The receiving device comprises an information transmitting unit transmitting, to the transmitting device, configuration information about a configuration of the receiving device, and the transmitting device includes a transmitting unit transmitting the radio signals by a transmission method corresponding to the configuration information received from the receiving device.

Abstract: A method for allocating space among a plurality of queues in a buffer includes sorting all the queues of the buffer according to size, thereby to establish a sorted order of the queues. At least one group of the queues is selected, consisting of a given number of the queues in accordance with the sorted order. A portion of the space in the buffer is allocated to the group, responsive to the number of the queues in the group. A data packet is accepted into one of the queues in the group responsive to whether the data packet will cause the space occupied in the buffer by the queues in the group to exceed the allocated portion of the space.

Abstract: Methods and apparatus for processing a plurality of sets of routing information received from corresponding ones of a plurality of neighbor nodes connectable to a router, the router having a plurality of memory units accessible via separate paths. The method comprises creating a respective plurality of non-identical routing information subsets from each of at least one of the received sets of routing information; accessing the plurality of memory units via the separate access paths; and storing the plurality of non-identical routing information subsets created from a given one of said received sets of routing information in respective ones of the plurality of memory units. By providing a distributed memory architecture for storing routing information, an increase in a router's memory requirements can be met by increasing the number of memory units.

Abstract: A system and method are presented for transceiving Time Division Multiple Access (TDMA) telephone communications through a common filter. The system includes a tunable ferro-electric bandpass filter (FE BPF), a controller, a low noise amplifier (LNA), and a power amplifier (PA). The FE BPF has a control input to accept tuning voltage signals from the controller and two signal ports. In response to the tuning voltage signals, the FE BPF selects a transmit or receive frequency passband between the signal ports. The FE BPF first signal port is connected to the LNA and the PA and the FE BPF second signal port is connected to an antenna in a wireless device. The LNA and PA are activated and deactivated in response to control signals from the controller.

Abstract: A distributed switching system comprising a call controller, multiple source modules, and multiple destination modules provides circuit switching functionality without using a centralized circuit switch. When a source module of the multiple source modules receives inbound data, the source module broadcasts the data to each destination module of the multiple destination modules via an inbound time slot of multiple inbound time slots. The call controller selects a destination module of the multiple destination modules to process the data and informs the selected destination module of the inbound time slot. The selected destination module then receives the broadcast via the inbound time slot and processes the broadcast data. The distributed switching system further provides for a transfer of data in an outbound direction by allocating an outbound time slot in which the selected destination module embeds tagged data for receipt and forwarding by the source module.

Abstract: A memory that includes a plurality of packet pins, a synchronous memory, and a packet controller. The synchronous memory receives address and control signals in synchronization with a clock signal. The packet controller sequentially receives packet data bits through the packet pins in synchronization with the clock signal when a packet enable signal is activated, and converts the inputted packet data into the address and control signals. Specifically, packet data bits that are first inputted through the packet pins represent an operation mode.

Abstract: A semiconductor memory device resolves skew problem due to delay difference between the case when data that is inputted through data input/output (IO) pin is transferred to one global I/O bus and the case when transferred to another global I/O bus based on data width option. The semiconductor memory device includes a first data IO pad formed at one side of a chip, a second data IO pad formed at the other one, a first global data bus receiving data from the first data IO pad, a second global data bus receiving data from the second data IO pad, a first data path for transferring data from the first data IO pad to the first global data bus, a second data path for transferring data from the first data IO pad to the second global data bus, and a third data path for transferring data inputted to the second data IO pad to the first global data bus depending on data width option, wherein data transfer time of the second data path is substantially equal to data transfer time of the third data path.

Abstract: A method and apparatus for transceiving multiple service data from multiple communication services to a SONET/SDH communication system or network are provided. A SONET/SDH universal framer (SURF) bidirectionally provides communication between a SONET/SDH communication port and multiple service communication ports using their native data format. A SONET/SDH byte engine processes complex hierarchical SONET/SDH frames storing intermediate states when it changes to process a byte of data of a different STS-1 equivalent frame in a SONET/SDH STS-N frame. A service byte engine processes the multitude of service data formats and generally intermediate states are restored, processed, and saved when the service byte engine changes to process a different data stream or a different frame of data of a given service.

Abstract: Cooperative scheduling of master and slave base station transmissions is disclosed. Silent and deaf intervals are scheduled in a frame format of a first network to allow transmissions to occur in a second network without interference.

Abstract: An instrumentation network data system that transmits periodically measured instrument parameters or data to workstations residing on a computer network. A laboratory workstation residing on the network periodically collects and processes data from the instruments at predetermined collection time-intervals. The laboratory workstation includes a buffering data file to store the analyzed data. A supervisor workstation residing on the network periodically accesses the analyzed data from the buffering data file at predetermined supervision-time intervals and updates a supervision data file in the supervisor working station with the analyzed data. At predetermined viewing-time intervals, the supervisor working station can transmit the analyzed data to at least one viewing workstation residing on the network for remote viewing of the analyzed data.

Abstract: A distributed memory switch system for transmitting packets from source ports to destination ports, comprising: a plurality of ports including a source port and a destination port wherein a packet is transmitted from the source port to the destination port; a memory pool; and an interconnection stage coupled between the plurality of ports and the memory pool such that the interconnection stage permits a packet to be transmitted from the source port to the destination port via the memory pool.

Abstract: A multiport concentrator concentrates network data from different links in a network and carried on a plurality of lower speed lines into a stream of data carried on a higher speed line. A measurement system determines network statistics from the stream of data carried by the higher speed line.

Abstract: A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism. According to the method, an efficient set of virtual output queues (at most one virtual output queue per ingress adapter) is selected, while keeping the algorithm simple enough to allow its implementation in fast state machines. For determining a set of virtual output queues that are each authorized to send a packet, the algorithm is based upon degrees of freedom characterizing states of ingress and egress adapters. For example, the degree of freedom, derived from the collapsed virtual output queuing array, could represent the number of egress ports to which an ingress port may send packet, or the number of ingress ports from which an egress port may receive packets, at a given time.

Abstract: A method and system for improving throughput and speed of an interconnect system such as peripheral component interconnect express (PCIe). The method and system automatically forward changes in virtual address translation data to each device that supports the system and method on the interconnect system. This improves performance by obviating the need for the devices to request address translation services each time a direct memory access is made, thereby diminishing the amount of overhead traffic on the interconnect system.

Abstract: Tree data structures are stored among and within multiple memory channels, which may be of particular use with, but not limited to tree bitmap data structures. A subtree (or entire tree) typically includes one or more leaf arrays and multiple tree arrays. One or more leaf arrays are typically stored in a first set of memory channels of N+1 sets of memory channels, the N+1 sets of memory channels including N sets of memory channels plus the first set of memory channels. Paths of the multiple tree arrays are typically stored in said N memory channels, wherein each tree array of the multiple tree arrays associated with one of said paths is stored in a different one of said N sets of memory channels.

Abstract: Apparatus and a method for ciphering messages in mobile telecommunications system user equipment are disclosed. The apparatus is arranged to receive ciphering configuration parameters in a Radio Resource Control (RRC) layer; forward ciphering configuration parameters to a Radio Link Control (RLC) or Medium Access Control (MAC) layer; and, in response to subsequent receipt of a message from the network, which message indicates that the user equipment device is to start ciphering, configuring the user equipment device to start ciphering using the ciphering configuration parameters in the RLC/MAC layer.

Abstract: A broadband packet switch that handles all packets that arrive within the same frame time by simultaneously bit-pipelining the packets into different sections of the one-stop packet buffer through an input switch. Each packet remains in is selected section until its eventual exit from the buffer through an output switch. Access to the memory storage in which the packet buffer resides is not through a memory bus or buses, thereby engendering massive parallel access.

Abstract: Placing virtualization agents in the switches which comprise the SAN fabric. Higher level virtualization management functions are provided in an external management server. Conventional HBAs can be utilized in the hosts and storage units. In a first embodiment, a series of HBAs are provided in the switch unit. The HBAs connect to bridge chips and memory controllers to place the frame information in dedicated memory. Routine translation of known destinations is done by the HBA, based on a virtualization table provided by a virtualization CPU. If a frame is not in the table, it is provided to the dedicated RAM. Analysis and manipulation of the frame headers is then done by the CPU, with a new entry being made in the HBA table and the modified frames then redirected by the HBA into the fabric. This can be done in either a standalone switch environment or in combination with other switching components located in a director level switch.

Abstract: A digital cross connect comprises plural switching stages. Each stage has plural switches which receive plural frames of time multiplexed input data and which switch the data in time and space. Configurations of the switches change in frame synchronization at the start of a synchronized data frame. Both the configuration data and a frame clock may be propagated through the plural stages from a master switch. First and last stages of the digital cross connect may be implemented on common chips having two framing time bases. Data may be aligned to a global frame clock and interchanged using a single random access memory in a time slot interchanger. The write address to the random access memory is generated from a local frame counter keyed to the input data frame while a read address is transformed from a global frame counter.

Abstract: Time-slot interchange (TSI) switches include an input buffer that is configured to receive at least first and second groups of serial input data streams and an output driver that is configured to generate at least first and second groups of serial output data streams. A control circuit is also provided. This control circuit is electrically coupled to the input buffer and output driver. The control circuit is configured to provide programmable group-based output drive enable control to the at least first and second groups of serial output data streams that is independent of per-channel output stream programming. This per-channel output stream programming is defined by mode bits within the switch's connection memory.

Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

Abstract: A signal router routes N inputs to M outputs. All inputs signals are ultimately applied to a data buss by spreading across multiple buss lines and time multiplexing. The data are read from the buss and written in identical images to K random access memories. The memories are addressed and read according to a different schedule for each of K output signals that are ultimately demultiplexed to M outputs. As each RAM image is read, another RAM image is written and vice versa. Since each RAM image contains the same data, the generation of signals from each RAM to supply each of the respective K output signals can be done at a rate that is substantially more independent of the input, buss, or RAM write operations than prior art techniques permit.

Abstract: A switch for a network. The switch comprises a memory mechanism in which portions of packets are stored. The switch comprises a mechanism for instituting changes to the memory mechanism while the memory mechanism continuously operating on packets. A method for switching packets. The method comprises the steps of receiving changes for a memory mechanism of a switch at a buffer of the switch. Then there is the step of implementing the changes to the memory mechanism when the memory mechanism receives an implementation signal while the memory mechanism continuously operates on packets.

Abstract: Method, apparatus and software for processing sets of routing information in a router having a plurality of memory units accessible via separate access paths. The sets of routing information are typically routes received from neighbour nodes. The method includes creating a plurality of non-identical routing information subsets from each received set of routing information, accessing the memory units via the separate access paths and storing the routing information subsets created from a common set of routing information in respective ones of the plurality of memory units, By providing a distributed memory architecture for storing routing information, an increase in a router's memory requirements can be met by increasing the number of memory units.

Abstract: A system for determining an order of service of temporarily stored objects, at least one priority flag being attached to certain objects, includes a set of storage units disposed in a matrix organized into C subsets of elements, where C is the number of objects stored temporarily. Each subset corresponds to an object and all the subsets include the same number P of elements corresponding to P time positions. Each element includes a memory which can receive at least one time priority flag. A first time position selector determines, within the matrix, and from all the subsets, the element(s) marked by a particular time priority flag and corresponding to the time position having the lowest value.

Abstract: A method for communicating information is disclosed wherein a time slot is allocated in a time division multiple access system for a transmission from a subscriber to a headend. Synchronization of a clock of the subscriber with respect to a clock of the headend is enhanced using a message transmitted from the headend to the subscriber which is indicative of an error in a subscriber transmission time with respect to the time slot. A feedback loop process is used to determine at least one of fractional symbol timing correction and carrier phase correction of a transmission from the subscriber to the headend. Filter coefficients are generated at the headend from a ranging signal transmitted from the subscriber to the headend and transmitting the filter coefficients from the headend to the subscriber, the filter coefficients being used by the subscriber to compensate for noise in a transmission from the subscriber to the headend.

Abstract: A multi-stage (e.g., two-stage) packet-based lookup process using a Ternary Content Addressable Memory (TCAM) divided into partitions. The result of a first stage lookup is used to selectively search one of a plurality of TCAM partitions during the second stage. A subset of destination address bits may be used in the first stage to hash to a selected partition for the second stage. Alternatively, a partitioning algorithm segments a routing trie into partitions, and then, either a separate, small TCAM or one of the partitions is used in the first stage to map a prefix of the destination address to one of the TCAM partitions for use in the second stage. The “trie-based” algorithms may advantageously partition the trie such that each second stage partition comprises a substantially contiguous sequence of routing prefixes in a post-order traversal of the routing trie, together with one or more covering prefixes thereof.

Abstract: A distributed memory switch system for transmitting packets from source ports to destination ports, comprising: a plurality of ports including a source port and a destination port wherein a packet is transmitted from the source port to the destination port; a memory pool; and an interconnection stage coupled between the plurality of ports and the memory pool such that the interconnection stage permits a packet to be transmitted from the source port to the destination port via the memory pool.

Abstract: Apparatus, and an associated method, for providing a mobile node with identifying indicia used to create a care/of address identifying the location of the mobile node. A router advertisement is generated by an access router. The router advertisement includes identifying indicia identifying the identity of the sub-network at which the access router is located. A detector detects the identifying indicia. A broadcast selector selectably broadcasts the identifying indicia to the mobile node. The mobile node utilizes the identifying indicia to form the care/of address.

Abstract: A switching apparatus incorporated in a time division multiplying system has a read control memory for storing addresses indicative of parts of different messages to be transferred to different channels, and a read controller checks the read control memory so as to determine the memory areas of a message memory for selectively transferring the parts of different messages to the channels, thereby making the memory structure simple.

Abstract: A high capacity digital non-blocking cross-connect switching fabric is realized by employing a multi-port RAM based space-time switch having a plurality of write circuits and a plurality of read circuits, each of which operates at a timing rate that is a prescribed fraction of the input/output clock rate of the input/output ports of the multi-port RAM based cross-connect switching fabric. The at least one multi-port RAM switch unit has a plurality of write circuits and a plurality of read circuits, each of which operates at a timing rate that is a prescribed fraction of the input/output clock rate of the input/output ports of the multi-port RAM based cross-connect switching fabric. Additionally, in one embodiment, each of the write circuits and each of the read circuits has independent and unrestricted access to all data storage positions in each of a plurality of storage units that make up the at least one multi-port RAM switch unit.

Abstract: A method of writing data to a packet memory device in a system for transmitting data in packets across a packet network, wherein said packets are arranged to form a plurality of packet streams, the method comprising:

Abstract: The invention provides a time-division switch and a time-division switching method by which a multi-frame signal of an arbitrary bit length can be outputted to or inputted from an arbitrary time slot. The time-division switching method is applied to weitchably connect time slots between different highways in time-division multiplex communication. The switch includes an external memory to which data from input time slots may be dropped, and from which data may be inserted into output time slots. Fixed data such as tone data may also be inserted into time slots. Dropping and insertion may be performed to replace existing time slot data or to fill new time slots.