Having Both Input And Output Queuing Patents (Class 370/413)
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Patent number: 9166878Abstract: In one embodiment, an apparatus includes a network management module configured to execute at a network device operatively coupled to a switch fabric. The switch fabric may have a distributed control plane. The network management module is configured to receive a request regarding status information for a certain set of network resources identified with a virtual or logical identifier. The network management module is configured to generate and send a corresponding query for status information to a set of physical elements that encompass and may be larger than the certain set of network resources and collect responses to that query. The network management module is configured to construct a response to the request from the status information in the collected responses to the query. The constructed response includes only information related to the original request.Type: GrantFiled: December 23, 2010Date of Patent: October 20, 2015Assignee: Juniper Networks, Inc.Inventors: Dana Cook, Chris Cole, David Nedde
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Patent number: 9166914Abstract: A mechanism is provided in a data processing system for shared buffer affinity for multiple ports. The mechanism configures a physical first-in-first-out (FIFO) buffer with a plurality of FIFO segments associated with a plurality of network ports. The plurality of network ports share the physical FIFO buffer. The mechanism identifies a FIFO segment under stress within the plurality of FIFO segments. The mechanism reconfigures the physical FIFO buffer to assign a portion of buffer space from a FIFO segment not under stress within the plurality of FIFO segments to the FIFO segment under stress.Type: GrantFiled: December 9, 2013Date of Patent: October 20, 2015Assignee: International Business Machines CorporationInventors: Omar Cardona, Andres Herrera, Pedro V. Torres, Rafael Velez
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Patent number: 9160699Abstract: A method of distributing messages from a server system to a plurality of client systems comprises defining a quality of service (QoS) level for messages provided by the messaging system to the client system, defining a message processing capacity provided by a client to the messaging system, and degrading the QoS level of messages in the event that the client system does not provide the defined message processing capacity to the messaging system.Type: GrantFiled: June 2, 2006Date of Patent: October 13, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Ian Gerald Craggs
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Patent number: 9117037Abstract: An interface apparatus, a cascading system thereof, and a cascading method thereof are provided. The cascading system includes a host, a first-type interface apparatus, and a second-type interface apparatus which are serially connected. The host provides data transmission of a first and a second channel by a first controller through a first interface port. In the first-type interface apparatus, data of the first channel is transmitted to a second controller through a second interface port and then to a third interface port, and data of the second channel is directly transmitted to the third interface port through the second interface port. In the second-type interface apparatus, the data of the second channel are transmitted to a third controller through a forth interface port and then to the fifth interface port, and the data of the first channel is directly transmitted to the fifth interface port through the forth interface port.Type: GrantFiled: August 3, 2012Date of Patent: August 25, 2015Assignee: Acer IncorporatedInventor: Sip Kim Yeung
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Patent number: 9083655Abstract: Processing techniques in a network switch help reduce latency in the delivery of data packets to a recipient. The processing techniques include internal cut-through. The internal cut-through may bypass input port buffers by directly forwarding packet data that has been received to an output port. At the output port, the packet data is buffered for processing and communication out of the switch.Type: GrantFiled: March 14, 2013Date of Patent: July 14, 2015Assignee: Broadcom CorporationInventors: William Brad Matthews, Puneet Agarwal, Bruce Hui Kwan
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Patent number: 9042397Abstract: An apparatus comprising a chip comprising a plurality of nodes, wherein a first node from among the plurality of nodes is configured to receive a first flit comprising a first timestamp, receive a second flit comprising a second timestamp, determine whether the first flit is older than the second flit based on the first timestamp and the second timestamp, transmit the first flit before the second flit if the first flit is older than the second flit, and transmit the second flit before the first flit if the first flit is not older than the second flit.Type: GrantFiled: December 1, 2011Date of Patent: May 26, 2015Assignee: Futurewei Technologies, Inc.Inventors: Rohit Sunkam Ramanujam, Sailesh Kumar, William Lynch
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Patent number: 9031087Abstract: A system for optimizing response time to events or representations thereof waiting in a queue has a first server having access to the queue; a software application running on the first server; and a second server accessible from the first server, the second server containing rules governing the optimization. In a preferred embodiment, the software application at least periodically accesses the queue and parses certain ones of events or tokens in the queue and compares the parsed results against rules accessed from the second server in order to determine a measure of disposal time for each parsed event wherein if the determined measure is sufficiently low for one or more of the parsed events, those one or more events are modified to a reflect a higher priority state than originally assigned enabling faster treatment of those events resulting in relief from those events to the queue system load.Type: GrantFiled: April 19, 2011Date of Patent: May 12, 2015Assignee: Genesys Telecommunications Laboratories, Inc.Inventor: Yevgeniy Petrovykh
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Patent number: 9030936Abstract: Methods and apparatus for implementing flow control with reduced buffer usage for network devices. In response to detection of flow control events, transmission of a data unit or segment such as an Ethernet frame is preempted in favor of a flow control message, resulting in aborting transmission of the frame. Data corresponding to the entirety of the frame is buffered at the transmitting station until the frame has been transmitted (or after a delay), enabling retransmission of the aborted frame. Preemption of frames in favor of flow control messages results in earlier responses to flow control events, enabling the size of buffers to be reduced.Type: GrantFiled: June 12, 2013Date of Patent: May 12, 2015Assignee: Intel CorporationInventors: Ben-zion Friedman, Eliezer Tamir
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Patent number: 9025615Abstract: Service providers can reduce multiple overlay networks by creating multiple logical service networks (LSNs) on the same physical or optical fiber network through use of an embodiment of the invention. The LSNs are established by the service provider and can be characterized by traffic type, bandwidth, delay, hop count, guaranteed information rates, and/or restoration priorities. Once established, the LSNs allow the service provider to deliver a variety of services to customers depending on a variety of factors, for example, a customer's traffic specifications. Different traffic specifications are serviced on different LSNs depending on each LSN's characteristics. Such LSNs, once built within a broadband network, can be customized and have its services sold to multiple customers.Type: GrantFiled: September 10, 2013Date of Patent: May 5, 2015Assignee: Tellabs Operations, Inc.Inventors: Michael Kazban, Mitri Halabi, Ken Koenig, Vinai Sirkay
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Publication number: 20150110126Abstract: An electronic device communicates according to a network protocol that defines data packets, for example EtherCAT. The device has a processor for performing input control on incoming data packets and performing output control on outgoing data packets, and a shared FIFO buffer comprising a multiuser memory. An input unit receives input data, detects the start of a respective data packet, subdivides the data packet into consecutive segments, one segment having a predetermined number of data bytes, and transfers the segment to the FIFO buffer before the next segment has been completely received. The processor accesses, in the input control, the multiuser memory for processing the segment, and, in the output control, initiates outputting the output packet before the corresponding input data packet has been completely received. An output unit transfers the segment from the FIFO buffer, and transmits the segment to the communication medium.Type: ApplicationFiled: July 3, 2012Publication date: April 23, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Graham Edmiston, Hezi Rahamim, Amir Yosha
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Patent number: 8997185Abstract: An encryption sentinel system and method protects sensitive data stored on a storage device and includes sentinel software that runs on a client machine, sentinel software that runs on a server machine, and a data storage device. When a client machine requests sensitive data from the data storage device, the data storage device interrogates the sentinel software on the server machine to determine if this client machine has previously been deemed to have proper encryption procedures and authentication. If the sentinel server software has this information stored, it provides an approval or denial to the storage device that releases the data if appropriate. If the sentinel server software does not have this information at hand or the previous information is too old, the sentinel server interrogates the sentinel software that resides on the client machine which scans the client machine and provides an encryption update to the sentinel server software, following which data will be released if appropriate.Type: GrantFiled: November 27, 2012Date of Patent: March 31, 2015Inventor: Bruce R. Backa
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Patent number: 8995459Abstract: A communication system detects particular application protocols in response to their message traffic patterns, which might be responsive to packet size, average packet rate, burstiness of packet transmissions, or other message pattern features. Selected message pattern features include average packet rate, maximum packet burst, maximum future accumulation, minimum packet size, and maximum packet size. The system maintains a counter of packet tokens, each arriving at a constant rate, and maintains a queue of real packets. Each real packet is released from the queue when there is a corresponding packet token also available for release. Packet tokens overfilling the counter, and real packets overfilling the queue, are discarded. Users might add or alter application protocol descriptions to account for profiles thereof.Type: GrantFiled: June 30, 2010Date of Patent: March 31, 2015Assignee: Meru NetworksInventors: Vaduvur Bharghavan, Shishir Varma, Sung-Wook Han
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Patent number: 8995455Abstract: One method includes: (a) providing a memory storage device having a plurality of storage locations for storing information received by a plurality of sub-ports of a base port of the network device, where the memory storage device is shared among the plurality of sub-ports such that each sub-port is given access to the memory storage device at a certain phase of a system clock cycle; (b) storing a packet or a portion thereof at one of the storage locations when a sub-port that receives the packet has access to one or more of the storage locations; and (c) scrambling addresses for the memory storage locations such that a different one of the storage location is available to the sub-port of step (b) for a next write operation in a next phase when the sub-port of step (b) is given access to the memory storage device.Type: GrantFiled: November 15, 2012Date of Patent: March 31, 2015Assignee: QLOGIC, CorporationInventors: Frank R. Dropps, Craig M. Verba
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Patent number: 8976803Abstract: Embodiments of the invention are directed to monitoring resources of a network processor to detect a condition of exhaustion in one or more of the resources over a predetermined time interval and to provide an indication of the condition. Some embodiments periodically sample various resources of a network processor and from the samples calculate utilization of the network processor's memory bus and core processor, and determine if an interworking FIFO packet queue error has occurred. Such information may help network operators and/or support engineers to quickly zero in on the root cause and take corrective actions for network failures which previously could have been attributed to many different causes and that would have required significant time and effort to troubleshoot.Type: GrantFiled: April 11, 2013Date of Patent: March 10, 2015Assignee: Alcatel LucentInventors: Toby J. Koktan, William R. McEachern
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Patent number: 8976802Abstract: An arbitration technique for determining mappings for a switch is described. During a given arbitration decision cycle, an arbitration mechanism maintains, until expiration, a set of mappings from a subset of the input ports to a subset of the output ports of the switch. This set of mappings was determined during an arbitration decision cycle up to K cycles preceding the given arbitration decision cycle. Because the set of mappings are maintained, it is easier for the arbitration mechanism to determine mappings from a remainder of the input ports to the remainder of the output ports without collisions.Type: GrantFiled: March 15, 2013Date of Patent: March 10, 2015Assignee: Oracle International CorporationInventors: Pranay Koka, Herbert D. Schwetman, Jr., Syed Ali Raza Jafri
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Patent number: 8971329Abstract: A multiple channel data transfer system (10) includes a source (12) that generates data packets with sequence numbers for transfer over multiple request channels (14). Data packets are transferred over the multiple request channels (14) through a network (16) to a destination (18). The destination (18) re-orders the data packets received over the multiple request channels (14) into a proper sequence in response to the sequence numbers to facilitate data processing. The destination (18) provides appropriate reply packets to the source (12) over multiple response channels (20) to control the flow of data packets from the source (12).Type: GrantFiled: November 18, 2008Date of Patent: March 3, 2015Assignee: Silicon Graphics International Corp.Inventors: Randal G. Martin, Steven C. Miller, Mark D. Stadler, David A. Kruckemyer
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Patent number: 8971346Abstract: A data collection system for, and methods of, providing reliable store-and-forward data handling by encoded information reading terminals can utilize ad-hoc peer-to-peer (i.e., terminal-to-terminal) connections in order to store data that is normally stored on a single terminal only, in a redundant manner on two or more terminals. Each portable encoded information reading terminal can be configured so that when it captures data, a software application causes the terminal to search out nearby peer terminals that can store and/or forward the data to other peer terminals or to a data collection server, resulting in the data having been stored by one or more peer terminals that are immediately or not immediately accessible by the data-originating terminal.Type: GrantFiled: April 30, 2007Date of Patent: March 3, 2015Assignee: Hand Held Products, Inc.Inventor: Mitchel P. Sevier
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Patent number: 8964760Abstract: A network switch transfers data, which are to be transferred between nodes, in a time-division multiplex manner after allocating the data to slots, which are created by dividing a unit of time into a plurality of sections. An input unit includes a selection unit that selects a buffer unit according to an input slot in order to transfer the data input from the input port to the buffer unit, an input slot correspondence management table that stores a correspondence relationship between the input slots and the buffer units, and input port management information used to control a communication bandwidth of the input port.Type: GrantFiled: March 8, 2010Date of Patent: February 24, 2015Assignee: NEC CorporationInventor: Nobuki Kajihara
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Patent number: 8953631Abstract: An embodiment may include circuitry to permit interruption, at least in part, of a first frame from a sender to an intended recipient in favor of transmitting, at least in part, a payload of a second frame from the sender to the intended recipient, and/or processing, at least in part, one or more incoming flow control notifications. The payload may be transmitted, at least in part, to the intended recipient in one or more frame fragments. Many modifications, variations, and alternatives are possible without departing from this embodiment.Type: GrantFiled: June 30, 2010Date of Patent: February 10, 2015Assignee: Intel CorporationInventors: Ygdal Naouri, Eliel Louzoun
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Patent number: 8937964Abstract: Packets having at least one cell are switched using input queues, output queues, a switch fabric, and a controller. Each input queue stores cells to be switched, and each output queue stores switched cells. The switch fabric couples the input queues to the output queues and has memory. The switch fabric stores cells moved from the input queues to the switch fabric and stores cells based on the output queues. The controller couples to the input queues and the switch fabric and determines input priorities for cells moving from the input queues to the switch fabric and output priorities for cells moving from the switch fabric to the output queues.Type: GrantFiled: June 27, 2003Date of Patent: January 20, 2015Assignee: Tellabs Operations, Inc.Inventors: Robert B. Magill, Kenneth P. Laberteaux
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Patent number: 8914560Abstract: An IOP 14 includes a path-state determining unit 54 and a path selecting unit 55. The path-state determining unit 54 determines whether there is any path which is neither in process of data transmission nor in a prohibition period in which data transmission is prohibited for a predetermined time since the last data transmission has been completed out of multiple paths connecting a device to a communication partner device. When the path-state determining unit 54 determines that there is no path which is neither in process of data transmission nor in the prohibition period, the path selecting unit 55 selects a path which completes data transmission but does not pass through the prohibition period as a path for data transmission.Type: GrantFiled: June 20, 2012Date of Patent: December 16, 2014Assignee: Fujitsu LimitedInventor: Tadasuke Katoh
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Patent number: 8908709Abstract: In one embodiment, a method includes receiving a request to transmit data from a first queue to a second queue via a switch fabric. In response to the receiving, a wake-up signal configured to trigger a stage of a processing pipeline in communication with the second queue to change from a standby state to an active state is sent.Type: GrantFiled: January 8, 2009Date of Patent: December 9, 2014Assignee: Juniper Networks, Inc.Inventor: Gunes Aybay
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Patent number: 8908711Abstract: Techniques for using target issue intervals are provided. Request messages may identify the size of a data packet. A target issue interval may be determined based on the request messages. The target issue interval may be used to insert a delay between sending subsequent request messages.Type: GrantFiled: November 1, 2011Date of Patent: December 9, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventor: Michael L Ziegler
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Patent number: 8885472Abstract: The systems and methods described herein allow for the scaling of output-buffered switches by decoupling the data path from the control path. Some embodiment of the invention include a switch with a memory management unit (MMU), in which the MMU enqueues data packets to an egress queue at a rate that is less than the maximum ingress rate of the switch. Other embodiments include switches that employ pre-enqueue work queues, with an arbiter that selects a data packet for forwarding from one of the pre-enqueue work queues to an egress queue.Type: GrantFiled: June 15, 2012Date of Patent: November 11, 2014Assignee: Broadcom CorporationInventors: Bruce Kwan, Brad Matthews, Puneet Agarwal
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Patent number: 8885657Abstract: Back pressure is mapped within a network, and primary bottlenecks are distinguished from dependent bottlenecks. Further, the presently disclosed technology is capable of performing network healing operations designed to reduce the data load on primary bottlenecks while ignoring dependent bottlenecks. Still further, the presently disclosed technology teaches identifying and/or suggesting a switch port for adding a node to the network. More specifically, various implementations analyze traffic load and back pressure in a network, identify primary and dependent bottlenecks, resolve the primary bottlenecks, collect new node parameters, and/or select a switch port for the new node. Further, a command can be sent to a selected switch to activate an indicator on the selected port. New node parameters may include new node type, maximum load, minimum load, time of maximum load, time of minimum load and type of data associated with the new node.Type: GrantFiled: November 6, 2009Date of Patent: November 11, 2014Assignee: Brocade Communications Systems, Inc.Inventors: Michael Atkinson, Vineet Abraham, Sathish Gnanasekaran, Rishi Sinha
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Patent number: 8879578Abstract: Processing techniques in a network switch help reduce latency in the delivery of data packets to a recipient. The processing techniques include speculative flow status messaging, for example. The speculative flow status messaging may alert an egress tile or output port of an incoming packet before the incoming packet is fully received. The processing techniques may also include implementing a separate accelerated credit pool which provides controlled push capability for the ingress tile or input port to send packets to the egress tile or output port without waiting for a bandwidth credit from the egress tile or output port.Type: GrantFiled: December 20, 2012Date of Patent: November 4, 2014Assignee: Broadcom CorporationInventors: Brad Matthews, Puneet Agarwal, Bruce Kwan
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Patent number: 8879571Abstract: Techniques for delays based on packet sizes are provided. Request messages may identify the size of a data packet. Delays may be initiated based in part on a portion of the size of the data packet. The delays may also be based in part on target issue intervals. Request messages may be sent after the delays.Type: GrantFiled: November 1, 2011Date of Patent: November 4, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventor: Michael L. Ziegler
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Publication number: 20140307746Abstract: A network device such as a router or switch, in one embodiment, includes a timing analyzer which is capable of providing timing analysis over one or more network circuits. The timing analyzer, in one aspect, receives a data packet traveling across a circuit emulation service (“CES”) circuit such as T1 or E1 circuit. Upon obtaining an arrival timestamp associated with the data packet, the arrival timestamp is stored in a timestamp buffer in accordance with a first-in first-out (“FIFO”) storage sequence. After identifying the oldest arrival timestamp in the timestamp buffer, an offset is generated based on the result of comparison between the arrival timestamp and the oldest timestamp. The timing analyzer can also be configured to generate timing reports on-demand based on generated offset(s).Type: ApplicationFiled: April 11, 2013Publication date: October 16, 2014Applicant: Tellabs Operations, Inc.Inventors: Anthony Leonard Sasak, Christopher V. O'Brien
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Patent number: 8861515Abstract: Generally, a method and apparatus are disclosed that store sequential data units of a data packet received at an input port in contiguous banks of a buffer in a shared memory, thereby obviating any need for storing linkage information between data units. Data packets can extend through multiple buffers (next-buffer linkage information is much more efficient than next-data-unit linkage information). According to another aspect of the invention, buffer memory utilization can be further enhanced by storing multiple packets in a single buffer. For each buffer, a buffer usage count is stored that indicates the sum (over all packets represented in the buffer) of the number of output ports toward which each of the packets is destined.Type: GrantFiled: April 21, 2004Date of Patent: October 14, 2014Assignee: Agere Systems LLCInventors: Chung Kuang Chin, Yaw Fann, Roy T. Myers, Jr.
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Patent number: 8861539Abstract: Multicast traffic is expected to increase in packet networks, and therefore in switches and routers, by including broadcast and multimedia-on-demand services. Combined input-crosspoint buffered (CICB) switches can provide high performance under uniform multicast traffic. However this is often at the expense of N2 crosspoint buffers. An output-based shared-memory crosspoint-buffered (O-SMCB) packet switch is used where the crosspoint buffers are shared by two outputs and use no speedup. An embodiment of the proposed switch provides high performance under admissible uniform and non-uniform multicast traffic models while using 50% of the memory used in CICB switches that has dedicated buffers. Furthermore, the O-SMCB switch provides higher throughput than an existing SMCB switch where the buffers are shared by inputs.Type: GrantFiled: August 29, 2008Date of Patent: October 14, 2014Assignee: New Jersey Institute of TechnologyInventors: Ziqian Dong, Roberto Rojas-Cessa
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Patent number: 8855129Abstract: A method for transmitting packets, the method includes receiving multiple packets at multiple queues. The method is characterized by dynamically defining fixed priority queues and weighted fair queuing queues, and scheduling a transmission of packets in response to a status of the multiple queues and in response to the definition. A device for transmitting packets, the device includes multiple queues adapted to receive multiple packets. The device includes a circuit that is adapted to dynamically define fixed priority queues and weighted fair queuing queues out of the multiple queues and to schedule a transmission of packets in response to a status of the multiple queues and in response to the definition.Type: GrantFiled: June 7, 2005Date of Patent: October 7, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Boaz Shahar, Freddy Gabbay, Eyal Soha
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Patent number: 8848587Abstract: Multicasting network packets is disclosed. A total number of copies of a frame, t, to be sent is determined. A number of copies of the frame, m, which is less than a total number of copies of the frame, t, to be made during a current iteration is determined. M copies of the frame are made. The m copies of the frame are then sent to their destinations. The original input frame is provided as output with an indication that the frame should be returned for further processing. Processing of the frame is discontinued during an interval in which other frames are processed. The process is repeated until t copies have been sent.Type: GrantFiled: April 23, 2004Date of Patent: September 30, 2014Assignee: Alcatel LucentInventors: Mark A. L. Smallwood, Michael J. Clarke, Mark A. French, Martin R. Lea
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Publication number: 20140269751Abstract: An arbitration technique for determining mappings for a switch is described. During a given arbitration decision cycle, an arbitration mechanism maintains, until expiration, a set of mappings from a subset of the input ports to a subset of the output ports of the switch. This set of mappings was determined during an arbitration decision cycle up to K cycles preceding the given arbitration decision cycle. Because the set of mappings are maintained, it is easier for the arbitration mechanism to determine mappings from a remainder of the input ports to the remainder of the output ports without collisions.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: ORACLE INTERNATIONAL CORPORATIONInventors: Pranay Koka, Herbert D. Schwetman, JR., Syed Ali Raza Jafri
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Publication number: 20140269752Abstract: A method for performing aggregation at one or more layers starts with an AP placing at a first layer one or more received frames in a queue at the AP. When a transmit scheduler is ready to transmit an aggregated frame corresponding to the queue, the AP may iteratively select a plurality of frames selected from the one or more received frames, and aggregate at the first layer the plurality of frames into the aggregated frame. The number of frames included in an aggregated frame may be based on at least one of: a dynamically updated rate of transmission associated with a size of the frames, a class of the frames, a transmission opportunity value associated with the class of the frames and a total projected airtime for transmitting the aggregated frame. Other embodiments are also described.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: Aruba Networks, Inc.Inventors: Gautam Bhanage, Sathish Damodaran
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Publication number: 20140269750Abstract: A system and method are disclosed for assigning incoming packets to receive queues of a virtual machine. In accordance with one embodiment, a hypervisor that is executed by a computer system receives a request from a virtual machine to transmit an outgoing packet to a destination, and an identification of a receive queue of a plurality of receive queues of the virtual machine, where the identification of the receive queue is provided to the hypervisor by the virtual machine along with the request. The hypervisor obtains a flow identifier from a header of the outgoing packet that identifies a flow associated with the outgoing packet, and the outgoing packet is transmitted to the destination. The computer system then receives an incoming packet whose header specifies the flow identifier, and the hypervisor inserts the incoming packet into the receive queue using the identification of the receive queue.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: RED HAT ISRAEL, LTD.Inventor: Michael Tsirkin
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Patent number: 8837502Abstract: A port queue includes a first memory portion having a first memory access time and a second memory portion having a second memory access time. The first memory portion includes a cache row. The cache row includes a plurality of queue entries. A packet pointer is enqueued in the port queue by writing the packet pointer in a queue entry in the cache row in the first memory. The cache row is transferred to a packet vector in the second memory. A packet pointer is dequeued from the port queue by reading a queue entry from the packet vector stored in the second memory.Type: GrantFiled: May 9, 2012Date of Patent: September 16, 2014Assignee: Conversant Intellectual Property Management IncorporatedInventor: Richard M. Wyatt
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Patent number: 8837503Abstract: Disclosed are methods, systems, paradigms and structures for processing data packets in a communication network by a multi-core network processor. The network processor includes a plurality of multi-threaded core processors and special purpose processors for processing the data packets atomically, and in parallel. An ingress module of the network processor stores the incoming data packets in the memory and adds them to an input queue. The network processor processes a data packet by performing a set of network operations on the data packet in a single thread of a core processor. The special purpose processors perform a subset of the set of network operations on the data packet atomically. An egress module retrieves the processed data packets from a plurality of output queues based on a quality of service (QoS) associated with the output queues, and forwards the data packets towards their destination addresses.Type: GrantFiled: December 2, 2013Date of Patent: September 16, 2014Assignee: Unbound Networks, Inc.Inventors: Damon Finney, Ashok Mathur
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Patent number: 8837504Abstract: A buffer temporarily stores data received from a network by a receiving unit. An output mode switching unit switches the mode in which the data received by the receiving unit is output to the buffer, between FIFO and FILO, in accordance with the storage amount of data temporarily stored in the buffer. For example, if the data temporarily stored in the buffer falls below a given threshold value of the buffer, data is stored in the buffer in FIFO. If the data temporarily stored in the buffer exceeds a given threshold value of the buffer, data is stored in the buffer in FILO. A sending unit outputs data taken from the buffer in FIFO or FILO, to a network.Type: GrantFiled: November 6, 2009Date of Patent: September 16, 2014Assignee: Fujitsu LimitedInventor: Atsushi Shinozaki
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Patent number: 8824321Abstract: A multi-function device capable of executing a plurality of functions, the device comprising: a first acquisition unit configured to acquire communication state information relating to a current communication state of the multi-function device; a determination unit configured to determine: a first priority order in a case of a first state indicating that the current communication state of the multi-function device is good; and a second priority order in a case of a second state indicating that the current communication state of the multi-function device is poor, wherein the second priority order is different from the first priority order, and wherein each of the priority orders indicate each of priorities of the plurality of functions; and a data transmission unit configured to execute preferentially a transmission of data for a high-priority function earlier than a transmission of data for a low-priority function, based on the determined priority order.Type: GrantFiled: September 16, 2011Date of Patent: September 2, 2014Assignee: Brother Kogyo Kabushiki KaishaInventor: Hiroshi Shibata
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Patent number: 8817806Abstract: An apparatus and a method for flow control between a Packet Data Convergence Protocol (PDCP) layer and a Radio Link Control (RLC) layer in a communication system are provided. The method includes storing Service Data Units (SDUs) to be transferred to the RLC layer, receiving information on a capacity that is currently unused in a buffer of the RLC layer from the RLC layer, and generating Packet Data Units (PDUs) from SDUs, a capacity of which corresponds to the information, among packets stored in a buffer of the PDCP layer, and then transferring the generated PDUs to the RLC layer.Type: GrantFiled: February 1, 2011Date of Patent: August 26, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Sook Kim, Byung-Suk Kim, Seong-Ryong Kang, Chul-Ki Lee, Hong-Kyu Jeong
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Patent number: 8811386Abstract: An improved packet handler for VoIP cable modems and other high-speed digital devices includes a direct communication link via hardware among internal processing components. Incoming and outgoing digital information packets are filtered into MAC packets, voice PDU packets, and non-voice PDU packets, such that priority can be given to relaying voice packets and minimizing potential voice delay within the cable network. Hardware components, including specialized logic circuitry, modify voice packets to an appropriate signal form for subsequent signal processing or signal transmission. Proprietary bus communication protocols can also be provided to facilitate relay of packets between a central processing unit (CPU) and a digital signal processor (DSP) within a VoIP cable modem. Line cards including subscriber line interface circuit (SLIC) and subscriber line audio processing circuit (SLAC) components provide analog-to-digital (A/D) and digital-to-analog (D/A) conversion functionality.Type: GrantFiled: August 6, 2012Date of Patent: August 19, 2014Assignee: Rockstar Consortium US LPInventor: Russell T. Enderby
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Patent number: 8811417Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.Type: GrantFiled: November 15, 2010Date of Patent: August 19, 2014Assignee: Mellanox Technologies Ltd.Inventors: Noam Bloch, Gil Bloch, Ariel Shachar, Hillel Chapman, Ishai Rabinovitz, Pavel Shamis, Gilad Shainer
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Patent number: 8811418Abstract: An information processing apparatus which circulates a packet in one way among a plurality of modules connected in a ring shape, and transmits/receives the packet, each of the plurality of modules comprising a determination unit to determine whether data contained in the packet is processing-data to be processed by a processing-module of the module or configuration data for changing settings of the processing-module by an internally contained command, a discrimination unit to discriminate, when the data is determined to be the configuration data, a command type indicating the type of command contained within the configuration data as a write-mode in which the configuration data is written in the module, a read-mode in which currently set configuration data held in the module is read out, or an exchange-mode in which the currently set configuration data is read out, and then the configuration data is written, a decision unit to decide a packet transmission interval based on the command type.Type: GrantFiled: July 15, 2011Date of Patent: August 19, 2014Assignee: Canon Kabushiki KaishaInventors: Hirowo Inoue, Hisashi Ishikawa
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Patent number: 8811419Abstract: A relay device relays between two TCP communication items of a LAN side and a WAN side. When a line bandwidth of the WAN side is smaller than a line bandwidth of the LAN side, buffer overflow in a LAN side reception buffer and a WAN side transmission buffer of the relay device is prevented, and a connection is prevented from being forced to be canceled. A value of a reception window size (rwnd) described in an ACK packet returned to a transmission terminal of the LAN side is controlled based on a transmission throughput, a discarding rate, and an RTT measured in TCP communication of the WAN side, and a total size of unarranged data and a size of arranged data in a reception buffer of the LAN side and a size of untransmitted data and ACK awaiting data in a transmission buffer of the WAN side.Type: GrantFiled: March 1, 2012Date of Patent: August 19, 2014Assignee: Hitachi, Ltd.Inventor: Takashi Isobe
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Patent number: 8804751Abstract: An epoch-based network processor internally segments packets for processing and aggregation in epoch payloads. FIFO buffers interact with a memory management unit to efficiently manage the segmentation and aggregation process.Type: GrantFiled: October 2, 2006Date of Patent: August 12, 2014Assignee: Force10 Networks, Inc.Inventors: Glenn Poole, Brad Danofsky, David Haddad, Ann Gui, Heeloo Chung, Joanna Lin
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Patent number: 8793336Abstract: Information content is managed in a network-based communication system by providing a first web-based interface accessible to a first user, the first web-based interface being configured to permit the first user to designate at least one data source that is external to the first web-based interface, maintaining persistent information content on behalf of the first user including content obtained from the data source designated by the first user, and generating a second web-based interface different than the first web-based interface, wherein access to at least a portion of the persistent information content is provided to each of one or more additional users via the second web-based interface in a manner controlled by the first user via the first web-based interface to thereby facilitate interaction between the first and additional users. The first and second web-based interfaces may comprise respective content management and mobile web sites.Type: GrantFiled: February 2, 2012Date of Patent: July 29, 2014Assignee: Wireless Ink CorporationInventors: David Walker Harper, Jason James Sabella, William Henry Munch
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Patent number: 8792514Abstract: A packet switching system includes a plurality of switch fabrics connected in cascade and a plurality of buffers respectively connected to the plurality of switch fabrics. In the event of packet competition, the plurality of switch fabrics buffer the competing packets to the corresponding buffers through buffer connection ports, and forward the competing packets in excess of the number of buffer connection ports to an adjacent switch fabric through switch connection ports.Type: GrantFiled: May 23, 2011Date of Patent: July 29, 2014Assignee: Korea Advanced Institute of Science and TechnologyInventors: June Koo Rhee, Chan-Kyun Lee
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Patent number: 8792512Abstract: A multiprocessor computer system comprises a sending processor node and a receiving processor node. The sending processor node is operable to send packets comprising part of a message to a receiver, to maintain a message buffer entry in the sender comprising the sent packets, to track acknowledgment from the receiver that sent packets have been received; to maintain a timer indicating the time since message data has been sent, and to resend packets not acknowledged upon the timer reaching a timeout state. The receiving processor node is operable to send acknowledgement to the sender that received packets have been received, to track packets using a received message table to track which packets comprising part of the message have been received and whether all packets in the message have been received, and to process packets once all packets in a message are received to reassemble the received message.Type: GrantFiled: June 7, 2007Date of Patent: July 29, 2014Assignee: Intel CorporationInventors: Steven L. Scott, Dennis C. Abts, Robert Alverson, Edwin Froese
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Patent number: 8789065Abstract: Systems and methods provide an extensible, multi-stage, realtime application program processing load adaptive, manycore data processing architecture shared dynamically among instances of parallelized and pipelined application software programs, according to processing load variations of said programs and their tasks and instances, as well as contractual policies. The invented techniques provide, at the same time, both application software development productivity, through presenting for software a simple, virtual static view of the actually dynamically allocated and assigned processing hardware resources, together with high program runtime performance, through scalable pipelined and parallelized program execution with minimized overhead, as well as high resource efficiency, through adaptively optimized processing resource allocation.Type: GrantFiled: November 23, 2012Date of Patent: July 22, 2014Assignee: Throughputer, Inc.Inventor: Mark Henrik Sandstrom
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Publication number: 20140198803Abstract: A memory bus connected module for scheduling services for network packet processing is disclosed. The module can include a memory bus connection, a scheduling circuit configured to reorder network packets received from the memory bus connection and place the reordered network packets into multiple input/output queues, and multiple offload processors connected to the memory bus connection, each offload processor configured to modify network packets in the multiple input/output queues.Type: ApplicationFiled: June 22, 2013Publication date: July 17, 2014Inventors: Parin Bhadrik Dalal, Stephen Paul Belair