Abstract: A wireless speaker system that transmits and receives both analog and digital audio signals simultaneously over a single channel at frequencies above 900 MHz. The present invention advantageously uses continuously variable slope delta (CVSD) modulation to perform analog-to-digital (A/D) and digital-to-analog (D/A) conversion of audio signals in the transmitter and receiver, respectively, using complementary filters and CVSD modulation circuits in both the transmitter and receiver. Analog signals are modulated in the transmitter with a high-frequency carrier and band-pass filtered before being combined with the digitized audio signal to modulate a high-frequency carrier, i.e. over 900 MHz, which is transmitted to the receiver. Similarly, the receiver band-pass filters and demodulates the received signal to recover the analog signal components.

Abstract: Known ADPCM transcoders use processors for coding and decoding, which are time and power consuming. Such a known ADPCM transcoder comprising one processor for coding and decoding can handle four channels, while according to DECT twelve channels need to be available, which requires three known ADPCM transcoders. By delaying signals in an ADPCM transcoder, it is no longer necessary to use processors, but, instead of said processors, logic elements can be used, which is very advantageous, because of such an ADPCM transcoder being able to handle sixteen channels.

Abstract: In a transmission system for transmitting speech and music signals, an input signal is coded in a coder (11) by a time domain coder (4). The output signal of the time domain coder (4) is decoded by a time domain decoder (8) and the signal thus decoded is subtracted from the input signal by a subtracter circuit (10). To improve the coding quality, the difference signal is coded by a frequency domain coder (12) and the output signal of the time domain coder (4) and the frequency domain coder (12) are combined in a multiplexer (14) and transmitted to a receiver.

Abstract: A digital data slicer which can allow the digital sum value (DSV) of the sliced signal to approach zero is provided. The digital data slicer includes a comparator for comparing the input signal with an analog reference slice level to thereby generate the sliced signal. A DSV calculator is used to obtain the DSV of the sliced signal. A DSV processor is used to compare the DSV with a predefined tolerance window to thereby generate a digital correcting signal. A digital-to-analog (D/A) converter is then used to convert the digital correcting signal into an analog form which either raises or lowers the reference slice level to the comparator. This feedback control goes on until the DSV is within the range defined by the tolerance window.

Abstract: Disclosed is a system for selectively enabling intermediate data processing of digital signals external to an integrated circuit (IC). The system comprises a transcoder, a codec connected to the transcoder, and a data processor located externally to the IC. In response to a strobe signal, a programmable switch diverts digital signals between the transcoder and the codec to a data path from the IC to the external processor. The digital signals are formatted within the IC for processing by the external processor. The externally processed digital signals are returned to the IC via a data path from the external processor. The digital signals are then reformatted within the IC for further processing by the IC.

Abstract: A method and apparatus for receiving a signal by the ETS/HIPERLAN standard. In the method decoding is done by the BCH standard. Differential pre-coding is done and integration for cancelling transmitter side differential pre-coding is done only after BCH encoding. The apparatus contains a non-coherent demodulation a BCH decoder and an integrator.

Abstract: The present invention allows for the simultaneous transmission of two digital signals from one integrated circuit to another. The two digital signals are encoded utilizing a voltage divider circuit and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded digital signal to further decode the second digital signal.

Abstract: A method of transmitting and receiving a differential self-clocking data stream. The communications link comprises the coding of information signals onto two signal wires using two logic levels on each wire for a total of four possible coding symbols. The four symbols are utilized to encode data and control-states in both electrically differential and common mode manner upon the two signal wires. The coding sequence is chosen so as to facilitate the communications of binary data and control signals along with demarcation of each successive bit boundary by utilizing the consecutive symbol sequences which are nonrepetitive.

Abstract: An A/D converter apparatus comprising a negative feedback loop having a main signal line supplied with an input signal of a predetermined frequency and a feedback signal line passing through a feedback signal, a A/D converter connected to the main signal line for frequency-converting the input signal to a signal having a frequency different from that of the input signal to output a converted signal, a D/A converter connected to the feedback signal line for frequency-converting the feedback signal to a signal having a frequency substantially equal to that of the input signal, and a subtracter for subtracting the feedback signal from the D/A converter from the input signal to supply a subtraction result signal to the A/D converter.

Abstract: A differential demodulator that is particularly suited for a digital audio broadcasting (DAB) system, and more particularly to the Eureka-147 (DAB) system, is disclosed. The differential demodulator of the present invention receives complex data components I and Q derived from a fast fourier transform operation and converts the data components I and Q into differential data components .DELTA.I and .DELTA.Q that are accepted by data demodulating elements of the Eureka-147 system so as to be reconstructed as digital data which, in turn, are converted into an analog form that is converted and reproduced into corresponding high quality sound. The conversion of I and Q data into .DELTA.I and .DELTA.Q data is accomplished via a network of four ROMs and one RAM, wherein the ROMs are time-shared between the multiple carriers of the Eureka-147 system.

Abstract: A method and apparatus for mitigating error in a received communications signal includes an error mitigator (35) of a communication unit (12) which receives and performs mitigation based on an error indication. In a first embodiment the error indication is a phase or non-used data symbol indicating error in ADPCM data, and mitigation includes changing certain nibble values to different predetermined values. In a second embodiment the error indication may include other parameters, e.g., a CRC frame error indicator, and an error estimator (34) determines a level of corruption in the ADPCM data. The error mitigator (35) applies a predetermined set of replacement values based on the indicated level of corruption and the mitigated data is subsequently decoded in an ADPCM decoder (26).

Abstract: A multiline PCM interface for signal processing is of particular application in cordless digital telephony, type DECT, with echo cancelling and ADPCM type voice encoding. The interface incorporates a set of ADPCM encoders (COD) and ADPCM decoders (DEC), digital-to-analogue (D/A) converters and analogue-to-digital converters (A/D). The outputs of the ADPCM decoders (DEC) and the analogue-to-digital converters (A/D) are joined to form a PCM output bus (BPO), the inputs of the digital-to-analogue (D/A) converters and ADPCM encoders (COD) are joined together to form a PCM input bus (PI). The interface also includes signal processing means (MSP) which receive data bursts from the PCM output bus (BPO) and applies these same bursts to the PCM input bus (PI) with a delay of one frame and echo-free. A synchronism generator (SYGEN) allocates consecutive time slots to converters involved in the same conversation, which therefore employ the same signal processor (DSP) to perform associated conference operations.

Abstract: In a compact disc having a fixed bit rate, the bit rate is rendered substantially variable for improving the sound quality. Each sample is represented by a fixed length of 16 bits. For a sample with a bit surplus K, its data is substantially represented by upper 14 bits. For the lower two bits of the block K are allocated data of lower two bits of data of a bit deficit block L substantially represented by 18 bits.

Abstract: A method for encoding a 10-bit based picture using a circuitry or devices inherently designed for handing an 8-bit based picture. The 10-bit based input picture data is motion-compensated with 8 bits in a motion compensation circuit. From the motion-compensated picture data, representative value data and the quantization width are found by an in-bloc representative value calculation circuit and a block quantization width calculation circuit, respectively. A difference between the picture data and the representative value data is found by an adder. The difference is sent to a block quantizer where first 8-bit quantized data is generated on the basis of the quantization width so that the representative value is at a mid point of the quantization width. The first quantized data is transformed by a discrete cosine transform circuit of a difference signal encoder to generate transform coefficients which are quantized by a quantizer to generate second quantized data.

Abstract: A self initialized coder and method thereof, the coder arranged and constructed for decoding an information stream, the coder including a buffer (301) for storing a portion (403) of the information stream, a controller (313) coupled to the buffer for temporally reversing a first part (401) of the portion to provide a file header (415), and an adaptive decoder (213) having a state parameter, the adaptive decoder, coupled to the controller and the buffer, for decoding the file header to provide an estimate of the state parameter and thereafter for decoding, using the estimate, the portion to provide a decoded signal.

Abstract: A speech encoder converts analog speech signals into a stream of binary coded speech samples. A circuit for performing analog to digital conversion compares an input speech signal with a signal from a digital integrator. Based on the comparison a series of decisions are registered which indicate a step sign of the input signal. A syllabic filter generates a step magnitude according to the registered decisions. The step sign and step magnitude are combined providing a sign/magnitude representation of the input signal. When the sign/magnitude representation is integrated digitally in a decimation filter a digital representation of the analog signal is formed. A speech decoder, the antithesis of the encoder, converts binary coded speech samples into an analog waveform in a manner opposite to the A/D conversion method.

Abstract: A method and apparatus of decoding a sequence of digitally encoded data. A sequence of digitally encoded data is received. If the digitally encoded data has a value indicative of a single corresponding decoded value, the corresponding decoded value is generated. If the digitally encoded data has a value indicative of a plurality of predetermined values, a unique decoded value is selected from the plurality of predetermined decoded values. The particular one of the plurality of predetermined values selected is determined by the number of consecutively received digitally encoded data values having a value indicative of a plurality of predetermined values, and further according to the sign bit of the most recently received digitally encoded datum having a value indicative of a single corresponding decoded value.

Abstract: In a process for the serial transmission of measurement values which are continuously supplied by a sensor and which occur at the transmitter end in digital form, to a receiver, the measurement values are ascertained at such short time intervals that their deviation from the respectively precedingly ascertained measurement value can he represented generally by only two bits of which the one reproduces the sign and the other the value of the deviation. Of the measurement values which occur within a predeterminable period of time, only a respective one is completely transmitted as an absolute value while of the others only the respective incremental alteration values which are related to the one measurement value are transmitted. At the receiver end `virtual` measurement values corresponding to the measurement values occurring at the transmitter end are synthesised by the transmitted incremental values being added, correctly in respect of value and sign, to the completely transmitted absolute value.

Abstract: Noise in an ADPCM signal is muted or suppressed by modifying the magnitude of the ADPCM information during noisy conditions. In one method, the ADPCM data is changed to a predetermined magnitude value. In another method, the magnitude is reduced by a predetermined amount.

Abstract: Disclosed is a system for selectively enabling intermediate data processing of digital signals external to an integrated circuit (IC). The system comprises a transcoder, a codec connected to the transcoder, and a data processor located externally to the IC. In response to a strobe signal, a programmable switch diverts digital signals between the transcoder and the codec to a data path from the IC to the external processor. The digital signals are formatted within the IC for processing by the external processor. The externally processed digital signals are returned to the IC via a data path from the external processor. The digital signals are then reformatted within the IC for further processing by the IC.

Abstract: Digitized audio information is compressed by retrieving a first audio sample from a digitized audio signal and storing it in its entire, uncompressed, form. The next audio sample is then retrieved and a signed difference between the first audio sample value and the next audio sample value is computed. If this difference value can be represented in fewer data segments than would be required to represent the next audio sample, the difference value is stored, rather than the value of the next sample, otherwise the next sample is stored. The invention proceeds in this fashion until the entire PCM audio signal is compressed and stored. The compressed data stream is decompressed to generate an output data stream by retrieving a stored sample and examining it to ascertain whether it is a difference value or a flag which indicates that the following data represents a coded amplitude value.

Abstract: A digital image differential pulse code modulation decompressor for simultaneously generating, during a cycle of operation of said decompressor, a decompressed value for a plurality of selected pixels located on a diagonal of an array of pixels. A storage stores an error value for each selected pixel to be processed during a cycle of operation of the decompressor. A processor simultaneously generates a decompressed value for each selected pixel where the decompressed value is derived from the error value for each selected pixel and a predicted value generated by the processor for each selected pixel. The predicted value is derived from a predictor which is at least a second order, two dimensional predictor.

Abstract: A digital receiver includes an antenna for picking up signals, a converter for converting an incoming signal to a predetermined intermediate frequency, and baseband processor. The receiver further includes an analog/digital converter using oversampling relative to the bandwidth of the signal and receiving the intermediate frequency signal at its input, and decimation filters receiving the output signal from the analog/digital converter and having their outputs connected to the baseband processor.

Abstract: A balanced delta-modulation analog-to-digital conversion circuit is disclosed. A first principal integrator produces a first output signal which rises when a first control signal is generated and falls when a second control signal is generated. A second principal integrator produces a second output signal which fails when the first control signal is generated and rises when the second control signal is generated. The first and second control signals are then generated based upon the differences between the first and second output signals.

Abstract: A method of accurately recording and reproducing an analog signal having a wide dynamic range with a small amount of information first samples amplitude values of an analog waveform which are then converted to a digital signal. Plural frames of data are stored in a buffer circuit. For each frame, the differences between successive values of the digital signal are extracted to form a second digital signal having an amount of shift S common to one frame, which is established and stored in a memory. In response to the amount of shift, the second digital signal is shifted toward lower bits thereof to compress the second digital signal into a third digital signal having less bits which is stored. When the difference values are small, the amount of shift is reduced to suppress errors produced during compression. When the difference values are large dynamic range is obtained, thereby coping with great signal variations without neglecting small variations in the analog signal.

Abstract: A digital signal processor (10) includes a primary data bus (12), a primary instruction bus (14), a program control unit (16), an arithmetic unit (18), and a multiplier (20). Within the program control unit (16), multi-instruction words are issued from program memory (22) to the primary instruction bus (14). These multi-instruction words allow both logical and arithmetic instructions to be performed simultaneously. The arithmetic unit (18) includes a secondary data bus (44) which couples the arithmetic unit to the accumulator (34). The arithmetic unit (18) also includes a barrel shifter (48) having sign extension to reduce the number of operations required to shift data. The arithmetic logic unit (32) further includes complex arithmetic functions resulting in fewer operations per instruction and a multiplier (50) which is used for filtering operations in digital filtering and by the arithmetic unit (18).

Abstract: Digitized audio information is compressed by retrieving a first audio sample from a digitized audio signal and storing it in its entire, uncompressed, form. The next audio sample is then retrieved and a signed difference between the first audio sample value and the next audio sample value is computed. If this difference value can be represented in fewer data segments than would be required to represent the next audio sample, the difference value is stored, rather than the value of the next sample, otherwise the next sample is stored. The invention proceeds in this fashion until the entire PCM audio signal is compressed and stored. The compressed data stream is decompressed to generate an output data stream by retrieving a stored sample and examining it to ascertain whether it is a difference value or a flag which indicates that the following data represents a coded amplitude value.

Abstract: An information gap in an ADPCM signal is detected in one or both of a transmitter or receiver. This detection can be accomplished using a voice activity detector. When an information gap is detected, a clock signal to the encoder and/or decoder is interrupted. Alternatively, null frames can be inserted into the encoder and/or decoder. When null frames are used, it is preferable to insert comfort noise into the signal output from the decoder.

Abstract: Quantizing section 1 input audio signal data with a quantizing step width. First predicting section 14 predicts a quantization step width to be supplied to the quantizing section on the basis of the input audio signal and a number of bits of quantized data. Second predicting section 15 predicts the quantization step width on the basis of the input audio signal and a number of bits of quantized data. Coding section 2 performs Huffman coding on the quantized data. Calculating section 3 calculates the number of bits per unit time of the coded sequence signal. Selecting section 16 selects either one of the first and second predicting sections 14 and 15 on the basis of the input audio signal and the number of bits of quantized data. The first predicting section 14 further predicts another wider quantizing step width by a predetermined step width when the number of bits calculated is exceeded a predetermined value B.

Abstract: A device (100) and method (400) are set forth that provide a parity check that utilizes a nonlinear dependence upon bits other than the parity bit alone. The 4D 16-state Wei trellis code is made transparent to m.multidot.90 degree rotations by utilizing a parity generating unit that generates a parity check bit based on at least a second rotationally significant label bit. The parity check bit allows detection of errors in a first rotationally-significant label bit, i.e., allows for achievement of a rotationally transparent parity check.

Abstract: A codec uses a number of different signal processing techniques to improve audio compression. These techniques include (1) dynamically varying the size of the processing block to match the duration of the signal over which the audio signal can be considered to be substantially constant, (2) reducing the power gain of the LPC coefficients to reduce leakage of coding noise from one block into the following block, (3) allocating bits to the residual signal in accordance with both objective and subjective criteria, and (4) computing a modified residual signal to take into account the zero input response of the synthesis filters to the reconstruction noise of past blocks.

Abstract: Speech signals coded according to the principle of high-resolution long-term prediction (HLTP) have a high accuracy due to the high-resolution which causes a high complexity. The ordinary LTP method is improved by use of oversampling and determining subsegments Cd lying in a preceding segment which precedes a subsegment to be coded, for which it is the case that the number of samples Dd, expressed in the numbers of samples after oversampling, between the initial time instant of the subsegment to be coded and the initial time instant of a subsegment Cd, fulfills the relation Dd=(D*Ob)/d, in which d=2,3,4 . . . n, where n is a positive integer and where Ob and n are chosen in a manner such that Dd is always an integer. Null sample values produced initially for oversampling are given significance by means of an interpolation technique, at predetermined positions which are situated at a spacing Dd from the original samples in the subsegment to be coded.

Abstract: The present invention provides a circuit for use in an ADPCM synthesizer for generating a function of a quantization step without the use of a look-up table. Illustratively, the function is represented in a piecewise linear fashion. This permits an ADPCM synthesizer to be implemented without the use of a memory storing a look-up table for the function so the area of the synthesizer chip can be reduced.

Abstract: The present invention relates to an audio signal coding and decoding device for coding and decoding an audio signal using an adaptive differential coding system. The audio signal coding and decoding device according to the present invention comprises an adaptive differential pulse code modulation coding device for coding an audio signal, an adaptive differential pulse code modulation decoding device for decoding the audio signal coded, an integrator provided in the preceding stage of the coding device and for decreasing the variation between unit samples of the input audio signal of the coding device, and a differentiator provided in the succeeding stage of the decoding device and for processing the audio signal decoded by the decoding device so that the variation decreased by the integrator is restored to the original one. Since the integrator is provided in the preceding stage of the coding device, the variation between the unit samples of the input audio signal of the coding device is decreased.

Abstract: A system and method of compressing and decompressing a digital signal using scaled quantization of variable-sized packets of difference samples. Difference samples are generated and subdivided into packets. Packet boundaries may be moved to maximize resolution. A scale value is established for each packet, and scaled samples are generated for the difference samples. Packet boundaries, scale values, and scaled samples are then output as the compressed signal. Decompression is performed by multiplying scaled samples by the appropriate scale value. The resulting set of decompressed difference samples are sequentially added to an initial sample to produce a decompressed signal.

Abstract: A storage medium (15) has capacity capable of storing data for one frame which is formed by 2.sup.M by 2.sup.N bits. A counter circuit (12) repetitively counts bit numbers of input signals in a range of 1 to 2.sup.M by 2.sup.N, while another counter circuit (13) counts frame numbers. A signal selection circuit (14) specifies addresses the storage medium (15) in an order obtained by successively carrying out N-digit leftward rotation every renewal of the frame number with respect to the count value of the counter circuit (12) expressed in a binary number. A control signal R/W specifies reading and writing in the storage medium (15) every addressing. Thus, data signals DIN belonging to one frame written in the storage medium (15) are read when a next frame is written. The order of the read data signals is leftwardly rotated by N bits with respect to that in writing. Thus, the storage capacity of the storage medium (15) can be halved as compared with the prior art.

Abstract: A multichannel ADPCM compression and expansion device includes N sets of input and output interfaces; an ADPCM compression and expansion device which expansively converts data of K bits in a form of ADPCM signals into PCM signals of M bits in response to a first control signal and outputs the same and compressively converts data of M bits in a form of PCM signals into ADPCM data of K bits in response to a second control signal; and a control unit which divides one signal transmission slot interval into N sections and successively selects the N sets of input and output interfaces in a predetermined order during respective divided intervals divided into N sections and connects to the ADPCM compression and expansion device, and successively performs, while separating the divided interval into a former half and a latter half, a first control which generates the first control signal and sends the data of K bits to the ADPCM compression and expansion device and then returns the expansively converted M bit data to t

Abstract: A bandpass sigma-delta analog-to-digital converter (ADC) (10) includes first (11) and second (12) bandpass sigma-delta modulators, and a digital filter (13) connected to digital outputs thereof. In the illustrated embodiment, the first bandpass sigma-delta modulator (11) is a second-order, single bit bandpass modulator, and the second bandpass sigma-delta modulator (12) is a first-order, multiple-bit modulator. Coefficients in feedback paths of the first (11) and second (12) modulators are derived from a transfer function of the digital filter. In one embodiment, a receiver (50) for a system such as frequency modulation (FM) radio converts an intermediate frequency (IF) analog signal to digital in-phase (I) and quaternary (Q) signals using the bandpass sigma-delta ADC (10).

Abstract: A trellis-coded modulation system is provided in which the output of the trellis encoder is used to select a subset of a multidimensional QAM constellation. The selection process is performed such that a) the minimum square Euclidean distance between valid sequences of successive selected subsets is maximized, b) the resulting code is rotationally invariant, and c) the selected subset corresponding to a transition of the trellis encoder from a present state i to a different next state j is different from the selected subset that corresponds to a transition of the trellis encoder from a present state j to a next state i.

Abstract: Multilevel coded modulation equipment includes a transmission unit and a reception unit. The transmission unit includes a first converting unit, a first encoding unit, a first differential encoding unit, a second encoding unit, a mapping unit, and a modulating unit. The reception unit includes a demodulating unit, a first decoding unit, an inverting unit, a phase shifting unit, a second decoding unit, a differential decoding unit, a decision unit, and a second converting unit. The first converting unit distributes an input serial digital signal to a plurality of levels containing a level 1 indicating a level which is transparent to a 90.degree. phase ambiguity, and a level 2 indicating a level which is transparent to a 180.degree. phase rotation. The second converting unit receives outputs from the inverting unit, the differential decoding unit, and the decision unit, multiplexes the received signals into a serial digital signal, and outputs the serial digital signal.

Abstract: Punctured binary convolutional codes are used in a trellis coded modulation scheme to achieve spectral efficiencies as high as those of multi-dimensional codes, using simple hardware. A base rate 1/2 binary convolutional code is punctured to rate n/k. The output of the punctured encoder is mapped to a four-way partition of a 2.sup.N point two-dimensional QAM constellation. The four-way partition consists of a two-way partition in both the I and Q dimensions. The two-way partitions of each dimension are used to transmit the two level output of the rate n/k binary convolutional coder. (N-2) "uncoded" bits are transmitted by selecting the unique constellation point in a partition group. The code has an average throughput of (N-2)+2n/k bits per symbol. The invention is also applicable to trellis coded amplitude modulation schemes based on 2.sup.N possible amplitude levels provided along a one-dimensional constellation.