Abstract: The amount of memory needed for a ROM-based .pi./4 DQPSK filter is reduced by using a mapper in an IQ modulator (inverse mapper in a demodulator) that incorporates a 90.degree. phase shift for every other symbol. During the intervening symbols no additional phase shift is incorporated by the mapper. This produces a coarse precession of 90.degree. for every other symbol. The 90.degree. of coarse precession may be produced by using alternate DQPSK mappers for alternate symbols. Both mappers share a common repertoire, so no new modulation state symbols are required. During the alternate 0.degree. symbols the filter inserts a 45.degree. phase shift, but does not insert such a 45.degree. phase shift during those intervening times when the mapper (or inverse mapper) is inserting a 90.degree. phase shift. This produces a fine precession. The result is to produce a uniform precession of 45.degree. between each modulation state symbol.

Abstract: A digital radio communication system achieves low envelope variations in a transmitted signal by encoding digital information as phase angle differences in a transmitted radio signal and by constraining the maximum possible phase angle difference. This reduction in envelope variation relaxes the linearity requirements for a desired level of distortion suppression of a radio frequency (RF) amplifier means employed for transmitting the radio signal. In addition, lower envelope variations imply a higher average transmit power for a given maximum transmitted power, thereby extending range and battery life.

Abstract: A method is disclosed of demodulating a signal (20) modulated by differential quadrature phase shift keying so that two bits of information are coded into each symbol period. The method comprises using a high frequency clock to determine the time taken (t.sub.1, t.sub.2, t.sub.3, t.sub.4), for the modulated signal to execute a predetermined number of cycles, such as 21, in the symbol period (T) and comparing the time thereby determined with the time (t.sub.o) of execution of the predetermined number of cycles for an unmodulated signal.

Abstract: In a digital wireless communication system operating between a first unit and a second unit, the first unit transmits a digitally encoded RF signal at a first frequency in a plurality of a non-contiguous time slots to the second unit. The second unit receives the digitally encoded RF signals. The received RF digitally encoded signal is converted to an intermediate frequency (IF). An A to D converter samples the received IF digitally encoded signals and generates a plurality of discrete binary symbols during one of the plurality of non-contiguous time slots. A phase error signal is generated for each one of the plurality of discrete binary symbols. A frequency error signal is generated for the subsequent symbol in accordance with .DELTA.f(n+1)=.DELTA.f(n)+g.sub.1 (.crclbar.(n)-.crclbar.(n)). The conversion of the RF signal to intermediate frequency is controlled in response to the frequency error signal.

Abstract: The method is of the type featuring a parallel transmission, over a predetermined number of transmission frequencies at a low bit rate, of useful information signals modulated at a predetermined phase shift keying. A parallel transmission on all the frequencies of the frames of useful signals and of frames of reference signals is performed, a frame of reference signals being inserted between two neighboring useful frames, and each reference signals being alternated with a useful signal in each frame of the reference signals. Such a method finds particular application to the digital transmission of speech.

Abstract: A differentially encoded quadrature modulation method comprises the steps of setting an index corresponding to a phase variation value constituted of input data, forming a phase value to obtain a phase-modulated output phase value from a given table and forming a channel signal to obtain in-phase (I) and quadrature (Q) channel signals from a given table using the phase value. The apparatus for performing the above comprises a signal converter for converting serially input data into two binary signal trains, a signal forming portion for obtaining channel signals, a digital-to-analog converter for converting the respective signals into two analog signals, a baseband filter for baseband-pass-filtering the signals, a phase shifter for shifting a carrier by 90.degree., first and second multipliers for multiplying the filtered signals with the carrier and phase-shifted carrier, respectively, and a mixer for mixing the respectively obtained signals and outputting a combined signal.

Abstract: An intermediate frequency (IF) to baseband frequency signal converter for decoding an analog IF signal using phase information contained in the IF signal includes a first signal generator for generating an analog square wave signal from the IF signal. The signal converter also includes a second signal generator for generating a local phase reference signal, and a phase difference determinator for determining at a particular sampling interval a phase difference between a phase of the analog square wave signal and a phase of the local phase reference signal, wherein the phase difference represents a symbol which the signal converter has decoded from the IF signal.

Abstract: A .pi./4 shifted DQPSK modulator includes a mapping/filtering circuit (6) equipped with a mapping function and filtering function. The mapping/filtering circuit (6) allows phase information which is obtained for each symbol to be shift-input to its shift register (61, 62, 63) and sequentially reads out filter-processed filter factor data corresponding to 256 samples initially stored in a factor memory circuit (7) and allows the filter factor data to be converted to numerical values based on position information corresponding to 10 symbols output in parallel manner from the shift register (61, 62, 63). According to this circuit (6), it is possible to obtain filtered mapping data MF. Therefore, the modulator has less number of gates of the filter and can be embodied with a very simplified compact circuit configuration.

Abstract: The preferred embodiment modem is an all hardware modulator which receives as its input two baseband drive signals, I and Q, which can come from a ROM filter or any other digital filter. Instead of storing modem responses in a ROM, multiplexers for the I and Q channels are used in combination with a control circuit to essentially perform as sine/cosine modulators for the baseband signal. The inputs into the I channel multiplexer include a non-inverted I signal, an inverted I signal, and a mid-value signal. The Q channel multiplexer has applied to it a non-inverted Q signal, an inverted Q signal, and a mid-value Q signal. Two-bit counters are applied to the control terminals of the I and Q multiplexers, where the 2-bit counters are clocked by a sample frequency. In one embodiment, the sample frequency is chosen to be four times the carrier frequency. The counter for the Q channel begins one count behind the I channel counter, thus giving a 90.degree. phase shift for the Q channel.

Abstract: A method for demodulating the carrier signal of powerline communication networks. The method involves demodulating an HDLC data body that had been modulated through differential phase shift keyed modulation. Under the method, the data body is split with data input into a single bit digital delay circuit which outputs a delayed or "previous" binary data bit. A "present" binary data bit is input to one input of an XNOR circuit and the previous binary data bit is input into a second input of the XNOR circuit. When the present binary data bit and the previous binary data bit have unlike phases the XNOR circuit outputs a first binary data bit value. When the present binary data bit and the previous binary data bit have like phases, the XNOR circuit outputs a second binary data bit value. Preferably, the demodulated data is input into a post detection filter.

Abstract: The invention provides a method and apparatus for transmitting digital signal information to a receiver using a plurality of antennas. The invention involves applying a channel code to a digital signal producing one or more symbols. A plurality of symbol copies is made and each copy is weighted by a distinct time varying function. Each antenna transmits a signal based on one of the weighted symbol copies. Any channel code may be used with the invention, such as a convolutional channel code or block channel code. Weighting provided to symbol copies may involve application of an amplitude gain, phase shift, or both. The present invention may be used in combination with either or both conventional interleavers and constellation mappers.

Abstract: Receiver (5) for digital signals which comprises a differential decoding circuit deinterleaving and convolution decoding circuit for received digital signals. The differential decoding circuit restores each received symbol to the original phase it had on transmission. This permits the calculation of optimum metrics(M.sub.k.sup.a,M.sub.k.sup.b)which are used by convolution decoding circuit to provide optimum decoding of received symbols.

Abstract: In a communication unit (200) that coherently demodulates differentially-encoded modulated signals (201) to produce soft symbols (210) including first and second soft symbols, a method and associated apparatus, for use by the communication unit (200), converts the soft symbols (210) into soft bits (212). A quality measure (305) is determined for at least the first soft symbol (210) indicating when the quality for the first soft symbol (210) is favorable and when the quality for the first soft symbol (210) is unfavorable. The first and second soft symbols (210) are processed in a forward direction in time (208) to produce the soft bits (212) when the quality measure (305) for the first soft symbol (210) is favorable. The first and second soft symbols (210) are processed in a reverse direction in time (209) to produce the soft bits (212) when the quality measure (305) for the first soft symbol (210) is unfavorable.

Abstract: A dual-mode radiotelephone terminal includes a .pi./4-shift DQPSK modulator (11). A dual-mode modulation is achieved by mixing an output of a transmitter oscillator (16) with an output of an offset oscillator (18) to form an injection signal (LO) at a final transmitter frequency, the injection signal being further modulated with a quadrature modulator in a digital mode of operation. In an analog mode of operation the transmitter oscillator or the offset oscillator is frequency modulated and the quadrature modulator is disabled with a bias signal, thereby passing the frequency modulated injection signal without substantial attenuation. The LO signal is regenerated and also phase shifted with a circuit (35) having a frequency multiplier (30) and a frequency divider (34). The circuit outputs two local oscillator (LO) signals (LOA and LOB), each of which directly drives an associated quadrature mixer (36, 38) of the modulator.

Abstract: A .pi./4-DQPSK differential phase state encoder/decoder (Codec) is presented which can be implemented using a small number of logic gates. The phase state Codec acts upon data in the transmitter and in the receiver of a .pi./4-DQPSK modulating system whereby the use of a look-up table technique or other off-line procedure to ensure proper phase transitions is not required. The phase state Codec is configured to ensure compliance with the IS-54 standard as well as other similar standards.

Abstract: A digital modulator in which symbols representing bits are encoded and assigned to respective points of constellation of points representing the modulation scheme. The quadrature components of a vector representing each of the constellation points are contained in a truth table (14) in which the columns comprise the respective constellation points and the rows comprise the relative in-phase and quadrature component values. In response to the assignment of a symbol to a constellation point the appropriate column in the truth table is read out in parallel as a binary word and the bits of the word are applied to respective first stages (S10) of a plurality of shift registers (SR1 to SR8) which store the histories of the respective component values for the previous (N-1) symbols.