Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.

Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.

Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.

Abstract: An apparatus includes first and second receiver circuits and a decision circuit. The first receiver circuit is configured to generate a first data symbol from a particular input data symbol of a plurality of input data symbols included in an input signal. The second receiver circuit is configured to generate a second data symbol from the particular input data symbol. The decision circuit is configured to select, using respective values of one or more previous output data symbols, either the first or second data symbol as a current output data symbol. In response to a change in value between successive input data symbols, the first and second receiver circuits are configured to generate the first and second data symbols with respective data valid windows with different durations.

Abstract: A transimpedance amplifier converts an input current to a differential signal and outputs the differential signal. The transimpedance amplifier includes a single-ended amplifier configured to convert a current signal to a voltage signal, a first feedback circuit configured to generate a bypass current, a differential amplifier circuit configured to generate the differential signal in accordance with the difference between the voltage signal and a reference voltage signal, and a detector circuit configured to detect a start and an end of a burst optical signal. The detector circuit detects the end of the burst optical signal based on a peak value of the positive-phase component and a peak value of the negative-phase component and switches the time constant of the first feedback circuit from a first time constant to a second time constant smaller than the first time constant in response to detecting the end of the burst optical signal.

Abstract: An apparatus includes first and second receiver circuits and a decision circuit. The first receiver circuit is configured to generate a first data symbol from a particular input data symbol of a plurality of input data symbols included in an input signal. The second receiver circuit is configured to generate a second data symbol from the particular input data symbol. The decision circuit is configured to select, using respective values of one or more previous output data symbols, either the first or second data symbol as a current output data symbol. In response to a change in value between successive input data symbols, the first and second receiver circuits are configured to generate the first and second data symbols with respective data valid windows with different durations.

Abstract: Provided are a memory device and a memory bank comprised of a local data bus, a segmented global data bus coupled to the local data bus, and a section select switch that is configurable to direct a signal from the local data bus to either end of the segmented global data bus. Provided also is a computational device comprising a processor and the memory device and optionally a display. Provided also is a method in which a signal is received from a local data bus, and a section select switch is configured to direct the signal from the local data bus to either end of a segmented global data bus.

Abstract: A transformer (2A) outputs differential signals of a positive phase signal (Vout2Ap) having phase ?1+90° and a negative phase signal (Vout2An) having phase ?1?90°. A transformer (2B) outputs differential signals of a positive phase signal (Vout2Bp) having phase ?2+90° and a negative phase signal (Vout2Bn) having phase ?2?90°. An adding circuit (3) composes a pair of differential output signals, as signals corrected in phase error (?1??2) generated in the transformers (2A, 2B), in a manner of summing up vectors of two pairs of the differential signals outputted from the transformers (2A, 2B) for the positive phase signal and the negative phase signal, respectively.

Abstract: This disclosure relates to the field of amplifiers for multi-level optical communication and more particularly to techniques for trans-impedance amplifiers (TIA) with gain control. The claimed embodiments address the problem of implementing a low cost TIA that exhibits high linearity, low noise, low power, and wide bandwidth. More specifically, some claims are directed to approaches for providing TIA gain control using a plurality of inverter-based replica gain control cells controlled by a feedback loop to manage the current into the amplifying output stage and thereby the TIA output voltage.

Abstract: Performing quadrature combining and adjusting including: a plurality of mixing circuits configured to generate a plurality of frequency converted signals; at least one mixing circuit of the plurality of mixing circuits is configured with a plurality of paths, each path representing one linearity mode; and a plurality of combining circuits configured to combine the plurality of frequency converted signals to generate a differential baseband output signal.

Abstract: Offset measurement and cancellation circuitry is employed in a transimpedance amplifier (TIA) circuit for directly measuring the offset in the TIA input voltage and for canceling the offset from the TIA output voltage. Employing the offset measurement and cancellation circuitry eliminates the need to use large transistors in the input stage of the TIA in order to reduce or eliminate the offset, which can increase noise and reduce Rx sensitivity. The offset measurement and cancellation circuitry of the invention obviate the need of making a tradeoff between the amount of noise and the magnitude of the offset that will be tolerated. The offset measurement and cancellation circuitry also eliminate the need for additional overhead in the decision threshold in order to avoid false triggering of the decision circuitry of the optical receiver due to noise.

Abstract: Methods and apparatus for reducing sensitivity to nonlinearities in the receiver of a digital communications system are disclosed. One aspect can be referred to as a Post-Distortion Decision Feedback Equalizer (PDFE). A gain stage is often implemented as a variable gain amplifier (VGA), and can introduce significant nonlinearities, a problem exacerbated by signals with a large peak-to-average ratio (PAR). One embodiment provides feed forward information from the VGA regarding its status to a DFE, and the DFE adjusts its filtering based on the provided information. The advantages are also applicable to fixed-gain amplifiers and to transversal filters.

Abstract: According to at least one example embodiment a two phase calibration approach is employed for calibrating an input/output interface having multiple single-ended receivers. During a first phase, amplifier offset calibration is applied to each of the multiple single-ended receivers. During a second phase, reference voltage calibration is applied to a single-ended receiver of the multiple single-ended receivers to determine a calibration reference voltage value. The calibration reference voltage value is then employed in each of the multiple single-ended receivers during an active phase of the input/output interface.

Abstract: A detecting circuit includes: a first offset generating circuit, arranged to apply a first offset to an input signal pair and accordingly generate a first output signal pair; and a first sampling circuit, coupled to the first offset generating circuit, the first sampling circuit arranged to sample the first output signal pair to generate a first sampling signal, wherein the first sampling signal is utilized to identify a data signal on the input signal pair, and the first sampling circuit is controlled by a first signal that is irrelevant to the input signal pair.

Abstract: In a high-impedance communications interface, driver energy consumption is proportional to the number of signal transitions. For signals having three or more distinct levels, it is possible for a signal driver to salvage energy from some downward signal transitions and reuse it on some subsequent upward signal transitions. To facilitate this energy-conserving behavior, communication is performed using group signaling over sets of wires using a vector signaling code, with the design and use of the vector signaling code insuring that energy availability is balanced with energy demand.

Abstract: Receiver design techniques are provided that are capable of producing relatively efficient, linear radio frequency (RF) receivers. During a design process, components of an analog receiver chain and digital nonlinearity compensation techniques are considered together to achieve reduced power consumption in the receiver.

Abstract: Methods for receiving a signal and a detection circuit are disclosed. The detection circuit and related methods may be useful for the fast and accurate receiving of data signals. The detection circuit generally comprises a first circuit having a first time constant, a second circuit having (i) a common input with the first circuit and (ii) a second time constant, the second time constant being less than the first time constant, and a switch configured to (i) charge the first circuit with an input signal when the switch is in a first state, and (ii) charge or discharge the second circuit with the input signal when the switch is in a second state, the switch having the second state when the input signal is no longer received at the common input.

Abstract: An open loop envelope tracking system calibration technique and circuitry are proposed. A radio frequency power amplifier receives a modulated signal. An envelope tracker power converter generates a modulated power amplifier supply voltage for the radio frequency power amplifier based on a control signal derived from the modulated signal. A first output power and a second output power of the radio frequency power amplifier are measured when the control signal is respectively delayed by a first delay period and a second delay period. A sensitivity of the output power of the radio frequency power amplifier is near a maximum near the first delay period and the second delay period. The first delay period and/or the second delay period are adjusted until the first output power substantially equals the second output power. The first delay period and the second delay period are used to obtain a calibrated fine tuning delay offset.

Abstract: Disclosed is a method and apparatus for reducing outbound interference in a broadband powerline communication system. Data is modulated on first and second carrier frequencies and is transmitted via respective first and second lines of the powerline system. A characteristic of at least one of the carrier signals (e.g., phase or amplitude) is adjusted in order to improve the electrical balance of the lines of the transmission system. This improvement in electrical balance reduces the radiated interference of the powerline system. Also disclosed is the use of a line balancing element on or more lines of the powerline system for altering the characteristics of at least one of the power lines in order to compensate for a known imbalance of the transmission system.

Abstract: An RF transmitter (10) includes an RF amplifier (28) that generates an amplified RF signal (36) including a linear RF signal (92) and a spurious baseband signal (94). The spurious baseband signal (94) interacts with bias feed networks (56, 66) to cause the RF amplifier (28) to generate an unwanted RF distortion at or near the allocated RF bandwidth. A baseband compensation signal (98) is generated and equalized in an adaptive equalizer (102) then fed to the RF amplifier (28). A feedback signal (46) is obtained from the RF amplifier (28) and used to drive the adaptive equalizer (102). A feedback loop causes the adaptive equalizer to adjust a baseband signal (24, 32) supplied to the RF amplifier (28) so that the RF distortion is minimized.

Abstract: A data receiving circuit that can accurately obtain a data signal corresponding to information data from a high speed high density transmitted signal, and a semiconductor device including the data receiving circuit. The amplitude of a first differential signal corresponding to a level difference between a pair of received differential signals, generated in a first differential stage, is amplified and binalized to obtain a received data signal. A second differential signal corresponding to the level difference between the received differential signals, and a third differential signal which is a phase-inverted signal of the second differential signal are generated in a second differential stage provided separately, and a current corresponding to the second differential signal and a current corresponding to the third differential signal are discharged into the respective ones of the pair of transmission lines, thereby suppressing the amplitudes of the received differential signals.

Abstract: Methods and apparatus are disclosed for transitioning a receiver from a first state to a second state using an in-band signal over a differential serial data link.

Abstract: Methods for detecting and/or indicating the presence of valid data and threshold setting and data detection circuitry are disclosed. The threshold setting and data detection circuitry and related methods may be useful for fast and accurate reception of optical signals. The detection circuit generally comprises (i) a first circuit configured to regulate or control a DC offset of a differential input signal, and (ii) a second circuit coupled to the first circuit, the second circuit configured to indicate the presence of a data signal at the differential input signal when a voltage difference between true and complementary nodes of the differential input signal is above a predetermined threshold.

Abstract: In the transmitter, receiver and interface system capable of selective adoption of a differential current driving scheme and a differential voltage driving scheme, a differential current driving scheme and a differential voltage driving scheme can be selectively adopted in one semiconductor chip depending upon the states of the transmission lines, so that effective data transmission is possible and common parts can be shared, whereby a design time can be shortened and a layout area can be reduced.

Abstract: A video signal and an audio signal are TMDS transmitted from a source device to a sink device. Through a reserved line and a HPD line provided separately from a TMDS transmission line, an Ethernet™ signal is bidirectionally transmitted, and also, a SPDIF signal is transmitted from the sink device to the source device. The Ethernet™ signal bidirectionally transmitted between Ethernet™ transmitter/receiver circuits is differentially transmitted by an amplifier and is received by the amplifier. The SPDIF signal from a SPDIF transmitter circuit is common-mode transmitted from an adder and is received by the adder to be supplied to the SPDIF receiver circuit.

Abstract: A receiver circuit. A receiving stage is coupled to a first supply voltage and an input signal, and operative to generate a first intermediate signal from the input signal based on the first supply voltage. A compensation stage is coupled to a second supply voltage and the first intermediate signal, and operative to generate a second intermediate signal by adjusting duty cycle of the first intermediate signal upon detecting changes in the first supply voltage to compensate for the changes in the first supply voltage. An outputting stage is coupled to the second supply voltage and operative to generate an output signal based on the second supply voltage upon receiving the second intermediate signal. A voltage of the output signal is adjusted to a level of the second supply voltage and the output signal has a 50% duty cycle.

Abstract: A circuit for down-converting an RF signal to a baseband signal includes a trans-admittance amplifier adapted to receive the RF signal and generate in response a pair of differential current signals. The circuit further includes a trans-impedance amplifier having at least four mixers and at least four linear amplifiers. The four mixers frequency down-convert the pair of differential current signals to generate four pairs of differential baseband current signals, wherein each pair of the differential baseband current signals has a different phase and is associated with each of the linear amplifiers. Additionally, the circuit includes a summing block that generates an in-phase signal using a first weighted sum of the four different baseband current signals and a quadrature signal using a second weighted sum of the four different baseband current signals. The circuit further includes an analog-to-digital converter for converting the in-phase and quadrature signals to respective digital representations.

Abstract: Traditionally, for multi-band communication systems, independent signal chains for each of the different bands are employed. By using such an architecture, there are a large number of components, and there is substantial power consumption. Here, transmit processor is provided that enables transmission across multiple bands using few components (namely, fewer signal chains), while also provided for digital predistortion.

Abstract: A communication system is provided that includes a transmitter device and a receiver device. The transmitter device transmits input data as a transmitted signal having the known non-linear distortion (NLD) characteristic. The receiver receives a received signal that represents a channel affected version of the transmitted signal and that has the known NLD characteristic. The received signal includes power amplifier distortion (PAD) induced by the transmitter device's power amplifier. The receiver is designed to iteratively estimate, based on the known NLD characteristic, remaining PAD caused by the power amplifier, and to iteratively cancel estimated PAD to reduce PAD in the received signal.

Abstract: Methods and systems for split voltage domain receiver circuits are disclosed and may include amplifying complementary received signals in a plurality of partial voltage domains. The signals may be combined into a single differential signal in a single voltage domain. Each of the partial voltage domains may be offset by a DC voltage from the other partial voltage domains. The sum of the partial domains may be equal to a supply voltage of the integrated circuit. The complementary signals may be received from a photodiode. The amplified received signals may be amplified via stacked common source amplifiers, common emitter amplifiers, or stacked inverters. The amplified received signals may be DC coupled prior to combining. The complementary received signals may be amplified and combined via cascode amplifiers. The voltage domains may be stacked, and may be controlled via feedback loops. The photodetector may be integrated in the integrated circuit.

Abstract: A differential signal detecting device includes a secondary amplifier; a front-end receiver and a final amplifier which are respectively connected to the secondary amplifier; and a signal outputter which is connected to the final amplifier. The front-end receiver receives two externally inputted channels of differential signals and an externally inputted reference threshold voltage, differentiates and transduces the two channels of differential signals. The secondary amplifier receives and amplifies the signals which are outputted by the front-end receiver, and outputs the signals amplified again. The final amplifier differentiates and amplifies the signals outputted by the secondary amplifier and outputs the two channels of differentiated signals. The signal outputter receives the two channels of differentiated signals which are outputted by the final amplifier and processes the two channels of differentiated signals with a logical conjunction before outputting.

Abstract: A signal receiver having a gain control circuit comprising: detection means configured to form a representation of the excess amplitude during a training period of a signal received by the receiver; a first gain stimulus generator configured to generate a first gain stimulus in dependence on the excess amplitude detected by the detection means during the training period; averaging means configured to estimate the average of the signal received by the receiver during the training period; a second gain stimulus generator configured to generate a second gain stimulus in dependence on the average estimated by the averaging means during the training period; and a gain control signal generator configured to generate a gain control signal for the receiver in dependence on the first gain stimulus and the second gain stimulus.

Abstract: Methods and systems for split voltage domain transmitter circuits are disclosed and may include amplifying a received signal in a plurality of partial voltage domains. Each of the partial voltage domains may be offset by a DC voltage from the other partial voltage domains. A sum of the plurality of partial domains may be equal to a supply voltage of the integrated circuit. A series of diodes may be driven in differential mode via the amplified signals. An optical signal may be modulated via the diodes, which may be integrated in a Mach-Zehnder or a ring modulator. The amplified signals may be communicated to the diodes, connected in a distributed configuration, via even-mode coupled transmission lines. The partial voltage domains may be generated via stacked source follower or emitter follower circuits. The voltage domain boundary value may be at one half the supply voltage due to symmetric stacked circuits.

Abstract: A disclosed radio communication apparatus includes an amplifier configured to amplify a signal received via one of multiple channels including a channel where frequency hopping is conducted; a signal strength measurement circuit configured to measure signal strength of the received signal; and a gain value computation unit configured to compute a gain value for the amplifier based on the signal strength measured by the signal strength measurement circuit. The gain value computation unit is configured to use values specific to the respective channels as coefficients of a function to compute the gain value.

Abstract: A receiver circuit includes a first slicer coupled to receive data signals from a signal path and a reference voltage from a reference voltage path that is separate from the signal path. The first slicer is configured output a logic value based on a comparison between a voltage of the data signal and the reference voltage. The receiver circuit further includes a reference voltage generator configured to generate the reference voltage. The reference voltage generator is configured to dynamically generate the reference voltage based on logic values of previously received signals during operation in a first mode. During operation in a second mode, the reference voltage generator is configured to generate and provide the reference voltage as a static voltage.

Abstract: A receiver includes: a first amplifier for amplifying an input signal and outputting an output signal; a clock generator for generating a clock signal corresponding to a period of the output signal; a judger for outputting a first logical value or a second logical value in accordance with a phase lead or phase lag which has been occurred at a crossing point of the positive-phase signal and the negative-phase signal of the output signal upon rising or falling the clock signal; a detector for outputting a difference value between a time for which the judgment signal has the first logical value and a time for which the judgment signal has the second logical value; and an adjustor for adjusting reference voltages of a positive-phase signal and a negative-phase signal of the input signal in accordance with the difference value output from the detector.

Abstract: Provided is a discrete time receiver having a structure capable of processing various broadband signals. The discrete time receiver uses a discrete time filter having a sampling frequency in a constant range so as to process a signal having an input frequency in a wide range and a wide bandwidth, so that it is possible to reduce current consumption and the area of the discrete time receiver. Since the discrete time receiver is easily integrated with a digital device, it is easy to design a chip using system on chip (SoC).

Abstract: According to one embodiment, a compact low-power receiver comprises first and second analog circuits connected by a digitally controlled interface circuit. The first analog circuit has a first direct-current (DC) offset and a first common mode voltage at an s output, and the second analog circuit has a second DC offset and a second common mode voltage at an input. The digitally controlled interface circuit connects the output to the input, and is configured to match the first and second DC offsets and to match the first and second common mode voltages. In one embodiment, the first analog circuit is a variable gain control transimpedance amplifier (TTA) implemented using a current mode to buffer, the second analog circuit is a second-order adjustable low-pass filter, whereby a three-pole adjustable low-pass filter in the compact low-power receiver is effectively produced.

Abstract: A circuit and method are provided to control the strength of signals from an array of photo-detectors (PDs) in an optical navigation sensor. The circuit includes a number of transimpedance-amplifiers (TIAs) each coupled to an output of at least one PD to receive a current signal therefrom and generate a signal in response thereto. A controller coupled to outputs of the TIAs receives the signals and executes an algorithm to adjust gain of a signal processor coupled to the array. In one embodiment, the signal processor includes differential transimpedance-amplifiers (DIFF-TIAs) each including inputs coupled to receive current signals from the array, and the controller outputs a control signal to adjust a time over which the DIFF-TIAs and the TIAs integrate the current signals. Optionally, the signal processor includes gain-amplifiers coupled to the DIFF-TIAs and TIAs, and the controller outputs a signal to adjust gain thereof.

Abstract: A circuit and method are provided to control the strength of signals from an array of photo-detectors in an optical navigation sensor. In one embodiment, the method includes receiving a current signal from an automatic gain control (AGC) photo-detector and generating an AGC signal in response thereto; generating an illumination control signal in response to the AGC signal; and coupling the illumination control signal to an illuminator configured to illuminate at least a portion of an array of photo-detectors with light reflected from a surface to sense displacement of the optical navigation sensor relative to a surface, and adjusting illumination from the illuminator. Other embodiments are also disclosed.

Abstract: A detecting circuit includes: a first offset generating circuit arranged to apply a first offset to an input signal pair comprising a positive input signal and a negative input signal and accordingly generate a first output signal pair comprising a first positive output signal and a first negative output signal; and a first sampling circuit coupled to the first offset generating circuit, the first sampling circuit arranged to sample a difference in voltage between the first positive output signal and the first negative output signal to generate a first sampling signal, wherein the first sampling signal is utilized to identify a data signal on the input signal pair.

Abstract: A dual mode RF transceiver is provided. The dual mode RF transceiver comprises an antenna, a differential low noise amplifier (LNA), a local oscillator and a dual mode differential mixer. The differential LNA receives an RF signal from the antenna to generate a differential amplified RF signal. The dual mode differential mixer comprises a switch module, a plurality of fundamental mixers and a plurality of sub-harmonic mixers. The fundamental mixers are activated in a first receiving mode to generate a first differential baseband signal according to a multiphase local oscillating (LO) signal from the local oscillator and the differential amplified RF signal. The sub-harmonic mixers are activated in a second receiving mode to generate a second differential baseband signal according to the multiphase LO signal from the local oscillator and the differential amplified RF signal. An RF signal receiving method is disclosed herein as well.

Abstract: A closed loop power output calibration system for variable power output wireless devices. The wireless device includes a wireless transceiver having a transmit core coupled to a discrete power amplifier. Power detection circuitry formed in the wireless transceiver provides a detected power level of the power amplifier, and a reference power level, both of which are converted to digital signals using existing I and Q signal analog to digital converters in the receiver core. The digital signals are processed to cancel power distortion and temperature effects to provide a resulting power feedback signal. Corrective control signals are generated in response to the power feedback signal relative to a desired power output level. The gain in the transmit core is then adjusted in response to the corrective control signals such that the power amplifier outputs the target output power level.

Abstract: A frequency translation filter includes a baseband filter circuit, a clock generator, and a switching circuit. The baseband filter circuit is operable to provide a baseband filter response. The clock generator is operable to generate multiple-phase clock signals at a desired frequency. The switching circuit is operable to frequency translate the baseband filter response of the baseband filter circuit to a high frequency filter response in accordance with the multiple-phase clock signals.

Abstract: Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition.

Abstract: A method for partitioning gain for a wireless radio frequency integrated circuit (RFIC) is provided. The method includes receiving an overall gain at the RFIC from a baseband controller that is coupled to the RFIC. The overall gain is then partitioned in the RFIC.

Abstract: Antenna identification data is transferred over a regular channel that is normally used for transferring navigation signals. Modulation of the received signal is used for transferring the portable antenna parameter data. Antenna identifications and parameters are written into a portable antenna module. The antenna module is attached to a radio receiver. The antenna module and the receiver are powered up. The portable antenna module receives radio signals that are amplified in a low-noise amplifier. Then, a level of the output signal is discretely modulated in the amplitude modulator and the signal is transferred to the radio receiver. The discrete fluctuations of the level of the signal are determined in the amplitude demodulator. The fluctuation of the level of the signal carries the information about the identification parameters of the portable antenna module. An analog-to-digital conversion of the determine signal fluctuation is performed in an analog-to-digital converter.

Abstract: An improved multi-channel receiver for satellite broadcast applications or the like. In an exemplary embodiment, a primary AGC loop controls an analog sub-receiver adapted to simultaneously receive multiple signals. Multiple digital demodulators, coupled to the sub-receiver, demodulate the multiple received signals. Multiple secondary AGC loops, one for each received signal, compensate for variations in demodulated signal strengths caused by the primary AGC loop. A feed-forward AGC compensation technique generates scalar control values for scaling the demodulated signals before the demodulated signals are processed by the secondary AGC loops. This at least partially compensates for gain variations caused by the primary AGC, reducing received signal drop-outs before the secondary AGC loops can compensate for the gain variations.

Abstract: A differential radio frequency signal transmitter is provided. The differential radio frequency signal transmitter includes an oscillator, a modulator and an amplifier module. The oscillator generates a pair of differential oscillation signals. The modulator generates a pair of differential modulated signals according to an input signal and the pair of differential oscillation signals. The input signal is a digital signal. When the input signal is at a first state, the modulator outputs the pair of differential oscillation signals as the pair of differential modulated signals, and when the input signal is at a second state, the modulator outputs a constant voltage signal as the pair of differential modulated signals. The amplifier module receives and amplifies the pair of differential modulated signals and generates a pair of differential radio frequency signals, accordingly.

Abstract: A method and system are provided for reducing power amplifier induced distortion. Power amplifier induced distortion is iteratively estimated and cancelled. When the difference between the current estimated power amplifier distortion and the previous estimated power amplifier distortion is less than a convergence threshold, particular M-QAM constellation points that are still in error are determined A M-QAM constellation point correction routine is provided that can move the incorrectly estimated M-QAM constellation points that are in error towards their expected quadrants by generating updated M-QAM constellation points. The remaining estimated non-linear power amplifier induced distortion in the received signal can then be estimated and canceled.