Abstract: Systems and methods are provided for a user equipment (UE) to perform frequency offset (FO) delta tracking. For an anchor component carrier (CC), the UE wakes up to perform tracking updates on a plurality of successive DRX cycles. For the non-anchor CC, the UE determines a minimum update interval ?tupd, and schedules wake-ups on a first subset of the plurality of successive DRX cycles based on the minimum update interval ?tupd. For the first subset of the plurality of successive DRX cycles with scheduled wake-ups, the UE performs the tracking updates on the non-anchor CC and updates an FO delta between the anchor CC and the non-anchor CC. For a second subset of the plurality of successive DRX cycles without the scheduled wake-ups on the non-anchor CC, the UE applies the FO delta to correct for a frequency error.

Abstract: A Bluetooth receiver is provided. The Bluetooth receiver comprises processing circuitry configured to receive a receive signal and to determine receive symbols based on the receive signal. The Bluetooth receiver further comprises control circuitry configured to determine a frequency offset and/or a modulation index of the receive signal based on the receive signal. The control circuitry is additionally configured to control an operation mode of the processing circuitry based on the determined frequency offset and/or the modulation index of the receive signal.

Abstract: Embodiments may comprise an orthogonal frequency division multiplexing (OFDM) system operating in the 1 GHz and lower frequency bands. In many embodiments, physical layer logic may implement a new preamble structure with a new signal field. Embodiments may store the preamble structure and/or a preamble based upon the new preamble structure on a machine-accessible medium. Some embodiments may generate and transmit a communication with the new preamble structure. Further embodiments may receive and detect communications with the new preamble structure.

Abstract: A plurality of Phase Locked Loops, PLL (12, 14), are distributed across an Integrated Circuit, each receiving a common reference signal (A). A local phase error (B) of each PLL (12, 14) is connected to a phase error averaging circuit (16), which calculates an average phase error (C), and distributes it back to each PLL (12, 14). In each PLL (12, 14), two loop filters (20, 22) with different bandwidths are deployed. A lower bandwidth, high DC gain, common mode loop operates on the average phase error, and forces the PLL outputs (H) to track the phase of the common reference signal. A high bandwidth, difference mode loop operates on the difference between the local phase error (B) and the average phase error (C) to suppress phase differences between PLL outputs, minimizing interaction between them. The reference noise contribution at the output is controlled by the common mode loop, which can have a low bandwidth.

Abstract: In one example, receiver circuitry for a communication system comprises signal processing circuitry configured to receive a data signal and generate a processed data signal, and error slicer circuitry. The error slicer circuitry is coupled to the output of the signal processing circuitry, and configured to receive the processed data signal. The error slicer circuitry comprises a first error slicer configured to receive a clock signal, and output a first error signal based on a first state of the clock signal and processed data signal. The first error slicer is further configured to output a second error signal based on a second state of the clock signal and the processed data signal.

Abstract: A method for power-smart packet processing includes, in response to an event trigger signal, generating, by a state machine, a number of enable signals. The method further includes applying the enable signals to a number of single-level inferred clock (SLICK) gates to generate multiple clock signals with cycles of latency. The clock signals are applied to at least some of a number of groups of flops used for packet processing. The enable signals are clock-gated enable signals that start at consecutive cycles of a main clock, and stay active for at least one cycle of the main clock. The method further includes using flow-aware clock-gating technology (FACT) to distinctly identify logic and tables and continually variable traffic (CVT) to control packet rate and packet spacing.

Abstract: Interference-avoiding distance measurement is provided. A controller of a first wireless device is configured for wireless communication over a first transmission protocol with a second wireless device. One or more occupied channels of a second transmission protocol are identified, the first and second transmission protocols having overlapping frequency spectrums. A channel plan is constructed according to the occupied channels, the channel plan using a set of channels of the first transmission protocol that do not overlap in frequency with the one or more occupied channels of the second transmission protocol. Phase-based ranging is performed using data scanned via the channel plan. A distance measurement is indicated based on the phase-based ranging.

Abstract: Disclosed is a method and apparatus for phase error compensation having tolerance to a cyclic slip. The method includes determining first phase error candidates based on symbol phases of a first block of a received signal, determining an initial estimation error according to the first phase error candidates, determining second phase error candidates based on symbol phases of a second block of the received signal, determining a final estimation error according to the initial estimation error and the second phase error candidates, and compensating for a phase of the received signal according to the final estimation error.

Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for generating and reporting CSI.

Abstract: Technologies directed to Serializer/Deserializer (SerDes) connections and SerDes routing between digital beam forming (DBF) devices of a panel with an array of antenna elements, such as on satellite User Link panels, are described. A first DBF device is coupled to a first modem over a first SerDes link and coupled to RFFE circuitry. A second DBF device is coupled to the first DBF device over a second SerDes link. Each of the DBF devices is coupled to multiple antenna elements. The DBF devices route data between the modem and the other DBF devices, such as in a chain of DBF devices.

Abstract: The invention relates to a wireless communication device configured for use in a wireless communication system, wherein, based on one or more structural properties of a multi-panel antenna array describing how the antenna array is structured into multiple panels, a precoder is selected to be applied for a transmission from the multi-panel antenna array; and wherein an information indicative of the determined precoder is signaled to a transmit radio node; the invention further refers to a transmit radio node configured for transmitting via a multi-panel antenna array in a wireless communication system, wherein signaling indicating one or more structural properties of a multi-panel antenna array describing how the antenna array is structured into multiple panels is transmitted to the wireless communication device.

Abstract: A method and data processing system for making a machine learning model more resistant to adversarial examples are provided. In the method, an input for a machine learning model is provided. A randomly generated mask is added to the input to produce a modified input. The modified input is provided to the machine learning model. The randomly generated mask negates the effect of a perturbation added to the input for causing the input to be an adversarial example. The method may be implemented using the data processing system.

Abstract: A threat detection apparatus and a threat detection method thereof for a wireless communication system are provided. The threat detection apparatus receives an observed time difference of arrival (OTDOA) message for positioning a user equipment (UE) from a serving base station (BS), and determines that the UE connects to a false BS when the identity of the serving BS is not on the identity list. If the identity of the serving BS is on the identity list, the threat detection apparatus calculates a first distance according to the measurement report message transmitted from the UE, and calculates a second distance between the UE and the serving BS according to the OTDOA message. When the difference between the first distance and the second distance is larger than a threshold, the threat detection apparatus determines that the UE connects to the false BS.

Abstract: Some aspects of the present disclosure relate to detection of a Phase Hit and, upon detecting the Phase Hit, determining the magnitude and location of the Phase Hit. Detecting the Phase Hit may involve comparing a phase offset difference for successive pilot symbol to a detection threshold. Determination of the detection threshold may involve a Neyman-Pearson binary hypothesis testing (NP-BHT) approach. Once the magnitude and location of the Phase Hit are known, data symbols received after the location may be processed to remove the magnitude of the Phase Hit.

Abstract: An electric power substation includes a circuit breaker, an electromagnetic pulse mitigation module coupled to the circuit breaker and comprising a continuous conductive enclosure that is impervious to radiated or coupled electromagnetic energy, an input/output device housed within the electromagnetic pulse mitigation module, and a control house communicably coupled to the circuit breaker via a primary communication line and housing one or more primary relay panels.

Abstract: Provided is a transmitter performing at least feed-forward equalizing and crosstalk cancellation, the transmitter including: a main driver (20) generating waveform including data to be transmitted; and an FFE driver block (40) connected to the main driver in parallel, and generating waveform that is acquired by applying a sum of amplitude for feed-forward equalizing and amplitude for crosstalk cancellation, so as to adjust the waveform generated by the main driver.

Abstract: Exemplary aspects are directed to FM-radio circuitries and systems in which, at the receiving end of an FM broadcast transmission, circuitry is used to set the bandwidth for receiving the desired channel of the FM broadcast signal based on measured signal properties of immediately-adjacent channel(s) and based on an inverse relationship between an indication of FM modulation level of the other channel(s) and the amount for which the bandwidth is to be set. FM-signal processing circuitry such as logic/CPU circuitry, then receives the desired channel, including information carried by the FM broadcast signal, in response to setting the bandwidth based on the measured signal properties.

Abstract: A method of performing carrier frequency offset (CFO) estimation and/or time offset (TO) estimation at a radio equipment in a mobile communications system. The method allows, for each of a plurality of synchronization signal (SS) blocks (SSBs) in a SS Burst detected at said radio equipment, determining a CFO estimation and/or a TO estimation based on network information signal prediction. The method includes selecting at least some of said detected SSBs in said SSB Burst and combining the CFO estimations and/or the TO estimations to obtain improved CFO compensation and/or TO compensation for signal processing at said radio equipment.

Abstract: A radio-frequency (RF) sampling transmitter (e.g., of the type that may be used in 5G wireless base stations) includes a complex baseband digital-to-analog converter (DAC) response compensator that operates on a complex baseband signal at a sampling rate lower than the sampling rate of an RF sampling DAC in the RF sampling transmitter. The DAC response compensator flattens the sample-and-hold response of the RF sampling DAC only in the passband of interest, addressing the problem of a sinc response introduced by the sample-and-hold operation of the RF sampling DAC and avoiding the architectural complexity and high power consumption of an inverse sinc filter that operates on the signal at a point in the signal chain after it has already been up-converted to an RF passband.

Abstract: Disclosed are systems, methods, and non-transitory computer-readable media for improved data transmissions using puncturing and binary sequences. A receiving device receives a sequenced data input that includes a set of individual values and performs a puncturing of the sequenced data input, yielding a punctured sequenced data input. The receiving device calculates correlation values for the punctured sequence data input and a set of predetermined data outputs. The receiving device determines whether any of the resulting correlation values exceeds a threshold correlation value. In response to determining that the correlation value calculated based on one of the predetermined data outputs exceeds the threshold correlation value, the receiving device determines that the sequenced data input corresponds to the predetermined data output.

Abstract: A clock and data recovery circuit is disclosed. The clock and data recovery circuit includes a phase detection circuit, a first voting circuit, a low-pass filtering circuit and a phase interpolation circuit. The phase detection circuit is configured to receive a first signal and a clock signal and generate a phase signal. The first voting circuit is configured to charge at least one capacitance component according to the phase signal and generate a first voting signal according to a charging result. The low-pass filtering circuit is configured to generate a phase control signal according to the first voting signal. The phase interpolation circuit is configured to generate the clock signal according to the phase control signal.

Abstract: A method of operation in a locked-loop circuit. The locked-loop circuit includes a loop filter and a digitally-controlled oscillator (DCO) coupled to the output of the loop filter. The loop filter includes a first input to receive a digital word representing a difference between a reference clock frequency and a DCO output frequency. The method includes determining a calibration DCO codeword representing a calibration operating point for the locked-loop circuit; determining a scaling factor based on the calibration operating point, the scaling factor based on a ratio of an actual DCO gain to a nominal DCO gain; and applying the scaling factor to operating parameters of the loop filter.

Abstract: A method of operation in a locked-loop circuit. The locked-loop circuit includes a loop filter and a digitally-controlled oscillator (DCO). The loop filter includes a first input to receive a digital word representing a difference between a reference clock frequency and a DCO output frequency. The loop filter includes internal storage. The method includes selecting a desired DCO output frequency that is generated in response to a calibration DCO codeword. A start value is retrieved from the loop filter internal storage. The start value corresponds to the calibration DCO codeword. The locked-loop circuit is then started with the retrieved start value.

Abstract: The present invention relates to a method implemented by computer means of a communicating entity, for inserting a reference signal for phase tracking, said communicating entity using a discrete Fourier transformation spread orthogonal frequency division multiplexing modulator, characterized in that the method comprises: obtaining a succession of signal samples by inserting said reference signal for phase tracking within a succession of data samples, according to at least one insertion pattern chosen among pre-defined patterns with respect to predetermined criteria of communication conditions, and feeding said modulator with a succession of signal blocks obtained from said succession of signal samples, so as to apply the discrete Fourier transformation after the insertion of the reference signal for phase tracking.

Abstract: The invention relates to a wireless communication device configured for use in a wireless communication system, wherein, based on one or more structural properties of a multi-panel antenna array describing how the antenna array is structured into multiple panels, a precoder is selected to be applied for a transmission from the multi-panel antenna array; and wherein an information indicative of the determined precoder is signaled to a transmit radio node; the invention further refers to a transmit radio node configured for transmitting via a multi-panel antenna array in a wireless communication system, wherein signaling indicating one or more structural properties of a multi-panel antenna array describing how the antenna array is structured into multiple panels is transmitted to the wireless communication device.

Abstract: An HE-LTF transmission method is provided, including: determining, based on a total number NSTS of space-time streams, a number NHELTF of OFDM symbols included in an HE-LTF field; determining a HE-LTF sequence in frequency domain according to a transmission bandwidth and a mode of the HE-LTF field, where the HE-LTF sequence in frequency domain includes but is not limited to a mode of the HE-LTF field sequence that is in a 1× mode and that is mentioned in implementations; and sending a time-domain signal according to the number NHELTF of OFDM symbols and the determined HE-LTF sequence in frequency domain. In the foregoing solution, a PAPR value is relatively low.

Abstract: A method for transmission of signal is provided, the method comprising the steps of receiving one or more modulating signals, generating one or more modulated sinusoidal carrier waves with zero side bands, including one or more sine wave cycles at carrier frequency that have a predetermined one or more properties, defined for complete cycle at the beginning of each sine cycle at one or more zero voltage crossing points in accordance with the one or more values of the one or more modulating signals. The one or more predetermined properties to change, is selected from group of amplitude, frequency, phase, time period and combinations thereof.

Abstract: Systems and methods are provided for enabling lower-bandwidth hardware components to support higher data rates. In particular, aspects of the disclosed systems and methods use Raised Cosine pulse shaping in short-reach links to band limit the signal spectra and thereby enable existing, such lower-bandwidth components to support higher data rates.

Abstract: Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error decision, the phase error decision selected in response to identification of a predetermined data decision pattern.

Abstract: A Bitcoin mining hardware accelerator is described. A System on Chip implementing a Bitcoin mining hardware accelerator may include a processor core and a hardware accelerator coupled to the processor core, the hardware accelerator to mine digital currency. The hardware accelerator may include a first computational block, including a message digest datapath, wherein the first computational block is to: precompute a first summation of a 32-bit message (Wi), a 32-bit round constant (Ki), and a content of a first shifted state register (Gi?1), and store a result of the first summation in a state register (Hi). The Bitcoin mining hardware accelerator may further include a second computational block comprising a message scheduler datapath.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may determine at least one of an orthogonal frequency division multiplexing (OFDM) parameter associated with the UE or a modem function associated with a modem of the UE. The UE may control a loop bandwidth of a phase-locked loop (PLL), used to generate a tunable radio frequency (RF) carrier frequency used by the UE to communicate synchronously with a base station, based at least in part on at least one of the OFDM parameter or the modem function. Numerous other aspects are provided.

Abstract: A phase-locked loop (PLL) for generating a VCO output signal at a target frequency has been disclosed. The PLL includes at least first and second VCOs, first and second multiplexers, and a frequency divider. The first and second VCOs generate first and second output signals over first and second frequency ranges, respectively. The first multiplexer receives the first and second output signals from the first and second VCOs, respectively, and outputs the first output signal when the target frequency is in the first frequency range and the second output signal when the target frequency is in the second frequency range or less than the first frequency range. The frequency divider divides a frequency of the second output signal by a division factor to generate a third output signal. The second multiplexer outputs one of the first, second, and third output signals as the VCO output signal.

Abstract: The systems and methods disclosed herein are generally directed to the real-time symbol rate of modulation modification based on noise and interference detection on a received signal during data transmission across a network. In one embodiment, a receiving device can measure the power of affected carriers, subcarriers, and/or tones. In one embodiment, adaptive bit loading can be used such that a lower order modulation scheme can be used to overcome through the noise and increase the Signal-to-noise ratio (SNR) of the transmitted signal. In one embodiment, more throughput (for example, more bps/Hz) can be achieved in the network by using subcarriers that have a higher SNR. Further, the bit-loading can serve to maximize the data rate subject to power and bit-error ratio (BER) constraints of the network.

Abstract: An electronic device includes a clock generating circuit, a receiving circuit and a training circuit. The clock generating circuit generates a sampling clock signal, a phase-early sampling clock signal and a phase-late sampling clock signal. The receiving circuit samples received data according to the sampling clock signal, the phase-early sampling clock signal and the phase-late sampling clock signal to generate a sample result. The training circuit controls the clock generating circuit to generate the sampling clock signal and the corresponding phase-early sampling clock signal and phase-late sampling clock signal that have different phases in a plurality of different time intervals, respectively, to cause the receiving circuit to generate a plurality of sample results. The training circuit further determines a sampling phase of the sampling clock signal according to the sample results.

Abstract: A signal processing circuit includes: a processor configured to adjust phases of reception samples which is supplied at a supply interval, according to a phase adjustment amount; and a processing circuit including a finite impulse response (FIR) filter with taps and configured to process, by the FIR filter, each of the reception samples and output output symbols at an output interval different from the supply interval, the processor is configured to: derive initial values of tap coefficients for the respective taps; and derive the phase adjustment amount such that a center of centroids of the tap coefficients at respective output time points of the output symbols coincides with a center of a number of taps of the FIR filter, the tap coefficients at respective output time points of the output symbols being set according to a deviation between the supply interval and the output interval and the initial values.

Abstract: Provided are a radio-frequency integrated chip (RFIC) and a wireless communication device including the RFIC. An RFIC configured to receive a carrier aggregated receive signal having at least first and second carrier signals may include first and second carrier receivers configured to generate, from the receive signal, first and second digital carrier signals, respectively. A phase-locked loop (PLL) may output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver. The first and second carrier receivers may include first and second analog mixers, respectively, for translating frequencies of the receive signal, using the first frequency signal and the second frequency signal, respectively. Each of the first and second carrier receivers may further include a digital mixer for farther translating the frequencies of the receive signal in the digital domain.

Abstract: Embodiments of a station (STA) and method for communication in accordance with phase noise compensation are generally described herein. The STA may determine, based at least partly on one or more operational parameters, whether to perform phase noise compensation of data symbols of a received protocol data unit (PDU). For instance, the STA may compare the operational parameters with one or more thresholds. The STA may further determine a method of phase noise compensation based at least partly on one or more operational parameters. As an example, the STA may determine a type of interpolation to be used for an interpolation of phase noise estimates of pilot symbols to determine phase noise estimates of data symbols. Example operational parameters may include a signal quality metric, a carrier frequency offset (CFO) measurement and/or modulation and coding scheme (MCS).

Abstract: An apparatus in a signal receiver, such as an optical signal receiver, is provided. An adaptive equalizer provides an equalized output indicative of a received signal. A feedback component receives the equalized output and provides feedback to the adaptive equalizer. A carrier recovery component receives the equalized output from the adaptive equalizer provides estimates of symbols. The carrier recovery component is partially or fully disjoint from the feedback component, thus removing the carrier recovery component from equalizer the feedback loop. The feedback component can include an initial carrier recovery component and a phase rotation and detection component. The initial carrier recovery component generates a carrier recovery output based on the equalized output. The phase rotation and detection component performs a phase rotation based on the carrier recovery output.

Abstract: A desirable feature of a SERDES design is power savings. One way to achieve power savings is by keeping the CDR circuit OFF during most of the time when a link is active between a transmitter and a receiver. However, due to voltage supply noise, temperature fluctuations and uncorrelated crosstalk, the receiver data may shift and/or the eye may collapse if the CDR is not turned ON to take care of these modulations. To address such disadvantages, it is proposed to generate a CDR profile that can specify optimum CDR ON and OFF time so that link stability may be maintained while saving power.

Abstract: Systems and methods disclosed herein provide for adaptively applying pattern filters so that the edges are discarded only when the DFE feedback has adapted to levels that can corrupt the timing recovery. Embodiments of the systems and methods provide for a phase detector that selectively suppresses timing information based on the logic level states of the Qp and Qm data samples associated with the received signal.

Abstract: Systems, methods and apparatus are described that facilitate transmission of data between two devices within an electronic apparatus. An apparatus has a bus interface, a 3-phase encoder, and a processing circuit that can configure the 3-phase encoder for a first mode of operation in which data is encoded in a sequence of two-bit symbols, transmit a first three-phase signal representative of the sequence of two-bit symbols on each of the three wires. The processing circuit may be configured to configure the 3-phase encoder for a second mode of operation in which data is encoded in a sequence of three-bit symbols. Three-phase signal representative of the sequence of two-bit symbols or sequence of three-bit symbols on each of three wires, where a three-phase signal is in a different phase on each wire when transmitted, and a transition in signaling state occurs between transmission of each pair of symbols.

Abstract: Apparatuses and methods for adding offset delays to signal lines of multi-level communication architectures are disclosed herein. An example method may include comparing a current channel state of a channel of a multi-level communication bus with a next channel state of the channel. The example method may further include, based on the comparison, applying an offset delay to a control signal configured to control transition of a signal line of the channel from a value associated with the current channel state to a value associated with the next channel state. The example method may further include after application of the offset delay, driving the signal line to the value associated with the next channel state responsive to the control signal.

Abstract: A method is disclosed for synchronization, comprising obtaining baseband signal samples of a baseband information signal having an in-phase signal sample and a quadrature signal sample, the baseband information signal having been generated by mixing a received modulated carrier signal with a local oscillator (LO) signal having an LO frequency, the modulated carrier signal being an in-phase signal and quadrature signal having a substantially uncorrelated nature and derived from different input data sets; determining an offset frequency rotation based on an estimated residual correlation between the in-phase signal samples and the quadrature signal samples; and, deriving synchronization information from the offset frequency rotation, wherein the received modulated carrier signal is a quadrature-modulated signal with arbitrary orthogonal in-phase and quadrature signal components.

Abstract: According to an aspect, a display device with a touch detection function includes: a touch detector including first group electrodes extending in a first direction and second group electrodes extending in a second direction intersecting the first direction; a display unit that displays an image; a display controller that controls the display unit to display the image on the display unit; and a touch detection controller that detects contact or proximity of a detection target object based on mutual capacitances between the first and the second group electrodes. The touch detection controller measures a frame frequency that is a number of times frames are displayed per unit time, to sequentially output touch drive signals having a frequency corresponding to the frame frequency to the first group electrodes, and to detect the contact or proximity of the detection target object based on signals output from the respective second group electrodes.

Abstract: An apparatus includes a phase interpolator configured to receive a four-phase signal and output a six-phase signal, and a summing network configured to receive the six-phase signal and output a two-phase signal, wherein: a first phase, a third phase, and a fifth phase of the six-phase signal are summed to generate a second phase of the two-phase signal, while a second phase, a fourth phase, and a sixth phase of the six-phase signal are summed to generate a first phase of the two-phase signal.

Abstract: A method for timing recovery for a high-speed data transmission system may be provided. The method comprises receiving an analog input signal at an ADC and passing processed digital signal samples to a Viterbi detector. The method also comprises receiving at least one processed signal sample and at least two sets of at least one candidate symbol each from the Viterbi detector and/or the processed signal samples by timing error detectors and forwarding output digital signals of the timing error detectors via loop filters to related multiplexers. Furthermore, the method comprises selecting one digital signal from each of the multiplexers using a select signal generated by the Viterbi detector, and deriving a control signal controlling a sampling clock of the analog-to-digital converter by at least one of the selected digital signals from the multiplexers.

Abstract: A post-equalization phase tracking unit, for each signal block of a received series: computes beginning absolute phase rotation using equalized preceding pilot symbols; subdivides the block into a time sequence of groups of equalized symbols; initializes accumulated phase associated with the first-in-time group with the absolute phase rotation. For each group, the unit: computes a de-rotated version of each symbol using the previous group's accumulated phase used to blindly estimate a residual group phase; assigns the group's accumulated phase with a sum of the group's residual phase and the previous group's accumulated phase; estimates phase drift within the group by using at least the group's accumulated phase to compute a phase compensation signal.

Abstract: Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error indication, the phase error indication selected in response to identification of a predetermined data decision pattern.

Abstract: Provided are a method and apparatus for estimating and correcting the phase error in 5G or pre-5G communication systems providing much higher data rates compared to existing 4G communication systems including LTE systems. The existing phase error estimation scheme using a cyclic prefix in the time domain may fail to prevent performance degradation due to inter-carrier interference. In the present invention, it is possible to enhance reception performance of the receiver by estimating and correcting the phase error multiple times within a symbol using a time domain signal and by reducing the influence of inter-carrier interference.

Abstract: Systems and methods are provided for packet detection in a wireless local area network transceiver. An antenna is configured to receive a signal, having a carrier frequency. A mixer is configured to mix the received signal with one of the in-phase and quadrature components of the local oscillator to produce a corresponding one of an in-phase downconverted signal and a quadrature phase downconverted signal. A packet detector is configured to determine, from the one of the in-phase downconverted signal and the quadrature phase downconverted signal, if the signal contains a packet of data and instruct a set of components associated with an other of the in-phase and quadrature components of the local oscillator to activate to process the received signal.