Abstract: Assuring acquisition of symbol timing in a full-duplex data transceiver under inter-symbol interference conditions. One embodiment includes a transmitter comprising a first local clock having a first free running frequency, and a receiver comprising a second local clock having a second frequency initially set to a value higher than the first free running frequency. A first type decision-directed timing recovery mechanism is intentionally limited to only decreasing the frequency of the second local clock. A second type decision-directed timing recovery mechanism is not limited to only decreasing the frequency. The receiver receives symbols, decrease the frequency of the second local clock to a third frequency value using the first type decision-directed timing recovery mechanism, disables the first type mechanism after reaching the third frequency, and then phase-lock the second local clock to the optimal phase under MMSE criteria using the second type decision-directed timing recovery mechanism.

Abstract: A method and tag for decoding a signal received from a radio frequency identification (“RFID”) reader. A signal is received from the RFID reader in which the signal has a series of pulses. A time frame between receipt of two consecutive pulses is measured to determine whether the pulses represent zero bits or one bits. A total pulse duration is calculated in which the total pulse duration represents a sum of the measured time frames for the signal. A command is decoded. The decoding is based on the total duration of the two pulses.

Abstract: The data processing unit (15) for a receiver of signals carrying information (1) includes a clock and data recovery circuit (16) on the basis of a data signal (DOUT), and a processor circuit (17) connected to the clock and data recovery circuit. The clock and data recovery circuit is clocked by a local clock signal (CLK) and includes a numerical phase lock loop, in which a numerically controlled oscillator (25) is arranged. This numerically controlled oscillator generates an in-phase pulse signal (IP) and a quadrature pulse signal (QP) at output. The frequency and phase of the pulse signals IP and QP are adapted on the basis of the received data signal (DOUT). The processor circuit is arranged to calculate over time the mean and variance of the numerical input signal (NCOIN) of the numerically controlled oscillator (25), so as to determine the coherence of the data signal if the calculated mean and variance are below a predefined coherence threshold.

Abstract: A receiver is described. The receiver includes a first injection-locked oscillator having a first input configured to receive a BPSK signal and a second input configured to receive a first frequency reference. The receiver also includes a second injection-locked oscillator having a third input configured to receive the BPSK signal and a fourth input configured to receive a second frequency reference. Further, the receiver includes a first phase-locked loop coupled with the second input of the first injection-locked oscillator. The first phase-locked loop is configured to generate the first frequency reference. And, a second phase-locked loop is coupled with the fourth input of the second injection-locked oscillator. The second phase-locked loop is configured to generate the second frequency reference.

Abstract: A two point modulation digital phase locked loop circuit is disclosed. The circuit includes a sampling clock input that is switchable between a plurality of frequencies. The circuit also includes a sigma-delta modulator in a feedback path that receives low-pass modulation data. The circuit also includes a voltage-mode digital-to-analog converter (VDAC) that receives high-pass modulation data. The circuit also includes an analog voltage controlled oscillator coupled to the feedback path and the output of the VDAC. The circuit also includes a phase-to-digital converter (PDC) coupled to the feedback path, the sampling clock and a loop filter.

Abstract: A bang-bang frequency detector with no data pattern dependency is provided. In examples, the detector recovers a clock from received data, such as data having a non-return to zero (NRZ) format. A first bang-bang phase detector (BBPD) provides first phase information about a phase difference between a sample clock and the clock embedded in the received data. A second BBPD provides second phase information about a second phase difference between the clock embedded in the received data and a delayed version of the sample clock. A frequency difference between the sample clock and the clock embedded in the received data is determined based on the first and second phase differences. The frequency difference can be used to adjust the frequency of the sample clock. A lock detector can be coupled to a BBPD output to determine if the sample clock is locked to the clock embedded in the received data.

Abstract: A low phase noise frequency synthesizer, comprising, arranged in series, a first mixer receiving a reference signal at a reference frequency Fr, a loop filter and a voltage-controlled oscillator delivering a microwave signal at a second frequency FO slaved to a multiple of reference frequency Fr, further comprises: means of multiplication of the frequency FO of said microwave signal by a factor N strictly greater than 1, means of correction of the frequency N.FO of the output signal of the multiplication means configured to restore frequency N.FO to an interval [FOmin, FOmax] where output frequency FO would vary if multiplication factor N=1, means of division of the frequency Fj of the output signal of the correction means by a factor equal to the expected ratio between frequency Fj and reference frequency Fr, the frequency division means being connected at output to the second input of the first mixer.

Abstract: In a phase locked loop, frequency-divided clocks each of which is given a phase difference of at least one cycle of a feedback clock are inputted to a first phase comparator and a second phase comparator, respectively, which are made to perform phase comparison with a reference clock. Then, outputs of the first and second phase comparators are weighted by a result of the phase comparison of a receive signal and the feedback clock, and phase adjustment of the feedback clock is phase adjusted using the weighted outputs. Thereby, it is possible to lower a frequency of the reference clock and consequently to suppress power consumption.

Abstract: In some embodiments an adaptive clock controller is to determine clock interference associated with a channel changing pattern for a radio in a computing platform, and to determine an earliest switching time of a clock of the computing platform. A clock generator is to change a frequency of the clock in response to the determined clock interference and in response to the earliest switching time. Other embodiments are described and claimed.

Abstract: An integrated CMOS clock generator with a self-biased phase locked loop circuit comprises a phase-frequency detector with a reference signal input, a feedback signal input and an output. A first charge pump of the clock generator has an input connected to the output of the phase-frequency detector and an output that supplies a control voltage. A loop capacitor is connected to the output of the first charge pump. The clock generator further has a second charge pump with an input connected to the output of the phase-frequency detector and an output. In particular, the clock generator has two oscillator blocks.

Abstract: A circuit, use, and method for controlling a receiver circuit is provided, wherein a complex baseband signal is generated from a received signal, a phase difference between a phase of the complex baseband signal and a phase precalculated from previous sampled values is determined, the phase difference is compared with a first threshold, a number is determined by counting the exceedances of the first threshold by the phase difference, a number of the counted exceedances is compared with a second threshold, and the receiver circuit is turned off if the number of counted exceedances exceeds the second threshold within a time period.

Abstract: The effects of shock and vibration on a navigation receiver processing satellite signals received from global navigation satellites are reduced by controlling the frequency and the phase of the individual numerically controlled oscillator in each individual satellite channel. The frequency is controlled by an individual frequency control signal based on individual correlation signals generated in an individual satellite channel. The phase is controlled by a common phase control signal or a combination of a common phase control signal and an individual phase control signal. The common phase control signal is based on all the correlation signals generated in all the satellite channels processed by a separate common broadband quartz loop (SCBQL). An individual phase control signal is based on the individual correlation signals generated in an individual satellite channel.

Abstract: Embodiments of the invention are generally directed to adjustment of clock signals regenerated from a data stream. An embodiment of a method includes receiving a data stream from a transmitting device via a communication link, the data stream including stream data, a link clock signal, and timestamps to indicate a relationship between the link clock signal and a stream clock signal. The method further includes adjusting the stream clock based at least in part on one or more measurements related to the data stream, the one or more measurements including a count of a number of pulses of the stream clock during a period of time, or a measurement of a number of data elements from the data stream stored in a buffer at a certain point in time.

Abstract: A system and method for reducing implementation complexity for estimation of a Carrier Frequency Offset (CFO) and a Symbol Timing Offset (STO) for an input signal for spectrally shaped multiple communication standards. The system is implemented by replacing multiplier with shifters. The system includes a CFO estimation block, a STO estimation block, and a band extraction block that extracts a lower band edge and an upper band edge of the input signal. The STO estimation block includes (i) a sample error generation block that computes a sampling timing error value, and (ii) a Phase Lock Loop block that estimates a frequency error and a phase error corresponding to the sampling timing error value. The CFO estimation block includes (i) a carrier offset error generation block that generates a carrier offset error value, and (ii) a leaky average block for performing a filter operation.

Abstract: In a method of recovering timing information over a packet network at a local receiver, timing information is received at intervals timing from a remote source and compared with a locally generated clock signal to generate an input signal y(k) subject to noise representative of the phase difference between the source clock signal and the local receiver clock signal. The input signal is applied to a state feedback controller, preferably including a Kalman filter, to generate a control signal with reduced noise. The control signal is used to control an oscillator in a way so as to reduce the phase difference and generate a slave clock.

Abstract: A processing device processes an analog complex input signal representing a sequence of OFDM symbols in a radio-receiver. The processing device comprises processing paths, each comprising a complex mixer and an analog channel-selection filter. Furthermore, the processing device comprises an oscillator unit that provides local oscillator signals associated with the complex mixer of each processing path. A control unit determines, based on received control data, subcarrier locations, within at least one individual OFDM symbol of the sequence, of one or more resource blocks allocated to the radio receiver. The control unit, for each of the at least one individual OFDM symbol, controls the local oscillator signals based on the determined subcarrier locations and passbands of the channel-selection filters such that each resource block allocated to the radio receiver is frequency translated by a complex mixer of the processing paths to appear within the passband of the following channel-selection filter.

Abstract: A data recovery device and a data recovery method are provided. The data recovery device includes an equalizer, a slicer, a phase lock loop (PLL) circuit, a detection circuit, and a compensation circuit. The equalizer adjusts a radio frequency (RF) signal according to a compensation signal and outputs an equalized RF signal sliced by the slicer according to a slicing level to output an AC_RF signal with segments. The PLL circuit outputs a clock according to phases of the AC_RF signal. The detection circuit calculates and outputs time intervals in the segments according to the clock and detects and outputs sampling heights in the segments. The compensation circuit selects at least two of the sampling heights, calculates a ratio of the selected sampling heights according to the outputs of the detection circuit, and outputs the compensation signal according to a result of comparison between the ratio and a corresponding reference.

Abstract: Embodiments of a receiver for using a first oscillator signal provided by a crystal resonator to support multiple, different functionalities are provided. The receiver comprises a phase-locked loop (PLL) configured to provide a second oscillator signal based on the first oscillator signal provided by the crystal resonator; a first mixer configured to mix a received signal received over a first input path with the second oscillator signal received over a second input path to provide a first frequency-shifted signal; and an automatic frequency controller (AFC) configured to estimate a frequency offset of the second oscillator signal and adjust the PLL to compensate for the frequency offset. The receiver further can include solutions for mitigating potential sources of noise caused by the frequency of the first oscillator signal not being compensated for by the AFC.

Abstract: A phase-locked loop having: an oscillator for forming an oscillating output signal; a frequency divider connected to receive the output of the oscillator and frequency divide it by a value dependent on a division control signal; and a phase comparator for comparing the phase of the divided signal and a reference signal to generate a control signal, the operation of the oscillator being dependent on the control signal; the output data to form a divided signal a division ratio controller configured to, when clocked by an input signal, generate a series of output data for forming the division control signal; the phase-locked loop having: a first mode of operation in which the frequency divider is operable to frequency divide the output of the oscillator by a value dependent on the output of the division ratio controller; and a second mode of operation in which the frequency divider is not operable to frequency divide the output of the oscillator by a value dependent on the output of the division ratio controller

Abstract: An apparatus for determining signal power comprise an oscillating circuit and a determining circuit. The oscillating circuit generates an oscillating signal. When a to-be-detected signal has signal power greater than a threshold, the oscillating signal has a first frequency; when the signal power is smaller than the threshold, the oscillating signal has a second frequency. The determining circuit determines whether the oscillating signal has either the first frequency or the second frequency, and generates a determination result accordingly.

Abstract: Method and apparatus for achieving high precision sampling recovery at a relatively low sampling rate. The apparatus includes: a sampling rate conversion module for converting the sampling rate of a received signal to an required sampling rate; a time domain impulse response estimation module for estimating a time domain impulse response of a transmission channel according to data output by the sampling rate conversion module; a high order interpolation module for performing high order interpolation to one or more selected transmission paths after obtaining the time domain impulse response; and a sampling error information extraction module for extracting sampling phase offset information and sampling frequency offset information based on interpolation results and drifts in two consecutive interpolation results of the high order interpolation step. The apparatus is capable of realizing fast high precision locking of sampling phase and correction of sampling frequency offset at a relatively low sampling rate.

Abstract: An aspect of the disclosure provides a signal processing circuit that decouples a timing loop and an equalizer adaptation loop. The signal processing circuit includes an analog to digital converter (ADC), an equalizer, a detector, and a timing module. The ADC is configured to receive an analog signal, sample the analog signal based on a sampling clock signal, and convert the sampled analog signal into a digital signal. The equalizer is configured to equalize the digital signal. The detector is configured to detect a bit stream from the equalized digital signal. The timing module is configured to detect a timing error based on the digital signal before being equalized, and to adjust the sampling clock signal based on the timing error.

Abstract: A single chip radio transceiver includes circuitry that enables received wideband RF signals to be down converted to base band frequencies and base band signals to be up converted to wideband RF signals prior to transmission without requiring conversion to an intermediate frequency. The circuitry includes a low noise amplifier, automatic frequency control circuitry for aligning the LO frequency with the frequency of the received RF signals, signal power measuring circuitry for measuring the signal to signal and power ratio and for adjusting frontal and rear amplification stages accordingly, and finally, filtering circuitry to filter high and low frequency interfering signals including DC offset.

Abstract: A spread spectrum clock signal generator and an accompanying method provide a spread spectrum clock signal of a reduced electromagnetic interference. The spread spectrum clock signal generator includes (a) a state machine, which maintains a current state of the spread spectrum clock signal generator, receives as input value a next state of the spread spectrum clock signal generator and generates a clock phase selection signal based on the current and next states; (b) a random number generator for generating the next state; and (c) a waveform generation circuit for generating a spread spectrum clock signal based on the clock phase selection signal.

Abstract: Unfolded adaptive/decision-directed loops and correction circuits therefor, architectures, apparatuses and systems including the same, and methods, algorithms and software for reducing latency in an adaptive and/or decision-directed loop. Disclosed embodiments advantageously reduce effects of loop latency, improve the accuracy of corrections in an adaptive loop, and minimize overhead and delays associated with such improvements.

Abstract: Systems and methods for on-the-fly characterization of an arbitrary array of antenna elements are provided. An array of arbitrary antenna elements and a reference receiver is provided. A location for a target source of signals is provided or assumed. Cross ambiguity functions are computed between the signal received by the reference receiver and the signal received by each antenna element. The cross ambiguity functions are analyzed to determine the phase and amplitude response of the antenna array to signals originating from the location of the target source of signals.

Abstract: A method and apparatus at a local terminal are described for demodulating a remote-terminal signal located at a subband offset frequency in a frequency subband of relayed interference from a transponder satellite link. The demodulation of the remote-terminal signal is accomplished by transferring the digital data that produced the local-terminal transmit signal to the local-terminal receiver. The digital data is time-delayed and converted to a narrowband offset-constellation signal that cancels the relayed interference in an adaptive equalizer. Providing cancellation in the subband of the relayed interference produces larger interference cancellation factors than those obtained in conventional broadband cancellation systems. A phase-noise error signal is also generated and used to increase cancellation levels limited by phase noise generated in the satellite link frequency converters.

Abstract: A method includes, in a receiver that operates using multiple clock signals having respective clock frequencies, accepting a request to receive a target channel frequency. In response to the request, a set of preferred clock frequencies is calculated, which when applied by the receiver will cause the receiver to tune to the target channel frequency while satisfying a predefined criterion relating to interference caused by the clock signals. The target channel frequency is received by setting the clock signals to the preferred clock frequencies.

Abstract: A receiver is described. The receiver includes a first injection-locked oscillator having a first input configured to receive a BPSK signal and a second input configured to receive a first frequency reference. The receiver also includes a second injection-locked oscillator having a third input configured to receive the BPSK signal and a fourth input configured to receive a second frequency reference. Further, the receiver includes a first phase-locked loop coupled with the second input of the first injection-locked oscillator. The first phase-locked loop is configured to generate the first frequency reference. And, a second phase-locked loop is coupled with the fourth input of the second injection-locked oscillator. The second phase-locked loop is configured to generate the second frequency reference.

Abstract: A transceiver node includes a pulse coupled oscillator in an integrated circuit, which can synchronize with other nodes to generate a global clock subsequently used to facilitate synchronous communications between individual nodes. Known potential uses include a low power sensor node radio for an ad-hoc network for military applications and medical applications such as ingestible and implantable radios, self powered radios, and medical monitoring systems such as cardiac and neural monitoring patches.

Abstract: A change-point detection circuit 16 extracts a clock signal from serial data, input data. A variable delay circuit provides a delay in accordance with a delay control signal to a reference signal having a predetermined frequency, so that the phase of the reference signal is shifted on the basis of an initial delay. An input latch circuit latches internal serial data by using an output signal of the variable delay circuit as a strobe signal. A phase comparator matches the frequencies of the clock signal and the strobe signal with each other, and generates phase difference data in accordance with a phase difference between the two signals. A loop filter integrates the phase difference data generated by the phase comparator and outputs it as the delay control signal. The phase shift amount acquisition unit acquires a phase shift amount based on the delay control signal, the phase shift amount being based on the initial delay provided to the reference signal by the variable delay circuit.

Abstract: An apparatus includes Radio Frequency (RF) circuitry and baseband circuitry. The RF circuitry is configured to receive strobe messages that are based on a system clock over a digital interface, and to communicate synchronously with the system clock based on the received strobe messages in accordance with a Radio Access Technology (RAT) that is selected from among multiple different RATs. The baseband circuitry is configured to generate the strobe messages, to delay the strobe messages by a delay that depends on the selected RAT, and to send the delayed strobe messages to the RF circuitry over the digital interface.

Abstract: A method for communication includes receiving a signal, which carries data bits and is distorted by multiple impairments including one or more frequency offsets and one or more In-phase/Quadrature (I/Q) imbalances. A corrected signal is produced by applying to the received signal a sequence of corrections to compensate for the impairments. The sequence includes a first and a third correction of one correction type and a second correction of another correction type intervening between the first and third corrections in the sequence, the correction types consisting of frequency offset corrections and I/Q imbalance corrections. The data bits are extracted from the corrected signal.

Abstract: The invention relates to a EHF wireless communication receiver comprising a phased array radio arranged for receiving a beam of signals in a predetermined frequency band. The phased array radio comprises a plurality of antenna paths, each arranged for handling one of the incoming signals and forming a differential I/Q output signal, each antenna path comprises a downconversion part and a phase shifting part for applying a controllable phase shift; a signal combination circuitry is connected to the antenna paths and is arranged for combining the differential I/Q output signals; and a control circuitry is connected to the phase shifting parts of the antenna paths and is arranged for controlling the controllable phase shift. In each antenna path, the phase shifting part is a baseband part downstream from the downconversion part and the phase shifting part comprises a set of variable gain amplifiers arranged for applying controllable gains to the respective downconverted incoming signals in the I/Q branches.

Abstract: The disclosure aims to implement an automatic frequency offset compensation of the frequency between emitter and receiver equipments, in radio frequency modules, with a frequency offset that can be larger than that the receiver can allow, without time loss and extra consumption. To solve this problem, the disclosure provides an automatic frequency offset compensation device comprising a reception front end, at least a filter, an I/Q demodulator for obtaining the I (In Phase) and Q (Quadrature) parameter, an automatic frequency control AFC unit for comparison of a received frequency with the real frequency of the equipment, and a microcontroller and a frequency synthesizer. In this device, the frequency offset is calculated by the AFC unit from the information given by the I/Q demodulator.

Abstract: A communication terminal includes first and second transmitters, which are coupled to produce respective first and second Radio Frequency (RF) signals that are phase-shifted with respect to one another by a beamforming phase offset, and to transmit the RF signals toward a remote communication terminal. The terminal includes a reception subsystem including first and second receivers and a phase correction unit. The first and second receivers are respectively coupled to receive third and fourth RF signals from the remote communication terminal. The phase correction unit is coupled to produce, responsively to the third and fourth RF signals, a phase correction for correcting an error component in the beamforming phase offset.

Abstract: A method and an apparatus for audio noise reduction of frequency modulation (FM) receiver are described. After receiving FM signal having pilot tone, pilot carrier sync detector performs pilot carrier synchronization detection of FM signal, FM demodulator demodulates synchronized FM signal, multiplex decoder decodes audio signal of demodulated FM signal for outputting the decoded audio signal, and noise reduction controls multiplex decoder for controlling noise attenuation associated with the decoded audio signal according to RSSI, the method comprising the steps: (a) performing phase error detection for detecting phase error of phase-locked loop (PLL) of pilot carrier sync detector; (b) determining whether noise exists by comparing the phase error with threshold value to determine whether noise exists in the phase error; and (c) performing noise reduction step by outputting noise reduction control signal to noise reduction based on determination in step (b) for reducing noise in the noise existence interval.

Abstract: A frequency synthesis system with self-calibrated loop stability and bandwidth, which outputs an output signal based on an input signal and includes a detector, a charge pump, a filter, a controllable oscillator and a programmable frequency divider. The detector produces a detection signal based on a logic level difference between the input signal and a feedback signal. The charge pump is connected to the detector in order to produce a control signal based on the detection signal. The filter is connected to the charge pump in order to produce a tuning signal based on the control signal. The controllable oscillator is connected to the filter in order to produce the output signal based on the tuning signal. The programmable frequency divider is connected to the controllable oscillator in order to produce the feedback signal based on the output signal. The filter is a discrete time loop filter.

Abstract: The invention relates to a clock generation circuit and a signal reproduction circuit including the clock generation circuit, and, more particularly, the invention provides a data judgment/phase comparison circuit capable of performing both of data judgment and phase comparison by a single-phase clock, and provides a CDR (Clock Data Recovery) circuit including the data judgment/phase comparison circuit. The same data and clock are inputted to two data judging units C_GOOD and C_BAD each having a different data determination period (setup/hold time) required for correctly judging a data, and an output of the data judging unit C_GOOD having a shorter required data determination period is taken as a data output of the data judgment/phase comparison circuit. When the outputs of both of the data judging units are different from each other, a signal Early indicating that a clock phase is too early or a signal Late indicating that the clock phase is too late is outputted.

Abstract: A receiver is described. The receiver includes a first injection-locked oscillator having a first input configured to receive a BPSK signal and a second input configured to receive a first frequency reference. The receiver also includes a second injection-locked oscillator having a third input configured to receive the BPSK signal and a fourth input configured to receive a second frequency reference. Further, the receiver includes a first phase-locked loop coupled with the second input of the first injection-locked oscillator. The first phase-locked loop is configured to generate the first frequency reference. And, a second phase-locked loop is coupled with the fourth input of the second injection-locked oscillator. The second phase-locked loop is configured to generate the second frequency reference.

Abstract: An apparatus provides a digital representation of a time difference between a periodic reference signal having a reference signal period and a periodic input signal having an input signal period. The apparatus includes a free-running finite state machine (FSM) that traverses a multiplicity of states in a predetermined order, the state having corresponding state vectors, each of which is held for a state dwell time. A timing circuit receives the reference signal, the input signal and the FSM state vectors, and determines a state transition count equal to a number of FSM state transitions that occur during a counting interval, which corresponds to the time difference between the reference and input signals. A digital low-pass filter receives the state transition counts and provides an output value including weighted sums of the state transition counts, proportional to the time difference between the reference and input signal. A period of the FSM is independent of the reference signal period.

Abstract: Aspects of a method and system for bandwidth calibration for a phase locked loop are presented. Aspects of the method may include generating one or more carrier signals based on one or more corresponding calibration signals. A pre-distortion function may be computed based on the generated one or more carrier signals for the phase locked loop circuit. An output radio frequency (RF) synthesized signal generated by the phase locked loop circuit may be modified based on the computed pre-distortion function and a subsequent output RF synthesized signal generated based on the modified output RF synthesized signal.

Abstract: A serializer-deserializer (SERDES) includes a clock-data recovery block, a control block, and a low-pass filter. The control block contains a state machine that includes a fast convergence mode utilizing an unstable operating point and a slow tracking mode utilizing a stable operating point. The control block is configured to start in the fast convergence mode to allow quickly locking the recovered clock to the incoming data stream by replicating movement commands resulting in multiple phase adjustments for each transition. To facilitate proper operation of the SERDES, the fast convergence mode is exited after N-bits and a slow tracking mode is entered to provide stable operation. The control block accepts filtered transition-data and data-transition phase state signals and converges to a phase aligned state in less than 2N-bits where N represents the number of phases in one data bit.

Abstract: A communications subsystem for a wireless device for correcting errors in a reference frequency signal. The communications subsystem comprises a frequency generator for generating the reference frequency signal and a closed loop reference frequency correction module that generates a reference frequency adjustment signal for correcting the reference frequency signal when the communications subsystem operates in closed loop mode. The subsystem further includes an open loop frequency correction means that that samples values of the reference frequency adjustment signal during the closed loop mode and generates a frequency correction signal for correcting the reference frequency signal when the communications subsystem operates in a mode other than closed loop mode.

Abstract: The carrier phase of a carrier wave modulated with information symbols is recovered with a multi-stage, feed-forward carrier phase recovery method. A series of digital signals corresponding to the information signals is received. For each digital signal, a coarse phase recovery is performed to determine a first phase angle which provides a first best estimate of the information symbol corresponding to the digital signal. Using the first best estimate as input, a second stage of estimation is then performed to determine a second phase angle which provides an improved (second) best estimate of the information symbol. Additional stages of estimation can be performed. The multi-stage, feed-forward carrier phase recovery method retains the same linewidth tolerance as a single-stage full blind phase search method; however, the required computational power is substantially reduced. The multi-stage, feed-forward carrier phase recovery method is highly efficient for M-QAM optical signals.

Abstract: An automatic zero-crossing signal demodulation and classification device for rapidly identifying unknown modulation in a signal identifies unknown modulation in a signal, demodulates differential phase shift keying signals and automatically recognizes certain phase shift keying signals. This is accomplished by eliminating unknown term fc in differential phase estimation, introducing a symbol rate tracking mechanism, applying hysteresis nonlinearity to eliminate phase shaping effect and using weighted average to estimate phase difference. Better estimates are accomplished by using hysteretic nonlinear function to detect zero-crossing points in eliminating false detecting of zero-crossing points caused by additive noise, and calculating differential phase without directly using center frequency to simplify estimation process.

Abstract: One embodiment of the present invention relates to a communication system having a digital to analog converter, a first input, a summation component, a compensation filter, and a compensation unit. The converter is configured to receive a first signal. The first input is configured to receive a phase modulation signal. The compensation filter generates a filtered frequency deviation signal to mitigate frequency distortions, such as those from a digital controlled oscillator. The compensation unit includes one or more inputs and is configured to generate a correction signal according to the filtered frequency deviation signal and the first signal. The correction signal at least partially accounts for estimated distortions of the phase modulation signal from the amplitude modulation path and mitigates frequency induced distortions. The summation component is configured to receive the phase modulation signal and the correction signal and to generate a corrected phase modulation signal as a result.

Abstract: A serializer is equipped with a plurality of input terminals into which a plurality of binary signals are input in parallel, and converts the plurality of input binary signals into serial binary signals and transmits the serial binary signals to an optical transmission module. One input terminal out of the plurality of input terminals is assigned as an input terminal for preventing bit continuation by inserting “1” signals or “0” signals into the serial binary signals so that a predetermined number of bits of the same value may not be inserted continuously. Due to this structure, bit continuation can be prevented even for a signal generating source with no coding function by a simple configuration without increasing cost and size.

Abstract: A communication system includes: a transmitter adapted to transmit a synchronizing clock and serial data synchronous with the synchronizing clock over a line at low amplitude; and a receiver adapted to receive the serial data and synchronizing clock from the transmitter. The receiver includes an amplifier adapted to amplify the received synchronizing clock of low amplitude to restore the clock to its original amplitude, a latched comparator adapted to latch the received serial data in synchronism with a reproduction clock, and a phase-locked circuit.

Abstract: According to one embodiment, a register outputs a first control code in first and second operation modes, saves the first control code as a third control code at an end of the first operation mode, and outputs the third control code at a beginning of a third operation mode. In the first operation mode, a digital-to-analog converter supplies a control signal with a control voltage to a voltage controlled oscillator. In the second operation mode, the control signal is supplied to a buffer amplifier, the amplifier drives a bandlimiting filter, and the filter generates the control voltage. In the third operation mode, the control signal is supplied to the filter, and the filter generates the control voltage.