Abstract: Signal conditioning circuitry includes logic circuitry, a low-pass filter, and comparator circuitry. The logic circuitry is configured to compare a data unit with a preceding data unit, from a sequence of data units, and provide a logic output signal. The low-pass filter is coupled to the logic circuitry, and the low-pass filter is configured to provide a data transition density measurement for the sequence of data units based on the logic output signal. The comparator circuitry is coupled to the low-pass filter, and the comparator circuitry is configured to compare the data transition density measurement to a threshold and, based on the comparison to the threshold, indicate a disruptive pattern in the sequence of data units.

Abstract: A data communication method in which input digital data is received and encoded into an encoded waveform having zero crossings representative of the input digital data. The encoding includes generating the encoded waveform based upon a continuous piecewise function having sinusoidal components. The continuous piecewise function may be used in generating a plurality of symbol waveforms, each of which occupies a period of the encoded waveform and represents bits of the input digital data. The plurality of symbol waveforms are defined so that a value of a phase offset used in the continuous piecewise function is different for each of the plurality of symbol waveforms, thereby resulting in each symbol waveform having a different zero crossing. An encoded analog waveform is generated from a representation of the encoded waveform and transmitted to a receiver.

Abstract: An example involves accessing a unique audience size of database proprietor subscribers exposed to media, the unique audience size of the database proprietor subscribers generated by a process of a server of a database proprietor based on a first quantity of impressions, the first quantity of impressions corresponding to first client devices that include database proprietor identifiers and exclusive of a second quantity of impressions corresponding to second client devices that do not include the database proprietor identifiers; and applying a missing-audience factor to the unique audience size of the database proprietor subscribers exposed to the media to produce a coverage-corrected unique audience size that corrects the unique audience size generated by the server of the database proprietor by using the coverage-corrected unique audience size to represent the first and second client devices in place of the unique audience size that corresponds to the first client devices exclusive of the second client devi

Abstract: Signal conditioning circuitry includes logic circuitry, a low-pass filter, and comparator circuitry. The logic circuitry is configured to compare a data unit with a preceding data unit, from a sequence of data units, and provide a logic output signal. The low-pass filter is coupled to the logic circuitry, and the low-pass filter is configured to provide a data transition density measurement for the sequence of data units based on the logic output signal. The comparator circuitry is coupled to the low-pass filter, and the comparator circuitry is configured to compare the data transition density measurement to a threshold and, based on the comparison to the threshold, indicate a disruptive pattern in the sequence of data units.

Abstract: One example includes a switch system. The system includes a first signal port and a second signal port. The system also includes a first switching path arranged between the first and second signal ports. The first switching path includes at least one first switch and at least one of the at least one first switch being configured as a high-speed switching device. The system further includes a second switching path arranged between the first and second signal ports in parallel with the first switching path. The second switching path includes at least one second switch and at least one of the at least one second switch being configured as a high-performance switching device.

Abstract: A single channel receiver includes an input terminal that receives an analog input signal, a mixer that down-mixes the analog input signal by use of a phase- and/or frequency-corrected oscillator frequency signal and shifts complex-valued information contained in the analog input signal to the real part (or alternatively to the imaginary part) to obtain an intermediate real-valued analog signal, an analog-to-digital-converter that converts the intermediate analog signal into an intermediate digital signal, a demodulator that demodulates the intermediate digital signal into a digital output signal, a phase tracking loop that detects zero-crossings in the intermediate digital signal to obtain phase error information representing a phase error in the intermediate digital signal, and an oscillator that generates the phase- and/or frequency-corrected oscillator frequency signal by compensating the phase and/or frequency error in the intermediate digital signal by correcting the phase of the oscillator frequency si

Abstract: A base station for generating multi-user precoders. The base station includes a transceiver configured to receive sounding reference signals (SRSs) from a set of user equipments (UEs), and a processor configured to select, for one or more UEs in the set of UEs, one or more codewords from an uplink codebook based on a correlation between the one or more codewords and the one or more SRSs; determine, using a composite downlink codebook, downlink codewords for the selected uplink codewords, respectively, the composite downlink codebook mapping uplink codewords to downlink codewords based on steering angles derived from the uplink codewords; transmit a set of pre-coded channel state information reference signals (CSI-RSs) to the one or more UEs, wherein the pre-coded CSI-RSs are pre-coded based on the determined downlink codewords; and identify a downlink channel matrix based on CSI feedback from the one or more UEs and the pre-coded CSI-RSs.

Abstract: A modulation device includes a mapping circuit configured to map information bits to signal points on a plurality of concentric rings, when a signal space arrangement in which the number of signal points on all of the plurality of rings is the same is used as a basis, reduce the number of signal points on an innermost ring or a plurality of rings from inner to outer rings from among the plurality of rings, generate a new ring outside the signal space arrangement used as the basis, and arrange, on the generated ring, signal points which achieve the same frequency utilization efficiency as that of the signal space arrangement used as the basis.

Abstract: Systems and methods for performing automatic frequency control are provided. Instead of relying on individual frequency tuners for each channel of a multi-channel receiver system, the present subject matter uses a single frequency tuner for receiving each channel of the multi-channel receiver system. A locked demodulator may be designated as a reference demodulator and frequency offset values associated with the reference demodulator may be applied to other demodulators of the multi-channel receiver. These frequency offset values may be used by individual demodulators of each channel for correcting corresponding frequency offsets.

Abstract: A radar system and method of extending a parameter of a location of a target obtained by radar is disclosed. The system receives an echo signal that is a reflection of a radar source signal from the target. The echo signal is sampled and a peak for the echo signal is objected in frequency space. For a peak that is located at a frequency greater than a Nyquist frequency of the echo signal, the peak is moved to a negative domain of the frequency space and the location of the target is determined using the peak in the negative domain.

Abstract: A communications adaptor comprises a receiver circuit, which can comprise a signal input configured to receive a frequency shift keyed (FSK) signal; a delay circuit in communication with the signal input and including a delayed signal output; a multiplier circuit in communication with the signal input and the delayed signal output, and the multiplier circuit can be configured to produce a serial bit steam from at least the signal input and the delayed signal output, the serial bit stream corresponds to one or more bits encoded with frequency shift keying in the FSK signal; and a signal output configured to output the serial bit stream. The communications adaptor also can comprise a transmitter circuit and a processor in communication with the receiver circuit and the transmitter circuit.

Abstract: Alternating on-die termination impedances are applied within an integrated circuit device to up-convert signal reflections to higher frequencies that are attenuated by the signaling channel as the reflections propagate toward an intended signal receiver. Through this approach, the disruptive effect of reflected signals may be significantly reduced with relatively little overhead within the interconnected integrated circuit devices and little or no change to the printed circuit board or other interconnect medium. Changes to the printed circuit board or other interconnect medium can be made to further increase attenuation over the frequency band of the up-converted reflection and outside of the transmission band of signals of interest.

Abstract: An arrangement is described in which phase parity or phase opposition between two signals can be determined, and if necessary remedial action may be taken.

Abstract: A terminal (10) includes elements for transmitting data towards a station (20) in the form of radio signals, the radio signals being transmitted using a frequency resource (MC) shared between a plurality of terminals (10), characterized in that the terminal is configured to emit radio signals, the instantaneous frequency spectrum of which has a bandwidth (TOB) that is significantly lower than a frequency drift of a frequency synthesis unit of the terminal. Also disclosed are a method for using a frequency resource, a method for manufacturing terminals (10) and a telecommunication system (1).

Abstract: A precoding codebook matrix/vector of length 2L is generated by the selection of two matrices/vectors, each from one of a predetermined set of L×L matrices and multiplying each column of one of the matrices/vectors by a complex coefficient.

Abstract: A receiver is described. The receiver includes a filter configured to receive a quadrature phase shift keying (“QPSK”) signal. Further, the receiver includes an amplifier coupled with the filter. And, a QPSK decomposition filter is coupled with the amplifier. The QPSK decomposition filter is configured to generate a first BPSK signal based on the QPSK signal and a second BPSK signal based on the QPSK signal.

Abstract: A receiver is set forth that includes a tuner circuit and a converter circuit. The tuner circuit provides an analog signal corresponding to a modulated signal that is received on a selected channel. The converter circuit includes a sample clock that is used to convert the analog signal to a digital signal at a conversion rate corresponding to the frequency of the sample clock. The sample clock is selectable between at least two different clock frequencies.

Abstract: A flow-based network switching system includes a memory having a flow table and a packet processor coupled to the memory. The packet processor includes a user-programmable flow-based rule storage that includes a plurality of flow-based rules. A flow-based handler and session manager in the packet processor is operable to retrieve application layer metadata from a first packet received over a network, determine a first flow session associated with the first packet using the application layer metadata from the first packet and the flow table, and retrieve at least one of the plurality of flow-based rules from the programmable flow-based rule storage using the application layer metadata from the first packet. A flow-based rule processing engine in the packet processor is operable to apply the at least one flow-based rule to the first packet. Packets with applied flow-based rules are forwarded through the network.

Abstract: Provided are a method and an apparatus for encoding and decoding an audio signal. A method for encoding an audio signal includes receiving a transformed audio signal, dividing the transformed audio signal into a plurality of subbands, performing a first sinusoidal pulse coding operation on the subbands, determining a performance region of a second sinusoidal pulse coding operation among the subbands on the basis of coding information of the first sinusoidal pulse coding operation, and performing the second sinusoidal pulse coding operation on the determined performance region, wherein the first sinusoidal pulse coding operation is performed variably according to the coding information. Accordingly, it is possible to further improve the quality of a synthesized signal by considering the sinusoidal pulse coding of a lower layer when encoding or decoding an audio signal in an upper layer by a layered sinusoidal pulse coding scheme.

Abstract: A FFR (fractional frequency reuse)-based network MIMO (multiple-input multiple-output) transmission architecture in a cellular system that employs cell sectoring using directional antennas. Each cell is sectorized into three outer sectors using three directional antennas which transmit in three different directions using three different frequency subbands. The cell sectors are arranged based on a frequency partition scheme so that three sectors in three neighboring cells form a coordinated group for network MIMO transmission. A regular and a rearranged frequency partition are described. Further, a practical implementation of SON (self organizing network)-based three-cell FFR-based network MIMO for a wireless OFDM system is described.

Abstract: An apparatus and method for demodulation of FSK signals are provided. Digital pulses of the FSK signals can be processed to detect digital data contained in the FSK frequencies by converting the FSK frequencies from a frequency signal to a digital logic signal and vice versa.

Abstract: Transmitter equalizer circuitry, e.g., for a serial, digital, data signal, includes tapped delay line circuitry for outputting a plurality of differently delayed versions of the signal propagating through the delay line circuitry. The equalizer circuitry also includes a plurality of electrical current digital-to-analog converters (“DACs”). The equalizer circuitry still further includes controllable (e.g., programmable) routing circuitry for selectably routing the delayed versions of the signal to the various DACs. The current strengths employed by the various DACs are also preferably controllable (e.g., programmable).

Abstract: A method of processing first and second corresponding signals having a delay therebetween. The method includes introducing a plurality of different delays between the first and second signals, successive delay amounts differing from each other by less than the interval between chip boundaries, and for each introduced delay, summing samples of the second signal which are obtained at the times of, at least, chip boundaries between bits of the first signal which have the same state, to obtain a value; thereby to obtain a representation of how the value varies according to the introduced delay, which representation contains a level change associated with an introduced delay which bears a predetermined relationship to the delay between the first and second signals.

Abstract: A receiver is described. The receiver includes a filter configured to receive a quadrature phase shift keying (“QPSK”) signal. Further, the receiver includes an amplifier coupled with the filter. And, a QPSK decomposition filter is coupled with the amplifier. The QPSK decomposition filter is configured to generate a first BPSK signal based on the QPSK signal and a second BPSK signal based on the QPSK signal.

Abstract: A receiver is set forth that includes a tuner circuit and a converter circuit. The tuner circuit provides an analog signal corresponding to a modulated signal that is received on a selected channel. The converter circuit includes a sample clock that is used to convert the analog signal to a digital signal at a conversion rate corresponding to the frequency of the sample clock. The sample clock is selectable between at least two different clock frequencies.

Abstract: A wireless communication device is provided that includes: a plurality of receiving portions that respectively receive wireless signals that are transmitted based on frequency-use methods set from among a plurality of frequency-use methods; and a setting portion that sets one of the plurality of frequency-use methods on each of the plurality of receiving portions respectively. The setting portion changes the frequency-use method of the plurality of receiving portions, based on a receiving result of a wireless signal in each of the plurality of receiving portions.

Abstract: Embodiments of the present invention relate to a system for clock synthesis or data timing recovery. No analog continuous time oscillator is required, all the building blocks of a Frequency Locked Loop/Phase Locked Loop belonging in the digital discrete time domain. From a system-level perspective, the system is characterized by its strong non-linear behavior due to the intrinsic nature of some building blocks. This inherent non-linearity is responsible for some unusual, attractive property of the complete system. The system is able to multiply the input frequency clock by an arbitrarily large factor, ensuring in any case the convergence of the algorithm in two reference clock cycles.

Abstract: A receiver circuit includes an LPF configured to remove an interference signal and/or a noise from a received signal, an ADC configured to digitize a signal output from the LPF, an FIR filter configured to further remove an interference signal and/or a noise from the signal output from the ADC and compensate imperfection in in-band characteristics caused in the LPF, a delay circuit configured to delay the signal output from the ADC by a predetermined time period, and a control circuit configured to control a destination of the signal output from the ADC, wherein the control circuit switches the destination of the signal output from the ADC to one of the FIR filter and the delay circuit according to a predetermined condition.

Abstract: A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal 30 according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock 15.

Abstract: A frequency translation system includes first and second translational switches, and a signal bus coupled therebetween. The first translational switch includes one or more inputs configured to receive a respective one or more first input signals, a first plurality of outputs, and a second plurality of outputs. The second translational switch includes one or more inputs configured to receive a respective one or more second input signals, a first output, and a second output. The signal bus, coupled between the first and second translational switches, includes (i) a first bus line coupled to a first one of the first plurality of outputs of the first translational switch, and to the first output of the second translational switch, and (ii) a second bus line coupled to a first one of the second plurality of outputs of the first translational switch, and to the second output of the second translational switch.

Abstract: A device (1) for reducing the interference in a received communication signal. The device includes: an adaptive filter (2) which uses a self-reference signal to remove a coherent and stable interfering signal from the received communication signal; a detection module (3) for detecting the existence of the target signal among the received communication signals; and a demodulation module (7) for demodulating the received communication signal when the target signal is detected. Further, this device includes: a noise-classifying device (5) which detects various interfering signals of the received communication signal and determines the classification of the detected interfering signals; and a switching module (6) for selecting the input signal for the demodulation module on the basis of the determination made by the noise-classifying device and the value when the existence of the target signal is detected.

Abstract: A system, method, and apparatus for a multiple data rate communication system is presented herein. The communication system receives data samples that are either sampled at a narrowband rate or a wideband rate and provides various functions and services, such as echo cancellation, DTMF detection and generation, and call discrimination. For wideband signals, a down-sampled signal is provided for each of the foregoing function and service. The output of the function or services is then recombined with the wideband signal.

Abstract: Methods, systems, and apparatuses for down-converting an electromagnetic (EM) signal by aliasing the EM signal, and applications thereof are described herein. Reducing or eliminating DC offset voltages and re-radiation generated when down-converting an electromagnetic (EM) signal is also described herein. Down-converting a signal and improving receiver dynamic range is also described herein.

Abstract: The Application is directed at arrangements at which switch mode power converters share a common load. More particularly, the application provides a masterless arrangement in which no single converter controls the operation of the other converters. This is achieved by an arrangement in which each converter attempts to share its current measurement with other converters through an arbitration scheme employed on a data line, with the winning converter providing a defacto current measurement; for example, a maximum or minimum, to the overall arrangement.

Abstract: Filter circuit includes Nth-order active filters switching circuit which switches shorting or non-shorting of active filter, and power-supply control circuit which controls such that a power supply of active filter is turned off when switching circuit shorts active filter. A receiver employing filter circuit turns off the power supply of active filter not needed when no interference wave exists within a given range from a desired frequency band. The foregoing structure allows lowering the power consumption of filter circuit.

Abstract: There is provided a method that comprises identifying a parasitic signal transfer in a filter using a signal-directed graph; and adding compensation paths to the filter to reduce or eliminate the effect of the parasitic signal transfer A corresponding filter is provided which comprises a plurality of amplifier stages that generate one or more filter poles; at least one component coupled to at least one of the amplifier stages, the component causing a parasitic effect in the filter; and means for applying a compensation current to the at least one amplifier stage to reduce or eliminate the parasitic effect.

Abstract: A device for generating a modulation signal for an RF pulse transmitter is disclosed. The device includes a detector, a video amplifier, an analog processing device, and a modulation signal generating device. The modulation signal generating device is configured to receive an information cue from the analog processing device and to output the modulation signal. The modulation signal generating device includes a digital processing device and a signal generating device. The digital processing device is configured to receive a transmission synchro signal and the information cue and to generate a first control signal and a second control signal. The signal generating device is configured to generate a variable-amplitude Gaussian-shaped signal in response to the first control signal, to generate a variable-amplitude square-shaped signal in response to the second control signal, and to generate the modulation signal according to the Gaussian-shaped signal and the square-shaped signal.

Abstract: A system and method for implementing an IQ generator includes a master latch that generates an I signal in response to a clock input signal, and a slave latch that generates a Q signal in response to an inverted clock input signal. A master selector is configured to provide a communication path from the master latch to the slave latch, and a slave selector is configured to provide a feedback path from the slave latch to the master latch. The foregoing I and Q signals are output directly from the respective master and slave latches without any intervening electronic circuitry.

Abstract: The invention relates to an arrangement for bypassing a low noise amplifier unit in the front stage of a radio receiver, especially intended for the base stations of mobile communication networks. The front stage includes, in succession, a divider (420), an amplifier unit (430) comprising two parallel, low noise amplifier branches, and a first combiner (450). The by-pass arrangement includes a second combiner (443), by which the halves (E11, E12) of the received signal are combined immediately after the divider before the amplification. A change-over switch (SW) is then used to select either the signal that has propagated through the amplifier unit and then combined (G·E1) or the signal (E1?) that has been directly combined as the output signal of the front stage. Due to the invention, the noise figure of the front stage is improved and the integration of its structure is facilitated.

Abstract: A digital-to-analog converter (DAC) includes a mismatch shaping feedback vector quantizer configured to store state information in expanded format using One-Hot Encoding of a matrix. The expanded state format storage enables implementation of a simplified state sorter for the vector feedback mechanism of the vector quantizer. The simplified state sorter may minimize the variance of ones (or other symbols representing state values) in the matrix, and allow performing sorting in a reduced number of clock cycles. For example, sorting may be performed on a predetermined edge of single clock cycle, or on two edges of the same clock cycle. The matrix may be normalized periodically or as needed, to avoid overflow and underflow. The DAC may be used as a quantizer of a modulator of an access terminal in a cellular communication system.

Abstract: A data transmission method with phase shift error correction comprising: transmitting through a network a transmission signal, wherein the transmission signal comprises a reference signal component having a predetermined frequency and a data signal component; receiving the transmission signal, wherein the received transmission signal includes a phase shift error caused by the network, wherein the phase shift error is in both the received reference signal component and the received data signal component; generating a multiplier signal at a receiver having the predetermined reference frequency; using the multiplier signal to determine the phase shift error in the received transmission signal; and correcting the received data signal component using the determined phase shift error.

Abstract: According to one embodiment of the present invention, it is possible to realize a signal transmitter which is capable of reducing power consumption and which can be easily designed. A differential transmitter block outputs differential output signals fixed to a predetermined logic signal to a differential receiver block and disconnects terminating resistors from a signal transmission path in an idle state. In the differential receiver block, a differential comparator outputs a logic determined by symbols of the differential output signal from the differential transmitter block, and an operating state detector detects the idle state upon detection that time successively outputting a predetermined logic by the differential comparator reaches a predetermined time, and controls switches so as to disconnect the terminating resistors from the signal transmitter in the receiving side upon detection of the idle state.

Abstract: A translational switch system includes first and second translational switches, and a signal bus coupled therebetween. The first translational switch includes one or more inputs configured to receive a respective one or more first input signals, a first plurality of outputs, and a second plurality of outputs. The second translational switch includes one or more inputs configured to receive a respective one or more second input signals, a first output, and a second output. The signal bus, coupled between the first and second translational switches, includes (i) a first bus line coupled to a first one of the first plurality of outputs of the first translational switch, and to the first output of the second translational switch, and (ii) a second bus line coupled to a first one of the second plurality of outputs of the first translational switch, and to the second output of the second translational switch.

Abstract: Methods and apparatus for coding a digital data string to represent a sequence of acoustic frequencies to be transmitted as an acoustic signal by a genuine acoustic authentication device; related to providing for improving the rate of successfully detecting a valid data string contained in the acoustic signal transmitted by the device. Each of a plurality of groups of bits of the data string are coded to represent a respective frequency value set of one or more acoustic frequencies to be transmitted acoustically to represent the respective group of bits. The number of acoustic frequencies in a frequency value set is less than the number of bits in the respective group of bits that the frequency value set represents. For each of the plurality of groups of bits of the data string, the respective frequency value set is selected according to a predetermined frequency assignation pattern that provides for probabilistic transition coding used for error correction of the acoustic signal.

Abstract: A full-wave rectifier circuit receives complementary signals and produces a current corresponding to an added value of differential signals at different levels. A voltage comparator performs a comparison between output signals produced and subjected to current addition and voltage conversion by the full-wave rectifier circuit. A timer detects whether an output signal of the voltage comparator is kept in the same state for a predetermined time or more, and produces a signal indicating a result of the detection. A signal detecting circuit that can accurately identify a state of digital signals of a minute amplitude transferred through a pair of complementary signal lines is achieved without complicating manufacturing steps.

Abstract: Methods, systems, and apparatuses for down-converting an electromagnetic (EM) signal by aliasing the EM signal, and applications thereof are described herein. Reducing or eliminating DC offset voltages and re-radiation generated when down-converting an electromagnetic (EM) signal is also described herein. Down-converting a signal and improving receiver dynamic range is also described herein.

Abstract: A receiver circuit controls a power source of a front-end circuit and a demodulator using a first power source control signal. Upon receiving data of a plurality of receiving slots having a guard bit provided between receiving slots adjacent to each other, the first power source control signal becomes a power source ON signal before starting receiving of the data, then becomes a power source OFF signal within the guard bit, and becomes a power source OFF signal after completing the receiving of the data. The receiver circuit controls a power source of an active filter circuit using a second power source control signal, which becomes a power source OFF signal after completing the receiving of the data after becoming a power source ON signal before starting the receiving of the data.

Abstract: A k-to-2k decoder is provided. Within the final stage of a k-to-2k decoder is a plurality of word line drivers. These word line drivers utilize clocking signals to fire word lines to a memory array. However, power consumption by clocks has become a serious issue with the increase component density on silicon wafers. To alleviate the problem, signals from the first stage of the k-to-2k decoder provide enablement signals to Local Clock Buffers (LCBs) that allow the word line drivers to fire. The enablement signal reduces the number of active buffers and signals carried to word line drivers, reducing power consumption.

Abstract: There is provided a receiver comprising: a control unit for controlling the functions of the receiver; a receiving unit for receiving data signals and timing signals; and a digitally controlled delay line unit connected to the receiving unit and to the control unit. The control unit is configured to measure several samples of the received data signal and the timing signal, to determine average values of the several measured samples of the data signal and the timing signal for defining compensation values, and the digitally controlled delay line unit is configured to adjust the number of unit delay elements for compensating for skew between the data signal and the timing signal on the basis of the defined compensation values.

Abstract: A method and apparatus for receiving one of a plurality of Ethernet transmission protocol signals is disclosed. Each transmission protocol signal includes a plurality of transmission signal streams. The method includes determining which of the transmission protocol signals is being received. An analog front-end processor is connected to one of a plurality of protocol digital processors based on the transmission protocol signal being received. A setting of at least one functional parameter of the analog front-end processor and/or the protocol digital processors is selected based on the transmission protocol signal being received. A sampling rate of the analog front-end processor and/or a processing rate of the protocol digital processors are selected based on the transmission protocol signal being received. The plurality of transmission signal streams of the transmission protocol signal being received by the analog front-end processor are ADC sampled based on a shared clock source.