Abstract: Systems, devices, processors, and methods are described which may be used for the reception of a wireless broadband signal at a user terminal from a gateway via a satellite. A wireless signal may include a series of physical layer frames, each frame including a physical layer header and payload. The received signal is digitized and processed using various novel physical layer headers and related techniques to synchronize the physical layer frames and recover data from physical layer headers for purposes of demodulation and decoding.

Abstract: A method and device is provided for detecting data symbols in a received radio signal. Each data symbol is allocated transmit-side a symbol value-specific PN sequence of successive PN chips in the chip clock, and the allocated PN sequences are offset QPSK modulated. The method for incoherent detection includes converting the received radio signal into a complex baseband signal sampled in the chip clock, generating a demodulated signal by differential demodulation of the complex baseband signal, calculating correlation results by correlating the demodulated signal with the derived sequences, and deriving the values of the data symbols by evaluating the correlation results. Each derived sequence is assigned to a PN sequence allocable transmit-side and includes derived chips, whose values correspond to a logic linking of particular PN chips of the PN sequence allocable transmit-side that is assigned the derived sequence. The invention relates furthermore to a corresponding receiving unit.

Abstract: In one embodiment, a circuit provides two quadrature components, I and Q, from a received modulated signal, from three mutually phase-shifted components of the received signal. The circuit can demodulate three mutually phase-shifted components of a baseband signal, in order to provide two quadrature demodulation components. The circuit includes three circuit inputs, each designed to received said three components, respectively. The circuit further includes a first and second adder circuit. The circuit also includes a bank of weighting circuits linked, at input, to the three circuit inputs and linked, at output, to the inputs of the first and second adder circuits so as to transmit to each adder input, with a determined weighting, a particular one of said three components, the weightings being chosen so that the first and second adder circuits provide said two quadrature demodulation components.

Abstract: To detect phase mismatches between in-phase and quadrature signals of a quadrature demodulator. The phase mismatches can be detected using the signals obtained by removing high frequency components of output of a multiplier by a low pass filter, the output being the product of the in-phase signals of which low frequency components are removed by a first high pass filter by the quadrature signals of which low frequency components are removed by a second high pass filter.

Abstract: A receiver can be configured to include an RF front end that is configured to downconvert a received signal to a baseband signal or a low Intermediate Frequency (IF) signal. The receiver can downconvert the desired signal from an RF frequency in the presence of numerous interference sources to a baseband or low IF signal for filtering and channel selection. The filtered baseband or low IF signal can be converted to a digital representation. The digital representation of the signal can be upconverted in the digital domain to a programmable IF frequency. The digital IF signal can be converted to an analog IF signal that can be processed by legacy hardware.

Abstract: A receiver system for early detection of a segment type of an input signal based on BPSK and DBPSK modulated carriers is provided. The receiver system includes a tuner that converts the input signal into an intermediate frequency (IF) signal, a signal conditioning module that converts the IF signal into a baseband signal, a Frequency Domain Synchronisation (FDS) block that detects the segment type of the input signal based on a carrier powers, a Transmission and Multiplexing Configuration Control (TMCC) decode block that performs a decoding operation on the received signal, a channel estimation block that estimates a channel and obtains a channel information. The TMCC decode block uses the channel information obtained from channel estimation block to correct a fast-frequency selective fading on the received signal before the decoding operation.

Abstract: A quadrature signal phase controller includes a first phase shifter and a second phase shifter. The first phase shifter generates phase shifted first in-phase differential output signals and phase shifted first quadrature-phase differential output signals. The second phase shifter generates phase shifted second in-phase differential output signals and phase shifted second quadrature-phase differential output signals. Each of the first and second phase shifters increases or decreases the phase difference between the first in-phase differential output signals and the second quadrature-phase differential output signals, and the phase difference between the second in-phase differential output signals and the first quadrature-phase differential output signals, in response to a change in a level of the first control signal and a change in a level of the second control signal.

Abstract: A receiving circuit includes a positive-side level judgment circuit, a negative-side level judgment circuit, and a gate circuit, and is configured to receive input of an AMI-coded signal, convert the signal to a binary output signal, and output the same. The positive-side level judgment circuit judges whether the voltage of an input signal is greater or less than a threshold on the positive side. The threshold on the positive side is provided with a hysteresis characteristic by a positive feedback. The negative-side level judgment circuit judges whether the voltage of an input signal is greater or less than a threshold on the negative side. The threshold on the negative side is provided with a hysteresis characteristic by a positive feedback loop. The gate circuit logically combines the outputs of the positive-side and negative-side level judgment circuits so as to generate the output signal.

Abstract: The present invention provides a method of processing signal data comprising generating a first clock signal and a second clock signal and processing the signal data using the first clock signal and the second clock signal. While processing the signal data, the phase difference between the first clock signal and the second clock signal is measured and corrected for so that a target phase difference between the first clock signal and the second clock signal is maintained.

Abstract: A demodulation circuit demodulates a differential phase shift keying (DPSK) modulated received signal. A phase difference data generator compares phase data representing a phase of the received signal input at every predetermined sampling time with previous phase data preceding by one symbol time to generate phase difference data representing a phase shift amount of the phase data. A symbol selection unit evaluates the phase difference data generated at every sampling time to select as a symbol.

Abstract: An apparatus and method is described that provide an efficient blind channel estimation approach for PSK and DPSK modulated multicarrier communication systems. With the requirement that the channel phase difference between any two adjacent carriers is smaller than one half of the minimum phase difference between two symbols of the PSK or DPSK constellation, a low-complexity deterministic approach to channel estimation is devised. This approach is highly effective, robust, and particularly useful for time varying channels with low AWGN noise.

Abstract: A method and device is provided for the detection of data symbols contained in a received radio signal, whereby each data symbol is allocated transmit-side a symbol value-specific PN sequence of successive PN chips in the chip clock and the PN sequences allocated to the data symbols are offset QPSK modulated. The method of the invention for incoherent detection provides for converting the received radio signal into a complex baseband signal sampled in the chip clock, generating a demodulated signal by differential demodulation of the complex baseband signal sampled in the chip clock, providing the derived sequences, calculating correlation results by correlating the demodulated signal with the derived sequences, and deriving, i.e., detecting, the values of the data symbols by evaluating the correlation results.

Abstract: A differential phase shift keying demodulator having an input structured to receive current data representing a current phasor and past data representing at least two past phasors, and a phase differentiator structured to process the current data and reference data representing a reference phasor to provide resulting data representing a phase difference between said current and reference phasors. The differential phase shift keying demodulator also includes a reference phasor computational module configured to generate said reference data basing on said past data representing the at least two past phasors.

Abstract: An apparatus and method is described that provides optimal D-PSK demodulation based on the distribution of phase differences between successive D-PSK symbols. A plurality of D-PSK data symbols are received, and each symbol is characterized by a real component and an imaginary component. An angle of correlation between any two successive symbols is calculated. A variance of correlation angles is obtained by using data symbols or pilot symbols, if available. The probability of the correlation angle being each of possible phase difference according the D-PSK constellation is then determined. From the probabilities of the particular correlation angle, a probability of each input bit being a “0” or “1” is determined.

Abstract: A system and method for data communication over a cellular communications network that allows the transmission of digital data over a voice channel of the communications network. Digital data is encoded into DBPSK data using differential binary phase shift keying encoding. The DBPSK data is then sent across the cellular network using a vocoder having a linear predictive or other speech compression codec. At the receiving end, the DBPSK data is demodulated back into the original digital data. This approach permits data communication via a CDMA, GSM, or other type of voice traffic channel at a low bit error rate.

Abstract: A quadrature signal phase controller includes a first phase shifter and a second phase shifter. The first phase shifter generates phase shifted first in-phase differential output signals and phase shifted first quadrature-phase differential output signals. The second phase shifter generates phase shifted second in-phase differential output signals and phase shifted second quadrature-phase differential output signals. Each of the first and second phase shifters increases or decreases the phase difference between the first in-phase differential output signals and the second quadrature-phase differential output signals, and the phase difference between the second in-phase differential output signals and the first quadrature-phase differential output signals, in response to a change in a level of the first control signal and a change in a level of the second control signal.

Abstract: An OFDM receiver apparatus receives an OFDM signal including a plurality of DBPSK signals transmitting identical information. An extraction unit extracts the plurality of DBPSK signals from the OFDM signal. A phase difference calculation unit calculates a phase difference between symbols of each of the plurality of extracted DBPSK signals. An accumulation unit accumulates the plurality of phase differences. A decision unit decides data transmitted by the DBPSK signals on the basis of an accumulation result.

Abstract: The present invention provides a light receiving apparatus using the DQPSK demodulation method. The light receiving apparatus comprises: one Mach-Zehnder interferometer for branching a received light signal into light signals at two arms to allow the branched two light signals to interfere with each other; one balanced photoelectric converter for converting the two interfered light signals, by using the Mach-Zehnder interferometer, into an electric signal corresponding to a difference between light intensities of the two light signals; and a phase adjuster for dynamically shifting the phase of a light signal passed through one of the two arms at the Mach-Zehnder interferometer.

Abstract: A differential receiver which provides for estimation and tracking of frequency offset, together with compensation for the frequency offset. Estimation and tracking of the frequency offset is undertaken in the phase domain, which reduces computational complexity and allows frequency offset estimation and tracking to be accomplished by sharing already-existing components in the receiver. Compensation for the frequency offset can be performed either in the time domain, before differential detection, or in the phase domain, after demodulation, or can be made programmably selectable, for flexibility.

Abstract: A system and method for implementing an IQ generator includes a master latch that generates an I signal in response to a clock input signal, and a slave latch that generates a Q signal in response to an inverted clock input signal. A master selector is configured to provide a communication path from the master latch to the slave latch, and a slave selector is configured to provide a feedback path from the slave latch to the master latch. The foregoing I and Q signals are output directly from the respective master and slave latches without any intervening electronic circuitry.

Abstract: A method and apparatus for frame synchronization in digital communication systems using multiple modulation formats, including the Differential Phase Shift Keying (DPSK), Duobinary Signaling (DBS), and ON/OFF Keying (OOK) modulation formats, perform a search for both a frame alignment sequence (FAS) and the inverted FAS and determine the polarity of the received digital stream.

Abstract: A technique for low-complexity high-performance coherent demodulation of GFSK signals involves utilizing a novel phase and frequency tracking mechanism coupled with a trellis search technique to track signal memory in the demodulation process. A method according to the technique may include modeling modulation based upon a trellis. The method may further include estimating unknown parameters, selecting a maximum likelihood path through the trellis, and mapping the maximum likelihood path to an output bit sequence. The technique is also applicable to DSPK and other applicable known or convenient protocols.

Abstract: In the field of communication and transmission, a method and a device for receiving an OPFDM-DQPSK signal are provided. The device includes a power splitter, adapted to split the OPFDM-DQPSK signal into two beams of signals; a polarization beam splitter (PBS), adapted to splitting one of the two beams of signals into a first signal and a second signal; a demultiplexer (Demux), adapted to demultiplex the other beam of signal to obtain a third signal and a fourth signal; two delayers, adapted to delay the third signal and the fourth signal respectively; a first frequency-mixing receiving module, adapted to perform frequency-mixing receiving on the first signal and the delayed third signal; a second frequency-mixing receiving module, adapted to perform frequency-mixing receiving on the second signal and the delayed fourth signal; and a decision recovery module, adapted to recover four logical sequences by performing decision on the four electrical signals.

Abstract: A novel and useful apparatus for and method of nonlinear adaptive phase domain equalization for multilevel phase coded demodulators. The invention improves the immunity of phase-modulated signals (PSK) to intersymbol interference (ISI) such as caused by transmitter or receiver impairments, frequency selective channel response filtering, timing offset or carrier frequency offset. The invention uses phase domain signals (r, ?) rather than the classical Cartesian quadrature components (I, Q) and employs a nonlinear adaptive equalizer on the phase domain signal. This results in significantly improved ISI performance which simplifies the design of a digital receiver.

Abstract: According to one embodiment of the present invention, it is possible to realize a signal transmitter which is capable of reducing power consumption and which can be easily designed. A differential transmitter block outputs differential output signals fixed to a predetermined logic signal to a differential receiver block and disconnects terminating resistors from a signal transmission path in an idle state. In the differential receiver block, a differential comparator outputs a logic determined by symbols of the differential output signal from the differential transmitter block, and an operating state detector detects the idle state upon detection that time successively outputting a predetermined logic by the differential comparator reaches a predetermined time, and controls switches so as to disconnect the terminating resistors from the signal transmitter in the receiving side upon detection of the idle state.

Abstract: The present invention relates to a low power serial link employing differential return-to-zero signaling. A receiver circuit consistent with some embodiments includes an input circuit for receiving differential serial data signals that form a differential return-to-zero signaling and a clock recovery circuit. The clock recovery circuit is coupled to the input circuit and includes a logic gate configured to generate a clock signal by using said differential serial data signals.

Abstract: A receiver includes a signal input for receiving a differentially-encoded quadrature phase-shift keyed (DEQPSK) communication signal. A demodulator performs bit decisions on a received coherent symbol and bit decisions on a received differential symbol. A processor is operative with the demodulator and scales a soft decision by a factor from 0 to 1 when the results of the bit decisions on the received coherent branch and differential branch are different.

Abstract: An acquisition scheme for receiving a Bluetooth basic data rate (BDR) or enhanced data rate (EDR) packet. A simplified acquisition apparatus for a Bluetooth receiver having a phase differentiator, a plurality of basic building blocks, a plurality of 1-bit switch, and a correlation computation equation. It features a simplified acquisition circuit implementation with a 1-bit correlator hardware shared by access code and EDR synchronization sequence correlation computations. A 4 MHz sampling rate is used for correlation computation. A SINC interpolator is then used to get an 8 or 16 MHz timing resolution for data bit decoding. Based on the measurement results, this simple acquisition scheme can support successful decoding of a received Bluetooth packet with a maximum timing offset of +/?40 ppm and a maximum frequency offset of +/?60 ppm without loss of receiver sensitivity.

Abstract: A network device includes a first demodulation path to recover a header portion of a data packet. A second demodulation path recovers a payload portion of the data packet. The second demodulation path includes a down sampler to down sample a payload portion of the data packet. An equalizer equalizes an output of the down sampler. A correlator receives an output of the equalizer. A demodulation controller selects the output of the equalizer or an output of the correlator based on the header portion.

Abstract: A method and a device for synchronizing the carrier frequency of a carrier signal comprising a frequency offset and/or a phase offset. According to the invention, the method estimates the frequency offset and/or phase offset of the carrier signal by means of a maximum likelihood estimation from a received signal, which comprises temporally discrete, complex rotary indices, for which only the temporally discrete phases are dependent on the frequency offset and/or phase offset. An offset quadrature-modulated received signal is thus converted into a modified received signal comprising temporally discrete, complex rotary indices, for which only the temporally discrete phases are dependent on the frequency offset and/or the phase offset.

Abstract: An encoding and/or decoding communication system comprises a framer interface, an encoder, a multiplexer, an output driver, and a clock multiplier unit (CMU). The encoder includes an input latch circuitry stage; an output latch circuitry stage; an intermediate latch circuitry stage interposed between the input latch circuitry stage and the output latch circuitry stage, the intermediate latch circuitry stage coupled to the input latch circuitry stage and the output latch circuitry stage; a plurality of encoding logic circuitry stages interposed between the input latch circuitry stage and the output latch circuitry stage, a last one of the plurality of encoding logic circuitry stages placed adjacent to the output latch circuitry stage and coupled to the output latch circuitry stage; and a feedback between the output latch circuitry stage and the last one of the plurality of encoding logic circuitry stages.

Abstract: A mixer circuit accumulates I signal (digital signal of first channel) having its band limited by low-pass filter and first carrier signal to perform two-phase shift keying modulation thereon. An adder adds fundamental-wave component of bit clock signal BCK into Q signal (digital signal of second channel) having its band limited by the another low-pass filter to obtain a resultant added-up signal. Another mixer circuit accumulates the added-up signal and second carrier signal to perform two-phase shift keying modulation thereon. Output signals of the mixer circuits are input to another adder so that they may be added up to obtain a QPSK signal as a modulated quadrature signal. The QPSK signal contains frequency signals whose frequencies are a sum of bit clock frequency and carrier frequency and a difference between them. When demodulating, the carrier signal and the bit clock signal are reproduced using the frequency signals.

Abstract: A receiver including first circuitry configured to combine corresponding soft decision values from at least two groups of RDS/RBDS data transmitted as part of a broadcast channel to generate a set of combined values and second circuitry configured to identify a subset of the combined values that indicate a relatively constant subset of the received values from the at least two groups of the RDS/RBDS data is provided.

Abstract: A D-PSK demodulator utilizes a two-layer coherent approach to estimate the phase shift of adjacent symbols. There is generated a probability set of each received symbol being one of possible constellation values. There is also generated a probability set of each of possible phase difference between two adjacent symbols. This probability set is then converted into soft bit information according to specific mathematical operation.

Abstract: An apparatus and method for improving a symbol error rate of an M-ary phase shift keying (M-PSK) system having a quadrature error are provided. The apparatus includes: a conversion parameter detector that detects a conversion parameter and converts a symbol decision region using the quadrature error and at least one pair of first received symbols; and a converter & determiner converting a pair of second received symbols using the detected conversion parameter, and determining a transmission symbol according to a symbol of the converted pair of second received symbols. An increase in a symbol error rate due to the quadrature error can be prevented and the quadrature error can be easily estimated.

Abstract: A display apparatus which processes an input image signal to display it thereon having a connector which is connected with an external source, a differential signal receiver which processes a differential signal from the external source, and a differential signal controller which generates a predetermined temporary differential signal using a single ended signal transmitted from the external source and outputs it to the differential signal receiver. Thus, the display apparatus generates a temporary differential signal corresponding to an input single ended signal to process it as a differential signal, and a control method thereof.

Abstract: A FFR (fractional frequency reuse)-based network MIMO (multiple-input multiple-output) transmission architecture in a cellular system that employs cell sectoring using directional antennas. Each cell is sectorized into three outer sectors using three directional antennas which transmit in three different directions using three different frequency subbands. The cell sectors are arranged based on a frequency partition scheme so that three sectors in three neighboring cells form a coordinated group for network MIMO transmission. A regular and a rearranged frequency partition are described. Further, a practical implementation of SON (self organizing network)-based three-cell FFR-based network MIMO for a wireless OFDM system is described.

Abstract: Embodiments for non-coherent phase differential and multiple orthogonal signal modulation/demodulation are disclosed. One illustrative embodiment may include: a method for non-coherent reception of a signal with spectrum spreading, comprising performing a multiple orthogonal signal demodulation operation on the signal; performing a phase differential demodulation operation on the signal; and combining the results of the multiple orthogonal signal demodulation operation on the signal and the phase differential demodulation operation on the signal.

Abstract: An apparatus for demodulating an analogue input signal comprises a hard limiter stage (4) for converting the signal to a two level signal. A digital down converter/low pass filter stage (6) converts the signal to a base band signal, and a symbol synchronization stage (8) extracts symbol timing. An instantaneous phase detector (10) calculates the instantaneous phase of the one or more symbols associated with the input signal. If the input signal has been modulated according to a pi/4DQPSK, pi/2DBPSK, GMSK, or a GFSK modulation scheme, a differential detector (12) determines a difference in the phase between adjacent symbols, a coarse frequency offset compensation stage (14) applies a compensation signal to compensate for frequency offset, and a frequency offset estimation stage (16) updates this compensation signal. A demapper (18) generates a demodulated output signal after compensation by the frequency offset compensation stage.

Abstract: A differential receiver which provides for estimation and tracking of frequency offset, together with compensation for the frequency offset. Estimation and tracking of the frequency offset is undertaken in the phase domain, which reduces computational complexity and allows frequency offset estimation and tracking to be accomplished by sharing already-existing components in the receiver. Compensation for the frequency offset can be performed either in the time domain, before differential detection, or in the phase domain, after demodulation, or can be made programmably selectable, for flexibility.

Abstract: According to one embodiment, a demodulation system, such as DPSK in a SPS system can be used with soft decision information to correct bit errors. Soft decision information values are utilized to switch hard decision bits of the differentially decoded signal. A parity check can be used to determine if the toggling of the bit corrected the parity error.

Abstract: An aircraft transponder comprises an antenna for receiving an RF signal a downconverter coupled to the antenna for downconverting the RF signal to an IF signal, an analog-to-digital converter coupled to the downconverter to digitize the IF signal to produce a digital signal, and; a processor unit coupled to the analog-to-digital converter. The processor unit is configured to: (1) generate a delayed digital signal; (2) multiply a delayed digital signal by the digital signal to produce a multiplied output; and (3) filter the multiplied output to produce a filtered output having a positive or negative sign. The transponder further includes a sign converter operable to output a one or zero based on the sign of the filtered output to recover the data component.

Abstract: Where the additional data throughput is added using an amplitude offset or a combination of phase and amplitude offset, the legacy differential demodulator does not recover the amplitude information. The present invention provides a method for demodulating amplitude offsets in a differential modulation system in order to recover the amplitude information. The demodulated amplitude information may be used to recover the additional Level 2 data transmitted as an amplitude offset or combination phase and amplitude offset in a differential multiple phase shift keying (D-MPSK) transmission, such as across adjacent OFDM symbols and/or adjacent frequency subcarriers.

Abstract: A system and method for clock data recovery for programming direct digital synthesizers is disclosed. A counter is used to calculate a coarse measurement of the clock frequency of a received digital signal, and a tap delay line is used to calculate a fine measurement of the clock frequency of the received digital signal. The coarse and fine measurements are used to calculate a value for programming a direct digital synthesizer to produce a clock signal that is an approximate replica of the clock frequency of the received digital signal.

Abstract: A method of estimating a signal-to-noise ratio from a received M-DPSK modulated signal, comprising a sequence of N known symbols, based on a division of the known symbols N and of N samples of the received signal at the output of the channel into a number of blocks B of length L with B greater than one.

Abstract: A quadrature signal phase controller includes a first phase shifter and a second phase shifter. The first phase shifter generates phase shifted first in-phase differential output signals and phase shifted first quadrature-phase differential output signals. The second phase shifter generates phase shifted second in-phase differential output signals and phase shifted second quadrature-phase differential output signals. Each of the first and second phase shifters increases or decreases the phase difference between the first in-phase differential output signals and the second quadrature-phase differential output signals, and the phase difference between the second in-phase differential output signals and the first quadrature-phase differential output signals, in response to a change in a level of the first control signal and a change in a level of the second control signal.

Abstract: The objective of this invention is to perform high-precision tracking error detection and tracking control using digital circuitry at relatively low speed and with a small circuit scale. Tracking servo circuit is formed as a single-chip circuit. Low-pass filters (LPF) and gain control amplifiers (GCA) of the input portion are analog circuits, while the circuits after analog-digital (A/D) converters, that is, offset cancellation circuits, equalizers (EQ), first and second phase difference detectors, adder, low-pass filter (LPF), gain control amplifier (GCA), and servo DSP are all digital circuits.

Abstract: A filter-based method of demodulating differentially encoded phase shift keyed (DPSK) optical signals, such as commonly used binary-DPSK (DBDPSK) and quadrature DPSK (DQPSK) signals, that can achieve optimal receiver sensitivity is described. This approach, which combines filtering and differential phase comparison, can reduce the complexity and cost of DPSK receivers by obviating delay-line interferometer-based demodulation. This can improve receiver stability and reduce size, weight, and power, while maintaining the ability to achieve optimal communications performance.

Abstract: A method and apparatus for recovering data by a digital audio interface begins by receiving a stream of biphase encoded data. The processing continues by determining whether a next transition of a frame of the plurality of frames occurs during a first, second, or third time window after a preceding transition of the frame. When the next transition occurs during the second predetermined time, the digital audio interface synchronizes to a data rate of the stream of biphase encoded data based on the next transition and the preceding transition. If, the next transition occurs during the first or third predetermined windows, the digital audio interface synchronizes to a data rate of the stream of biphase encoded data based on the preceding transition edge and a subsequent transition. When the transition occurs during the third time window, the biphase encoding is violated, which indicates that a preamble is being received.

Abstract: Receiver module and receiver formed from several cascaded module. The module comprises inputs (E1, E2, E3, E4) and outputs (S1, S2, S3, S4) connected to a selection means (44) circuit, to a switching means (45) circuit, and to a decoding means (46, 58, 60) circuit. Such modules can be cascaded by simply connecting the corresponding inputs and outputs. The final module delivers the transmitted information. Application to differential phase modulation and orthogonal modulation spread spectrum digital transmission.