Abstract: Error rates above a given threshold are detected by initiating a counter to count a group of n bits on each occurrence of an error bit. The counters are inspected on each occurrence of an error to see whether the counter initiated x error bits earlier is still counting. If the counter is still counting the error rate is above a threshold of x error bits in a group of n bits in a serial stream.

Abstract: A high speed counter circuit for counting electrical pulses includes a master/slave flip-flop at the input stage of the counter. An AND gate logically ANDs the pulses being counted with the master output to produce a first gating signal. A plurality of cascade coupled flip-flops each having a slave and an inverse slave output are provided. The clock input to each cascade coupled flip-flop is produced by the logical OR of the electrical pulses being counted, the first gating signal and the slave output of all preceding flip-flops of the counter. The counter output is provided by the inverse slave output of each flip-flop.

Abstract: A loadable N-bit ripple counter having N bit subcircuits that each inlude a flip-flop and a bit loading element. The flip-flop output is controllable to a known state when a flip-flop control signal is asserted. The bit loading element is connected to receive the flip-flop output and a bit input of a multibit number being loaded and to provide a bit output of the counter, the bit output being controlled by the states of the flip-flop output and the bit input, and, except for the most significant bit, serving as a clock for the next more significant bit subcircuit.

Abstract: A clock generating circuit having at least one loop of at least two stages. Each stage consists of a pass transistor serially connected to an inverter. An inverter couples the end of the loop to its beginning. The gate electrodes of the transistors in the serially connected stages are controlled alternatively by a true and a complemented clock signal. Preferably, there are two such loops operating in parallel but which include initialization circuitry that initializes the two loops to complementary values.

Abstract: A pipeline binary updown counter is comprised of simple stages that may be readily replicated. Each stage is defined by the Boolean logic equationA.sub.n (t)=A.sub.n (t-1).sym.[(U.multidot.P.sub.n)+(D.multidot.Q.sub.n)]where A.sub.n (t) denotes the value of the nth bit at time t. The input to the counter has three values represented by two binary signals U and D such that if both are zero, the input is zero, if U=0 and D=1, the input is -1 and if U=1 and D=0, the input is +1. P.sub.n represents a product of A.sub.k 's for 1.ltoreq.k.ltoreq.-1, while Q.sub.n represents the product of A's for 1.ltoreq.k.ltoreq.n-1, where A.sub.k is the complement of A.sub.k and P.sub.n and Q.sub.n are expressed as the following two equationsP.sub.n =A.sub.n-1 A.sub.n-2 . . . A.sub.1Q.sub.n =A.sub.n-1 A.sub.n-2 . . . A.sub.1which can be written in recursion form asP.sub.n =P.sub.n-1 .multidot.A.sub.n-1Q.sub.n =Q.sub.n-1 .multidot.A.sub.n-1with the initial values P.sub.1 =1 and Q.sub.1 =1.

Abstract: A pulse train divider circuit includes a first flip-flop (1) whose Q output is connected to the D input of a second flip-flop (2) whose Q output is connected to the D input of the first flip-flop (1). A pulse train to be divided is applied via an input (3) directly to the clock input C of the first flip-flop (1) and via a circuit (4) which delays the pulse train applied to the clock input C of the flip-flop (2) to provide a given phase relationship between the pulse trains at the two clock inputs. The circuit divides-by-two, and the resulting divided pulse trains available at the various outputs have phase relationships depending on the phase relationship of the applied pulse trains at the clock inputs.

Abstract: A stable binary counter as applicable to synchronous counters, to frequency dividers and more particularly to microwave integrated circuits is constituted by a plurality of elementary counters mounted in cascade. Each elementary counter is formed by a half-adder having two inputs, one "sum" output and one "carry" output. The "sum" output is connected to the input of a master-slave flip-flop, the output of which is connected in a feedback loop to one input of the half-adder. The master and slave flip-flops are controlled by the two complementary waveforms of a single clock signal. The "carry" output of one half-adder is connected to the input of the following half-adder.

Abstract: In a binary counter made using the I.sup.2 L technique, the realization of different gate types is complicated, because only NAND gates can be obtained directly. According to the invention, a particular circuit construction is indicated, which is constructed according to the I.sup.2 L technique, is very simple and requires only a few gate transit times so that a comparatively high switching speed can be attained. In the circuit construction of the invention, both the flipflops and their associated combinatorial networks are fabricated in the I.sup.2 L technique, using only NAND gates. Nevertheless, because of the particular circuit configuration of the invention, all of the necessary internal signals can be generated in an efficient manner.

Abstract: A programmable divide-by-N counter employs a plurality of speed enhancement techniques to provide an overall operational speed corresponding to the speed at which a single-clocked flip-flop is capable of being toggled. The counter configuration provides flexibility in selecting the value of N, the programmable divisor, as well as the possibility of increasing the length the counting chain without producing a reduction in overall operational speed. The speed enhancement techniques are primarily located in the reset logic portion of the counter. A key aspect utilized through-out the overall circuit is that critical signal propagation paths in terms of speed of operation present no more than four gate delay intervals in total response time.

Abstract: A weighted event counting circuit comprises a cascade connection circuit composed of a plurality of frequency dividing circuit means and a plurality of coincidence detecting circuit means inserted between the frequency dividing circuit means, and input circuit means to supply digital data representing the occurrence of plural events to the coincidence detecting circuit means. The number of occurrence times of the plural events is counted and totalized with weighting.

Abstract: A multi-digit counter circuit performs both successive data production function and non-successive data production. Successive data is produced by an increment or decrement operation according to a first carry (borrow) signal. Non-successive data is produced by a control circuit which applies a second carry (borrow) signal independently of the first carry (borrow) signal to an arbitrary selected digit or digits. The arbitrary digit is designated according to the distance between the preceding data and the following data to be produced.

Abstract: A circuit for providing an indication of watt-hours from a voltage input that is an analog of watts comprises a source of a high-frequency square wave and a precision triangular wave at a frequency that is derived from the high-frequency square wave by frequency division. A time interval is derived by selecting a period between a time when the triangular wave crosses zero volts and the time at which the amplitude of the triangular wave equals the analog input voltage. A count of the number of cycles of the high-frequency signal during that interval provides a measure of the value of the input voltage, and a continuing count of that number of cycles provides a time-integrated value of the count. When the input signal is analogous to watts, the integrated output provides a measure of watt-hours.

Abstract: A high speed, low power, multi-bit, single edge triggered, wraparound binary counter is provided which is resettable and loadable from a user-supplied address. The binary counter requires a relatively small amount of power due to the use of CMOS technology for construction of its circuitry, may be initiated at any of 2.sup.N (where N=bit count) start locations, and can be easily adapted to accommodate any desired number of counter cells. Further, it is capable of operating over wide ranges of temperatures and power supply conditions. The high speed binary counter is formed of a plurality of counter cells in which each counter cell includes a pass gate device responsive to a counter-update signal for allowing true and complement addresses to control a switching device when the counter-update signal is in the low state and for isolating the true and complement addresses from the switching device when the counter-update signal is in the high state.

Abstract: A system for sensing the position of an object such as a rotating member has a plurality of photocouplers coupled with the interposition of a rotary disc having slits and rotating with the object. The system further has a position signal generating circuit for receiving signals produced by the photocouplers and producing a series of component position signals differing in phase successively by a predetermined phase difference, a counting circuit having an up/down count for determining the position of the object by counting occurrences of a predetermined change recurring periodically in the component position signals, and a direction determining circuit for producing an up/down signal for controlling the counting mode of the up/down counter. Each time the predetermined change occurs in any one of the component position signal, the direction determining circuit determines the order in which the change occurs in two successive component position signals.

Abstract: The present invention performs analog to digital conversion using the system clock of a microprocessor, the system clock being the clock which controls the rate of operation of the microprocessor. A varying analog signal is applied to the clock frequency control input of the microprocessor, thereby causing the clock frequency and the rate of operation of the microprocessor to vary in accordance with the varying analog signal. The clock is counted for a predetermined period of time. In the preferred embodiment this predetermined period of time is set by the 60 Hz AC power line. The counted contents at the end of this predetermined period of time is a digital representation of the varying analog signal. The microprocessor includes circuits for performing other operations at the rate set by the clock frequency. The other operations performed by the microprocessor must not be deleteriously affected by the varying rate of operation caused by the varying analog signal.

Abstract: A synchronous binary circuit comprising a counter including J-K flip-flops constituting lower l bit stages and higher m bit stages, first logic means for feeding, to J and K input terminals on each of flip-flops among the lower l bit stage flip-flops higher than the second bit stage, an AND of non-inverted outputs of all the lower stage flip-flops than the pertinent stage, second logic means for feeding, to the J and K input terminals of the first stage flip-flops among the higher m bit stage flip-flops, a first logical product of the non-inverted output of a one bit lower stage flip-flop and non-inverted outputs of the first to (l-1)-th bit stage flip-flops among the lower bit stage flip-flops, and third logic means for feeding, to the J and K input terminals of flip-flops among the higher m bit stage flip-flops higher than the second stage, a second logical product of non-inverted outputs of the lower first to (l-1)-th bit stage flip-flops and a third logical product, the third logical product being a logic

Abstract: A clock frequency divider circuit for producing signals of a desired frequency (of, for example, 1.024 MHz) in response selectively to input clock pulses of two or more different predetermined frequencies, wherein control pulses are produced from and in synchronism with the input clock pulses and are fed to a frequency division network including two master-slave "D" flip-flop circuits adapted to produce a first predetermined fraction of the frequency of the control pulses in response to input clock pulses of a first frequency (of, for example, 2.048 MHz conforming to CCITT Recommendation standard) or a second predetermined fraction of the frequency of the control pulses in response to input clock pulses of a second or third frequency (of, for example, 1.536 MHz or 1.544 MHz conforming to T-1 standards).

Abstract: An M-bit binary counter is disclosed having M sequentially ascending binary value stages, the first stage being the lowest significant bit. In accordance with the invention, each stage above the least significant bit stage has a subsequent value decoder which has the function of determining the effect of lower order carry bits on higher order stages with a minimum of signal delay. The decoder includes the feature of using natural threshold FET devices in a transfer gate configuration to perform logical AND functions so as to minimize gate delays in decoding a carry condition for higher order stages. A selective up-counting or down-counting function is also disclosed.

Abstract: Sensors in the infeed and output stackers, under control of the microprocessor, monitor the sheets. The apparatus is started automatically by placing sheets in the infeed. A count of the sheets is developed and displayed as the sheets are fed. When the infeed is empty and the output contains sheets, the count is retained. If sheets are removed from the outfeed, the count is retained and is reset only after more sheets are placed in the input. The same rules obtain for batching. The sensors cooperate with singles, holes and doubles detectors and have their gain adjusted depending upon sheet density. Automatic threshold adjustment circuits compensate for dust build-up and component aging. Upon sheet detection, the sensing circuit threshold level is instantaneously shifted to prevent an abrupt change in intensity from the sheet covering the sensor to provide an erroneous indication of the presence of a subsequent sheet or sheets.

Abstract: A clock circuit is initiated by an external trigger pulse. Timing measurements commence at a first rate, and after a first delay (t.sub.1) which is sufficient to allow an oscillator of the clock circuit to stabilize. After a second delay (t.sub.1) the clock circuit operates at a second rate which is half the first rate. The clock circuit then represents the time from reception of the external trigger pulse. The first and second delays are derived by charging a capacitor at a constant rate and comparing the voltage level developed across it with respective reference voltages (V.sub.1, V.sub.2) in comparators.In general, the second rate may be 1/r+1 times the first rate, where r is the ratio of the first delay to the second delay.

Abstract: Diode load emitter coupled logic circuits is described that utilizes forward biased diodes in the load circuits. The load circuits may be comprised of a single diode or two or more diodes connected in series. If a single diode is used in the load circuits, the slope factor of the diode must be greater than or equal to the slope factor of switching transistors in the logic circuit. External bias circuitry provides a bias current which can be varied for varying the frequency of operation of the logic circuit. High speeds at low power dissipations can be obtained since the switching transistors in the logic circuits do not switch completely on and off.

Abstract: Integrable frequency divider circuit, including a preamplifier in the form of a differential amplifier having a signal input for receiving signals to be processed, a reference input and two outputs, a frequency divider having divider stages including a first divider stage, each being in the form of identical series-connected flip-flop cells, the first divider stage having two inputs each being connected to a respective one of the two outputs of the differential amplifier for receiving the signals to be processed, an operational amplifier having an output directly connected to the reference input of the differential amplifier and having two inputs, two resistors each being connected between a respective one of the inputs of the operational amplifier and a respective one of the outputs of the differential amplifier, a capacitor connected between the inputs of the operational amplifier, and another capacitor connected between the output of the operational amplifier and reference potential.

Abstract: A dynamic two-phase circuit arrangement includes two dynamic switching circuits, each of which has an input stage, a non-inverting output stage and an inverting output stage. Two-phase control of the two dynamic switching circuits is effected by two drive pulses. The arrangement also includes combinatorial logic which is operated by the drive pulses to feed counter clock pulses to the first dynamic switching circuit. The first dynamic switching circuit performs a divide-by-two operation in response to the clock pulses and drives the second dynamic switching circuit from its Q-output. The second dynamic switching circuit includes an additional switching transistor which is also driven from the Q-output of the first dynamic switching circuit. This transistor is connected to perform an OR-function with the non-inverting output stage of the second dynamic switching circuit. As a result, this output stage produces shift pulses having half the repetition frequency of the clock pulses.

Abstract: An improved clock circuit in which a counter can begin its counting operation following the release of the reset signal always within one-half of the period of the input clock signal. The input clock signal is applied through a D-type flip-flop to one input of an exclusive-OR gate, and to the other input of the exclusive-OR gate directly. The output of the exclusive-OR gate drives the clock input to the counter. The clock input to the D-type flip-flop is supplied by the reset signal.

Abstract: A counter for the non-volatile storage of an n-bit word includes a storage matrix having 2.sup.m non-volatile electrically programmable storage elements which may be bitwise selected by means of a word shift register and a bit shift register, a binary counter having m+n bistable flip-flops, with each one of the n Most Significant Bit flip-flops being coupled to a storage cell of a non-volatile storage device, and a clock sequence control for providing reset, erase and write pulses.

Abstract: In the disclosed device, a counter digitally counts the used or unused length of a tape, a display using a liquid crystal or the like displays the count, and a switch optionally shifts the count up or down.

Abstract: A frequency generator circuit which provides an output signal which is both synchronous with and proportional in frequency to a clock signal of predetermined frequency in response to an input control signal is provided. A frequency divider portion couples a clock signal of divided frequencies to predetermined control electrodes of series-connected switches which selectively couple an output node to a reference voltage node. A decode portion selectively bypasses predetermined switches in response to the input control signal to selectively couple the reference node to the output node. A latch is coupled to the output node to hold the decoded output signal at a predetermined logic level for a predetermined amount of time.

Abstract: A prescaler circuit which provides an output signal which is synchronous with and proportional in frequency to a clock signal is provided. A counter portion counts a predetermined number of cycles of the clock signal and provides a plurality of count signals after a predetermined number of clock signal cycles. A decoder portion is coupled to the counter portion and couples a reference voltage node to a decoder output in response to both an input control signal and the count signals. A latch portion is coupled to the decoder portion for holding the decoder output, and a delay portion is utilized to provide the scaled output signal after a predetermined amount of time delay. The prescaler utilizes both odd and even scaling factors.

Abstract: A multibit counter circuit uses a plurality of essentially identical stages which each have a feedback circuit, a flip-flop, and a carry circuit. Each of the stages is connected together in essentially the same way. A counter circuit of any desired bit capacity can be relatively quickly and easily formed with a saving in silicon area compared to standard configurations.

Abstract: A circuit responsive to pulses on first and second input signal lines for blocking the propagation of these pulses and inhibiting the production of corresponding pulses on output lines when pulses are present at the same time on the input lines and for producing output pulses corresponding to the pulses on the input lines when there is no coincidence or concurrence of pulses on the two input lines.

Abstract: A frequency dividing ratio setting device capable of successively changing the frequency dividing ratio of a programmable counter and further changing the changed portion of the frequency dividing ratio is provided. The device comprises a circuit for generating a pulse signal corresponding to predetermined data, an adder-subtracter having first and second input terminals and adding or subtracting data supplied to first and second input terminals thereof, said first input terminal being connected to the output terminal of the pulse signal generating circuit, and a shift register to which an output signal is supplied from the adder-subtracter and supplying an input signal to a program terminal of the programmable counter and to the second input terminal of the adder-subtracter.

Abstract: A switched frequency divider is disclosed comprising an array of bistable devices which are linked together so as to propagate through the array a low or high signal applied to an input to the array, first gating means for inserting at least one more bistable device into the array, and second gating means for making such an insertion only when the output of the array completes a cycle. To provide for an output wave form that has approximately a 50 percent duty cycle, the bistable devices are coupled togther in the form of a Johnson counter. To permit a change in the divisor only upon the completion of an output cycle, the second gating means is a bistable device which reads an incoming control signal only when the output of the Johnson counter makes a specified change in state. Advantageously, the switched frequency divider may be used as an FSK modulator to generate different AC frequencies from a single AC input signal in response to a digital data signal applied to the divider as said control signal.