Abstract: An electronic counter such as for use in the odometer of a motor vehicle is provided comprising an array (10) of m rows and n columns of single flip-flop data latches and a central shifting unit (14). The central shifting unit (14) comprises a row of n data latches arranged to read data from and write data to each of the m rows of data latches of the array (10). In operation, the central shifting unit (14) reads data from a row of data latches of the array, performs a shift operation on the data and an invert operation on one of n data latches of the central shifting unit (14) and returns the data so operated on to the row of data latches in the array (10). By these steps, a counting operation in Johnson code is performed on the data. This invention uses less chip area than known counters.

Abstract: A counter slip control circuit is described for digital transmission systems wherein the counter uses a feedback circuit to define the permissible counter states. The slip control input modifies the feedback function so that certain counter states are either repeated or skipped. A repeated counter state is equivalent to retardation of the counter output signal phase. A skipped counter state is equivalent to advancing the counter output signal phase. The slip control gate is eliminated from the clock input line to the counter and instead is included in the feedback path which eliminates the skew problem and permits the equivalent of adding clock pulses without the requirement for logic speeds of twice the normal clock speed.

Abstract: A tone generator for producing a plurality of output tone waveforms for a plurality of frequencies, includes an encoder for selectively generating a first waveform that has a first number of states and second waveform that has a second number of states which are less than the first number of states. A control circuit is connected to the encoder and selects the second waveform for higher frequency output tones and the first waveform for lower frequency output tones. The control circuit provides a control clock signal to the encoder for determining the frequency of the output tones. A low pass filter is connected to the encoder for filtering the output tones. The encoder includes a plurality of flip flips having outputs connected to a summer by gates that are actuated by the control circuit.

Abstract: A pulse width control circuit for providing a control signal to adjust variations of electrical characteristics among a plurality of printing elements has an up/down counter and a plurality of control signal generating circuits. The up/down counter counts the number of pulses of a clock signal and delivers the counted value. The control signal generating circuit compares the counted values from the up/down counter with set values corresponding to conduction time periods of the currents used for driving light emitting diodes, and generates a plurality of control pulse signals having pulse widths whose central positions thereof are in accord with each other.

Abstract: A liquid crystal display device comprises first and second substrates coated on the inner surfaces thereof with electrodes, at least one of said first and second substrates including an extended portion thereof with projects beyond the edge of the other of said substrates, a sealing member disposed around the periphery enclosing liquid crystal material and sealing between the substrates, input conductors disposed on the inner surface of said extended portion and electrically connected to said electrodes, a plurality of driving integrated circuit chips mounted on the inner surface of said extended portion and electrically connected to said input conductors, including a plurality of pairs of input terminals thereof electrically connected, one input terminal constituting each pair is arranged in the reverse order on one side of a reference line with respect to the other constituting the pair on the other side of a reference line, metal film conductor formed on the inner surface of said extended portion and conne

Abstract: A counter for counting clock pulses and having a plurality of output bits successively numbered from a first output bit to a highest output bit. The counter includes a plurality of bistable devices, one bistable device being associated with each output bit, and each bistable device including a clock input for receiving clock pulses to be counted, and an output for providing one of the output bits and its complement. The bistable device which is associated with the first output bit toggles with the receipt of each clock pulse to be counted. The counter also includes a decode section responsive to the outputs of the plurality of bistable devices for providing decoded signals, and a select section for receiving the clock pulses to be counted and responsive to the decoded signals and the complement of the first output bit. The select section selects which of the plurality of bistable devices associated with the second and higher output bits will toggle on the receipt of the next clock pulse.

Abstract: The digital frequency divider (or synthesizer) produces non-integral submultiples of an input frequency by alternately dividing its input by two integers by means of two integral digital frequency dividers, one of which produces an output higher than the desired non-integral submultiple and the other of which produces an output lower than the desired non-integral submultiple. The desired non-integral submultiple is obtained by alternately switching the circuit output to two integral digital dividers, the duty cycle of the switch determines the precise output frequency obtained. The concept can be implemented with programmable digital counters and logic circuitry. The circuitry can be used to implement a novel method of duplicating an accurate signal with improved stability. A circuit useful in practicing the method measures the ratio of two frequencies.

Abstract: A clock frequency divider circuit for producing signals of a desired frequency (of, for example, 1.024 MHz) in response selectively to input clock pulses of two or more different predetermined frequencies, wherein control pulses are produced from and in synchronism with the input clock pulses and are fed to a frequency division network including two master-slave "D" flip-flop circuits adapted to produce a first predetermined fraction of the frequency of the control pulses in response to input clock pulses of a first frequency (of, for example, 2.048 MHz conforming to CCITT Recommendation standard) or a second predetermined fraction of the frequency of the control pulses in response to input clock pulses of a second or third frequency (of, for example, 1.536 MHz or 1.544 MHz conforming to T-1 standards).

Abstract: A gating arrangement for a pulse compression circuit includes a surface acoustic wave delay line SAW responsive to an input pulse to generate a frequency-modulated radio-frequency output signal which is applied to an output gate OG. The output signal is also applied to circuit means DC operable to product a digital pulse corresponding to each cycle of the output signal. The pulses are counted by a counter CT and applied to control means CM. This responds to first and second predetermined counter states to control the operation of the output gate OG.

Abstract: A high-speed programmable timing generator in which a continuously cycling binary count is compared with an input data word. Predetermined bits, starting from the highest-order end of the counter, can be selectively inhibited to effectively vary the cycle period of the counter. The digital word with which the output of the counter is compared can be varied to set the reference phase of the output timing pulse stream. Further, fine delay adjustment of the phase of the output timing pulse stream is effected by a controllable phase-locked loop.

Abstract: A counter counts clock signals following a reference signal to provide an address for accessing a memory wherein marks are stored at respective addresses corresponding to desired timing signals with respect to the reference signal. The memory has plural channels, all of which are accessed by the same count value, to provide different timing signals on different channel outputs corresponding to the marks stored in respective portions of the memory. Different sets of timing signals can be stored in different memory blocks, and the memory block which is accessed by the count value can be selected. The memory can be divided into plural memories of smaller capacity, and low speed memories can be used. A timing signal with respect to a first reference signal can be provided after the occurrence of the subsequent reference signal.

Abstract: A frequency generator circuit which provides an output signal which is both synchronous with and proportional in frequency to a clock signal of predetermined frequency in response to an input control signal is provided. A frequency divider portion couples a clock signal of divided frequencies to predetermined control electrodes of series-connected switches which selectively couple an output node to a reference voltage node. A decode portion selectively bypasses predetermined switches in response to the input control signal to selectively couple the reference node to the output node. A latch is coupled to the output node to hold the decoded output signal at a predetermined logic level for a predetermined amount of time.

Abstract: A prescaler circuit which provides an output signal which is synchronous with and proportional in frequency to a clock signal is provided. A counter portion counts a predetermined number of cycles of the clock signal and provides a plurality of count signals after a predetermined number of clock signal cycles. A decoder portion is coupled to the counter portion and couples a reference voltage node to a decoder output in response to both an input control signal and the count signals. A latch portion is coupled to the decoder portion for holding the decoder output, and a delay portion is utilized to provide the scaled output signal after a predetermined amount of time delay. The prescaler utilizes both odd and even scaling factors.

Abstract: A multibit counter circuit uses a plurality of essentially identical stages which each have a feedback circuit, a flip-flop, and a carry circuit. Each of the stages is connected together in essentially the same way. A counter circuit of any desired bit capacity can be relatively quickly and easily formed with a saving in silicon area compared to standard configurations.

Abstract: An improved counter wherein consecutively cascaded flip-flops of the prior art are divided into two groups. A first detector produces a first signal in response to a predetermined set of flip-flop states of the first group. A second detector produces a second signal in response to a predetermined set of flip-flop states of the second group. A third detector produces a count output in response to simultaneous existence of the first and second signals. The output from the first group is arranged in phase so that the second signal may be produced before the count output is produced, by applying an inverted output of the first group to the input of the second group.

Abstract: A frequency-dividing circuit comprises an asynchronous counter having a plurality of one-half frequency-dividers connected in series in a plurality of stages in which a master clock signal is applied to an input terminal of the initial stage, for asynchronously producing output signals of each of the one-half frequency-dividers, where the asynchronous counter is set with a preset data n (n is an integer) which is preset according to a desired frequency-dividing ratio when a load pulse is applied, a coincidence detection circuit for detecting the coincidence of a plurality of outputs supplied from the asynchronous counter, and a frequency-divided output signal and load pulse generation circuit supplied with the master clock signal and an output signal of the coincidence detection circuit, for generating a frequency-divided output signal and a load pulse. The frequency-divided output signal and load pulse generation circuit supplies a load pulse to the asynchronous counter.

Abstract: A signal generator which may be fabricated as monolithic integrated circuit is disclosed. The signal generator includes a counter having a plurality of stages and providing parallel outputs and a plurality of flip-flops. A programmable logic array capable of functioning as AND and OR logic and composed of a matrix arrangement of programmable elements receives as inputs the parallel outputs of the counter and provides inputs to the flip-flops to generate signals at the outputs of the flip-flops.

Abstract: A clock rate generator is described which can be programmed to provide an output clock rate that is N/M times the rate of a standard clock where N and M are integers. The generator comprises a counter, a programmable memory, reset logic and a clocking control. A standard clock is applied to the counter so that the counter is advanced by one for each clock bit. The output of the counter is connected to the input lines of the programmable memory where a pattern of binary ones and zeros are stored. The output of the programmable memory is applied to the clocking control to combine successive bits of the same polarity. The divisor M is determined by the number of standard clock counts between successive resets of the counter. The multiplier N is determined by the number of output cycles from the clocking control between successive resets of the counter.

Abstract: A frequency generating circuit comprises a piezoelectric buzzer (18) which is driven by a driving signal having a desired frequency and a desired pulse width; a frequency dividing circuit (1) made up of a multi-stage flip-flop array for frequency dividing a reference frequency signal; logic setting means (3.sub.1 to 3.sub.6, 4) which is responsive to a plurality of externally generated setting signals (C.sub.1 to C.sub.

Abstract: Means are described for generating a pair of oscillator signals that will respectively drive P and N channel transistors in Class B. These signals are used to clock a synchronous inverter stage that will only change state during the appropriate time interval. Pairs of such stages are cascaded using common clocking to create a shift register which drives an output inverter, the output of which is coupled back to the input of the register. The output stage also has series-coupled P and N-channel transistor pairs for each pair of clocked inverters. Each transistor pair has its gates driven by the respective pair of clocked inverters. The output stage switches at a frequency which is a submultiple of the oscillator frequency, with the submultiple being equal to the number of inverters minus one. Since the inverters are fully Class B there is no direct current conduction due to simultaneous transistor conduction.

Abstract: The ring counter of this invention is self-initializing and is operable at a clock frequency corresponding to four gate delays and comprises a plurality of master of slave flip-flops, in which this high speed capability is attained by using non-inverting feedback between the first and last flip-flops and by operating the master and slave of each in complementary fashion without requiring the use of a complementary clock signal. The non-inverting feedback takes advantage of the inherent delay between the response of the complementary outputs of each flip-flop.

Abstract: A frequency divider for electric timepieces or the like comprising a first block composed of even clock controlled inverters connected in cascade, a second block composed of even clock controlled inverters connected cascade and a clock controlled signal compounding circuit. The final stage output terminal of the first block is connected to a second input terminal of the clock controlled signal compounding circuit.