Abstract: The present invention is directed to a circuit for detecting the end of a burst count in a semiconductor memory device. The circuit is responsive to a plurality of burst counter output bits and a plurality of burst length selection bits. The circuit is comprised of an array of individual semiconductor devices responsive to the burst counter output bits and the burst length selection bits for producing a transition in an output signal when the burst counter output bits are at a logical combination determined by the burst length selection bits. A method for detecting the end of a burst count in a semiconductor memory device is also disclosed.

Abstract: A counter control circuit of a counter for measuring a pulse period of a video synchronization signal includes a main control unit having a synchronization signal input Sync, and a control signal producing unit including a stop signal generator, a latch signal generator, and a start signal generator. The outputs of the stop, latch and start signal generators are supplied to the counter for controlling the counter to count clock pulses fed from a clock generator in response to receipt of a start signal and output a count value in response to receipt of a latch signal. The main control unit produces sequential control signals during the input of the video synchronization signal differentiated by the clock pulses. The counter control circuit allows the counter to measure a pulse period of an input synchronization signal in a stable state that results in an accurate count value, since the count operation is first stopped and the count value is latched by the clock signal.

Abstract: Integrated counter-based instrumentation for generating a frequency distribution representation such as a histogram. An integrated circuit device includes an event counter to count a number of a predetermined type of events detected in each of a plurality of measurement periods during a first sub-experiment period. A frequency counter coupled to the event counter is to be incremented at the end of each measurement period if the number counted by the event counter meets a first test. A count stored in the frequency counter is provided to a frequency distribution data store at the end of the first sub-experiment period.

Abstract: An m bit counter which counts to a desired clock frequency F.sub.D given a central clock frequency F.sub.C is emulated by a chain of two subcounters. The ratio r of the central clock frequency F.sub.C over the desired clock frequency F.sub.D is factored to r=F.sub.C /F.sub.D =2.sup.n * p, where n is one of zero or an integer (i.e., 0, 1, 2, 3 . . . ) and where p is an integer. A 1 to p subcounter counts from 1 to p driven by the central clock frequency F.sub.C. The output of the 1 to p counter is an intermediate clock frequency which includes a pulse every periodic count from 1 to p. The intermediate clock frequency drives a m+n bit subcounter with the n bits being appended as the least significant bits of the m+n bit subcounter. In this manner, the m most significant bits of the m+n bit subcounter count to the desired clock frequency F.sub.D.

Abstract: A fractional time frequency measuring apparatus includes a divider for dividing a frequency of a signal to be measured with a predetermined division factor; a counter unit for counting the divided signal with a standard clock for every period of the divided signal and outputting count results; a fractional time measuring unit for measuring fractional times produced by the counting with the standard clock; a sequence control unit to form a sequence circuit for sequentially counting the divided signal with the standard clock; a memory unit for holding the count results from the counter unit; a microprocessor for determining a value of the divisional factor, generating a reset signal, and calculating the frequency of the signal to be measured from the count results stored in the memory unit.

Abstract: A programmable burst sequence counter is described. The counter is capable of counting sequences of binary numbers in a linear burst sequence or interleaved burst sequence starting from a initial binary number that is presented to the inputs of the counter. The programmable burst sequence counter is applicable to the generation of addresses for the storage and retrieval of digital data from memory arrays.

Abstract: A computer-implemented method of transmitting images from a transmitter to a receiver (e.g. in a teleconferencing application). A receiver maintains an image in a local storage (e.g. that from a previous frame in a sequence of frames) and the transmitter receives an updated image for a next temporal period (e.g. the next frame). The transmitter divides the updated image into blocks and comparing a rotating pixel sample(s) of each of the blocks from the updated image with a sampled pixel from a local copy of a receiver's image at a same spatial position of the pixel sample(s). The transmitter determines a difference between the rotating sampled pixel of each of the blocks from the updated image and the local copy of the receiver's image. It stores a reference to the block and associates the difference with the reference.

Abstract: A high speed divider circuit is provided for phase-locked loops (PLLs). The divider circuit in the feedback loop of the PLL has two divider circuits, a prescalar divide-by-4 circuit, which receives the high frequency signal from the voltage-controlled oscillator (VCO) of the PLL, and a programmable divide-by-N circuit, which resets itself after counting up to N. Responsive to the reset signal from the divide-by-N circuit, the prescalar divider circuit divides the VCO signal by 4+P, where P is a programmable value. This programmable periodic change in the divisor of the prescalar divide circuit allows the divisor in the classic PLL frequency synthesis equation to be set to nearly any number so that the synthesized output frequency of the PLL can be set with very fine resolution.

Abstract: A counter system has a first counter seeded by several input signals and a second counter seeded by at least a first output from the first counter. A selection signal is input to the second counter to select the use of either an interleaved count sequence or a sequential count sequence.

Abstract: A circuit for detecting pulses in an electric input signal, which pulses are superposed on a specific reference level (U.sub.ref), has an input terminal for receiving the electric input signal, at least a first and a second comparator device, switching means (S.sub.1), an output terminal and control signal generator means. The control signal generator means supply a control signal to the switching means (S1) to control the position of the switching means. The input terminal (1) is coupled to a first input of the comparator devices, whose outputs are coupled to a terminal (c and a respectively) of the switching means (S.sub.1). The output terminal (b) of the switching means is coupled to the output terminal. The first comparator device transfers only pulses whose relative amplitude in relation to the reference level exceeds a first value (U.sub.D1). The second comparator device transfers only pulses whose relative amplitude in relation to the reference level exceeds a second value (U.sub.D2).

Abstract: A periodic signal is produced by counting pulses of a clock during a given period of time. The number of pulses counted is divided by a whole number. A count is then made of a batch of pulses of this clock, the number of pulses in this batch corresponds to the quotient of this division. At each time a batch is completed, a value of a periodic signal is produced.

Abstract: The invention discloses a method and an apparatus for implementing an L phase clock in conjuction with L counters, where L is an integer, to count at a frequency scalable by L.

Abstract: An integrated circuit which includes not only a real time clock, but also an elapsed time counter, and a third counter. The elapsed time counter measures the total number of seconds during which a system has been powered up. The third counter is a "cycle counter," which measures the number of times a power cycle (power-up and power-down) has occurred. Thus, by reading the cycle counter and the elapsed time indicator, the general power history of a system can readily be determined, even if the system itself has totally failed. This integrated circuit is battery backed, and is advantageously combined with a system for which power history must be maintained.

Abstract: A non-volatile electronic counter provides a substantially increased maximum count by utilizing a ring counting sequence to count the first n-1 events out of every n events, and a base-2 counting sequence to count each nth event. Each counting position of the ring counting sequence and the base-2 counting sequence is implemented with a memory stage that stores the logical state of the counting position when power is removed. Each memory stage can be implemented with redundant memory cells and voting logic, which provides the logic state represented by a majority of the redundant memory cells, to increase the reliability of the count.

Abstract: A programmable time-intervals generator comprising first and second digital counters, a memory, a digital divider and a digital adder. On the occurrence of a first event, the first counter starts counting, and on the occurrence of a second event, only the most significant bits of the number counted up to then are stored, thereby providing a division by truncation. From the stored number, at least two discrete fractions are obtained by the divider, whereafter said fractions are summed at the adder which operates on strings of bits. The second counter counts down the sum number and, on becoming cleared, generates a signal.

Abstract: A reload-timer/counter circuit provides a reload-timer function and a counter function commonly and selectively. The circuit is comprised of first, second, third, and fourth registers. The third and fourth registers act as a control status register and a mode register, respectively. The first and second registers act as, in the reload-timer mode a data register and a counter register, respectively, while in the counter mode, the first and second registers act as the counter registers.

Abstract: A programmable counter composed of D-type flipflops receives a clock pulse having a constant frequency and is configured to generate a count pulse when a count value reaches a programmed number. A ring counter composed of D-type flipflops receives the count pulse from the programmable counter. A coincidence detection and control circuit detects a predetermined count value of the ring counter, and modifies the programmed maximum count number of the programmable counter, so that the maximum count value of the programmable counter can be selected from either an ordinary maximum count number or the predetermined maximum count number.

Abstract: A single chip microcomputer includes two kinds of timer circuits which receive a common clock signal. One of the timer circuits generates a first timer signal, and the other generates a second timer signal. When the first timer signal is being reset, the second timer signal is inactive.

Abstract: A synchronous counter circuit comprises first and second counting circuits and a latch circuit. Each of the first and second counting circuits includes a clock terminal for receiving a clock signal, an enable terminal for receiving an enable signal, a counter coupled to the clock terminal for counting pulses of the clock signal, a carry signal generating circuit coupled to the counter for generating a carry signal in response to a finish of the counting of the counter, and a ripple carry signal generating circuit coupled to the clock terminal and the carry signal generating circuit for generating a ripple carry signal in response to the clock signal and the carry signal.

Abstract: A method and apparatus for improving the speed of response and display accuracy of a periodic input signal, of the type having a widely variable frequency, on an analog gauge have a meter deflection representative of the frequency of the input signal. Frequency scaling means are provided for multiplying the frequency of the input signal by a first constant to generate an intermediate signal. Counting means are coupled to the frequency scaling means for counting the frequency of the intermediate signal for a time period which is directly proportional to the maximum sweep deflection arc of the gauge times a second constant, and is inversely proportional to the maximum expected frequency of the input signal. Meter driver means coupled to the counting means are provided for deflecting the meter proportional to the counted intermediate signal frequency.

Abstract: In the transmission of variable length data blocks, where data and addresses share the same bus lines, one of the other signals, which are present anyway (chip-select, CS-, read, write), indicates the block length. The first time slot following the setting of this signal is designated for an address (starting address), all subsequent time slots are designated for data, until the signal is reset. In this way, the length of the data block need not be known at the beginning of the transfer.

Abstract: A timing circuit 10 that can be used to control the flow of fluid according to a specific time period that is allotted for each user includes a initialization circuit 30, a reset counter circuit 32, a flow time counter circuit 38, and a clock circuit 40. The timing circuit 10 accepts a DETECT* input signal, that indicates the presence of a user, and provides a DRIVE output signal that indicates when fluid shall be permitted to flow. The flow time counter circuit 38 is user configurable to provide a maximum flow time period while the DETECT* signal is active. The reset counter circuit 32 ensures that each user is provided with his or her maximum flow time period by introducing a system reset time between consecutive users and by allowing a user to remove him or her self from being detected, thus placing the DETECT* signal in an inactive state and subsequently inactivating the DRIVE signal, for certain periods of time without forfeiting any of his or her allotted maximum flow time period.

Abstract: A counter circuit includes Johnson-type counters of m stages, each counter including a plurality of flip-flops connected in a cascade connection, each flip-flop receiving a clock signal at a respective clock input end. In the constitution, signals at respective output ends of flip-flops in a (k-1)-th stage counter are simultaneously input to respective clock input ends of flip-flops in each counter of a k-th stage and more. As a result, it is possible to obtain a signal having an arbitrary ratio of frequency division with high speed, while relatively simplifying the circuit constitution.

Abstract: A pulse counter has a programmable prescaler that divides the frequency of an input clock pulse signal by a factor designated by a code signal. A counter counts the prescaled clock pulse signal output by the programmable prescaler to generate a count output. A code generator encodes the count output to generate the code signal that controls the programmable prescaler.

Abstract: To sense the presence of written data on an optical disk, the readback signal from the disk is detected, and the intervals between detected signal events are measured. That signal event occurring at an expected time delta after the preceding signal event indicates a valid data signal time delta. Those signal events occurring at an unexpected time delta after the preceding signal event indicates the readback signal to be noise. If the count of valid signal time deltas minus the unexpected time deltas attributed to noise accumulates rapidly along a given track within a given sector of the optical disk that sector is determined to be written. Provision is made for counting signal events in accordance with the specific run-length limited in use.

Abstract: The invention includes a data memory having sequentially stored N-bit words that are each a binary description of a time at which an event is to occur. Also stored is a K-bit word, associated with each N-bit word, that is a binary description of what the scheduled event is to be. The invention utilizes a free-running clock and clock circuitry to gauge when an event should occur. The clock circuitry tallies an N-bit description of running time. M-bits of the N-bit description of running time are specified by a single fast synchronous counter. The remaining N-M bits are specified by two slow counters each of N-M bit capacity. Because incrementation of slow counters creates count settling times that may significantly affect accurate event sequencing, the slow counters are alternately incremented and a multiplexer is used to switch to the counter that will provide a "steady state" count at a scheduled event time.

Abstract: A digital pulse processing device is capable of selecting desired precision. The digital pulse processing device includes a counter group for counting pulses output from a pulse output device, the counter group having a plurality of counters A and B that can be separated from and coupled with each other, a mode control circuit for instructing separation and coupling of the counters A and B, and a control circuit for separating and coupling the counters A and B in accordance with the instruction of the mode control circuit. An overflow condition of the free-run counter B is detected using an overflow flag. Detection of an overflow is conducted by setting the flag when an overflow condition has occurred twice or more. The flag is reset by rewriting the state of the flag by a software. An overflow condition which has occurred for the first time is detected in the conventional manner and is treated as carry or borrow.

Abstract: A fast counter includes a clock generator (18), a control circuit (22), and a counting circuit (12). The counting circuit is formed of at least one uniform delay structure (12a, 12b) having a plurality of counter bit cells (58, 60). The uniform delay structure has a regular configuration suitable for very large scale integration. The fast counter is implemented so as to provide minimal propagation delay at relatively low cost.

Abstract: A counter circuit which incurs a uniform number of logic changes whether the clock signal is rising or falling is used in both a first counter circuit for measuring the reference signal for horizontal scanning period and a second counter circuit for measuring signals in the vertical blanking period. Since the number of logic changes of the flip-flops with respect to the clock signal is uniform, a driving circuit for a solid-state image sensor is realized in which noise in the vertical blanking period does not appear in the video period even if by using 1H delay line.

Abstract: A pulse transfer system is provided by which a pulse signal output from a manual pulse generator unit is transferred to a numerical control apparatus through a wireless channel. Pulses are generated in accordance with the rotation of a knob of the manual pulse generator and are counted from a reference time by a counter. A numerical value of the counter is modulated by a modulation circuit, amplified by a power amplifier circuit, and transferred as a coded signal from an antenna to a numerical control apparatus at each predetermined time. The numerical control apparatus receives the coded signal through the wireless channel and recognizes the pulses from the manual pulse generator. The coded signal transferred from the manual pulse generator unit through the wireless channel is a signal as an absolute position using time as a reference, and thus even if an error occurs during the transfer, the correct number of pulses can be recognized.

Abstract: A circuit that may be implemented in a computer system that will measure the maximum and minimum time intervals for system elements to respond to a request for data or information. The circuit includes control logic that controls operation of the circuit, an up-counter and a down-counter that are used together for measuring the maximum or minimum response time interval, and a display for displaying the maximum or minimum response time interval that is measured during a test period.

Abstract: The horizontal synchronous signal and the vertical synchronous signal included in a composite synchronous signal which is output from one TV camera are separated from the composite synchronous signal. A plurality of TV cameras are controlled on the basis of the horizontal synchronous signal and the vertical synchronous signal so as to produce synchronized video signals from the plurality of TV cameras. These synchronized video signals are easy to compound. In the blanking period of the vertical synchronous signal, the rise period of the synchronous signal is 1/2 of the period of the vertical synchronous signal. Pulses are eliminated alternately in the blanking period by a half killer circuit including a counter and a decoder and having a simple structure, thereby generating a horizontal synchronous signal appropriate for driving the TV cameras.

Abstract: The electronic counter for counting a periodic clock signal generated at a preset clock frequency (f.sub.o) includes a clock circuit generating the periodic clock signal at the preset clock frequency (f.sub.o); an adjustable frequency divider (4) having an output (8), a first input (5) and a second input (7), the first input of the frequency divider (4) being connected to the clock circuit (6) so as to receive the periodic clock signal and the second input (7) of the frequency divider being connected to receive a cycle speed signal (n), the frequency divider (4) containing means to produce a pulsed output signal at a divider output frequency (c.sub.o); a tracking circuit (T) connected to the output (8) of the frequency divider (4) to receive the pulsed output signal at the divider output frequency (c.sub.

Abstract: A frequency division scheme which offsets for a phase lag produced on initial power-on is described. A division ratio of a programmable counter is initially set at a first division ratio at the time of releasing the programmable counter from its reset state. When the first division cycle is complete, the division ratio is reset to its steady state value. Thus, a delay equivalent to the phase lag is produced. A frequency synthesizer is also proposed where the division ratio is set, and a phase difference is detected. Reset signals are continually set while the phase difference is changed. This cycle is continued until the phase difference is reduced to one cycle of the input signals or less.

Abstract: In a reactive volt-ampere-hour meter, either of a pair of electric signals representative of, respectively, an AC voltage and an AC current fed to a load has the phase thereof shifted by 90 degrees to produce a signal representation of a product of the two signals. A cumulative adder cumulates the resulting product signals. A first carry pulse and a borrow pulse are generated in the event of, respectively, an overflow and an underflow during cumulation and are fed to a first and a second up-down counter, respectively. The first up-down counter up-counts the first carry pulses and down-counts the borrow pulses and generates a second carry pulse when an overflow occurs. The second up-down counter up-counts the borrow pulses and down-counts the first carry pulses and generates a third carry pulse in the event of an overflow. An up-counter up-counts the second and third carry pulses from the first and second up-down counters, respectively.

Abstract: A circuit arrangement generates a preset number of output pulses each time between two consecutive input pulses, the distance between the input pulses being subject to variation. The output pulses should be approximately evenly distributed, which even distribution, however, cannot be maintained when the cycle of the input pulses changes. To achieve first and foremost that the total number of output pulses is reached as quickly as possible in the case of a change in the input pulse cycle, the circuit includes a first counter device, which supplies a measure for the cycle duration of the input pulses in relation to a clock pulse, and this measure is used as a preset value for the next cycle for a further counter, which counts down the preset value in period with the clock pulses.

Abstract: A multiple synchronized agile pulse generator is configured as high speed digital/analog test apparatus for providing complex patterns associated with modern avionics systems. The multiple synchronized agile pulse generator includes a network of counters and random access memory (RAM) banks which allow for predetermined hopping of pulse repetition intervals, pulse widths, pulse patterns, pulse amplitudes, and combinations of the above.

Abstract: An uninterrupted event-time recorder enables high-precision measurements of the time-of-occurrence of randomly- and rapidly-occurring, digitally specified events such as the leading and/or trailing edges of asynchronous pulses. The lowest order binary digits of the recorder are constructed of high-speed synchronous integrated circuit counter devices. For an N-bit timer having M low-order bits, the highest order (N-M) bit counting is executed by two parallel (N-M)-bit slow-speed counters, one of which is incremented by the terminal count of the M-bit high-speed counter and the other which is incremented by the most significant bit (MSb) of the M-bit counter. The (N-M)-bit counters are read out through a multiplexer controlled by the MSb.

Abstract: A data link controller receiver is disclosed that includes a series of shift registers and a bit counter that counts the number of received bits. When an end of frame character is received, the value in the bit counter which represents the bit residue is supplied to a bit adjustment counter. The bit adjustment counter is employed to control the operation of the shift register containing the bit residue during a byte adjust operation, in a manner which enables the shift register containing the bit residue to be clocked until the value in the bit adjustment counter is indicative of the number of bits in a defined byte. Accordingly, the bit residue is serially shifted until the least significant bit of the shift register is filled. In addition, a mechanism is provided for loading zeros into the shift register during the byte adjust operation.

Abstract: A circuit configuration for improving the resolution of successive pulsed signals over time includes first and second counters each having one clock input, the clock input of the first counter being supplied with a first clock signal, and the clock input of the second counter being supplied with a second clock signal having a n-multiple frequency of the first clock signal. The first counter has a control input and a counter output, the control input of the first counter being supplied with successive pulsed signals. The second counter has a counter input, an overflow output and a write input, the write input of the second counter being connected to the overflow output of the second counter.

Abstract: An interleaving method and apparatus suitable for burst error correction occurring in data transmission or reading of recording medium. In the interleaving method in which data to be transmitted is once written in a storing means and then read to be output in order different from a writing order, a plurality of counters for dividingly generating addresses of the storing means is used; and an operational relationship between the counters is changed between writing and reading of the storing means. ROMs for address translation can be omitted so that the number of gates is reduced very much. Thus, a reasonable interleaving apparatus suitable for LSI formation can be realized. In addition, since ROMs for address translation interposed between the counter and the storing means in the conventional apparatus are omitted, access time for the storing means can be shortened substantially.

Abstract: Disclosed is a pulse counting circuit for counting pulse signals comprising a first pulse signal generating means for generating a first pulse signal corresponding to an input signal, a counting means for counting at least either of said first pulse signal and a second pulse signal which differ from said first pulse signal corresponding to said input signal, said first pulse signal possessing a pitch set smaller than that of said second pulse signal, and a control means for selectively controlling the operation of said count means for counting said first and second pulse signal.

Abstract: An automatic anomalous event detection method uses a pair of counters to count the occurrence of main triggers simultaneously with the occurrence of advanced triggers indicative of anomalous events as defined by an operator. The anomalous events may be defined as either time or voltage qualified events that occur at a much lower rate than the repetition rate of an input analog signal being measured. When the main trigger counter reaches a maximum count, the count of the advanced trigger counter is compared with a range greater than zero to less than the maximum count modified by an operator specified divider. If the advance trigger count is within the range, then an anomalous event is detected and the next advanced trigger signal causes a portion of the input analog signal to be acquired for storage in a waveform memory and subsequent display of the anomalous event.

Abstract: Modulo timer apparatus including a chain of modulo counter stages is controllable by write signals generated by a central controller. The central controller is operative to generate a write signal corresponding to a selected counter stage, and a digital control signal. The initial counter stage of the chain includes a selecting circuit controlled by the digital control signal to couple either a reference clock signal or the corresponding write signal to the initial counter stage to alter the count thereof. Each successive counter stage includes a corresponding selecting circuit also controlled by the digital control signal to couple either a pulse signal generated from the preceding counter stage as it counts through its modulus value or the corresponding write signal to the successive counter stage to alter the count thereof.

Abstract: A decimetor circuit is constructed to execute an FIR filtering of "n" taps for input data sampled with a sampling frequency "f" and then to resample an output of the FIR filter at a frequency of "f/m". A first counter of a "divided-by-n/m" type is driven with a clock having a frequency of "n/m" of the sampling frequency "f" and selectively operates either in a first counting condition in which the first counter is incremented by one count with each clock pulse of the clock or in a second counting condition in which the first counter is incremented by two counts with each clock pulse of the clock. A second counter of a "divided-by-n" type is driven with the clock and incremented by one count with each clock pulse of the clock. A first decoder is coupled to the second counter for decoding a content of the second counter so as to bring the first counter either into the first counting condition or into the second counting condition.

Abstract: A matrix of multiplexed synchronous binary counters for an integrated circuit comprising a sequence of m counter cells (CC1, CCm) each provided with an individual data input link (Din.1, Din.m) and an individual data output link (Dout.1, Dout.m), and controlled by means of common links comprising a clock link (Clk) for synchronization, a load link (LOAD), and n select links (LS1 to LSn). Each counter cell (CC) includes n memory cells (CM1 CMn), each organized around a unique memory element (B1 to Bn) which is individually selectable by means of the select links (LS1 to LSn), which cells are connected in parallel between the individual data input link (Din) and the individual data output link (Dout) of the said counter cell (CC), and share a common loop memory element (BR) having its data input connected to the individual data ouput link of the counter cell under consideration (CC) via an incrementation circuit.

Abstract: A motor controller provides a digital monostable circuit which generates a control signal indicating whether a field coil within a motor should be turned on or off. Two registers are provided within the digital monostable to store values indicating a fixed off time and a minimum on time. These registers can be loaded with selected values by a microprocessor or other controller. The stored values are selectively loaded into a counter which, when the field coil current reaches a preselected level, turns the supply to the field coil off for a time corresponding to the off time value, then on again for a period at least as long as the minimum on time value. The values in the off time and minimum on time registers can be changed to suit operating conditions of the system, and the controller can be operated in either PWM or open loop mode.

Abstract: An asynchronous nonlogical counting device includes at least a first counter and a second counter connected in cascade. The first counter has a frequency dividing ratio of 2.sup.n where n is a natural number. A control unit produces a control signal based on the count value of the first counter. The second counter has a variable frequency dividing ratio which is based on the control signal. The counting device can be made programmable by substituting a comparator circuit for the control unit. The comparator compares the output of the first counter to an instruction signal from an external source.

Abstract: A counter comprising n one-bit cells receiving a clock signal (CK0) having a frequency f to be counted and a read transfer order (TO). The lower rank p cells operate at the frequency f and the n-p higher rank cells at a frequency f/2.sup.p. The lower rank p cells (51-53) directly receive the clock signal (CK0) at frequency f and, if necessary, the transfer order (TO) synchronized in correspondence with CK0. The higher rank n-p cells receive as a clock signal at frequency f/2.sup.p, a signal (CK1) delayed by at least two periods of said clock signal CK0 and at the most by (2p-2) pulses CK0 with respect to the counting signal of the highest rank cell among the lower rank p cells.

Abstract: An apparatus is described for the dual modulus prescaling of a high frequency signal. The apparatus comprises a dual modulus divider, second divider, synchronization circuit for providing a first modulus control signal to the dual modulus divider, and means for coupling the output of the second divider to the input of the synchronization circuit when a second modulus control signal is in a first state.