Abstract: A shift register has four systems of shift registers for bidirectional scans and normal/redundant lines. The respective systems of shift registers are divided into blocks, so that transmission circuits are provided therebetween. The transmission circuits form switching circuits through transfer gates. The transmission circuits receive output signals from both of the shift registers for the normal/redundant lines, and output only normal output signals to next stage shift registers in accordance with control signals.

Abstract: A method for the resetting of a group of series-connected non-transparent synchronous memory cells. The method includes modifying the clock signals that control the transfer gates of these cells on the activation of a resetting signal to set all the transfer gates in the on state. The method is particularly suited to the resetting of long shift registers such as those used in cryptographic applications, especially in micro-circuit cards, and the reset circuitry can be implemented using conventional logic gates.

Abstract: The scale of a pseudo-random number generating circuit that can select normal or reverse order in which pseudo-random numbers are generated is reduced. The outputs of first and second NOR circuits are selected by a selecting circuit and sent to a parity check circuit. The output of the parity check circuit is directly sent to the right and left shift input terminals of a bidirectional shift register.

Abstract: A start signal is given to an SP.sub.-- I/O buffer through a terminal SP1, and its pulse width is controlled by an SP control circuit. A selection signal SEL is given to a selector circuit so that the data shift direction of a bidirectional shift register is switched. When the shift direction is directed to the other side, the start signal is supplied from a terminal SP2 through an SP.sub.-- I/O buffer. When the shift operation is to be done from the terminal SP1 to the terminal SP2, the output of the 38th stage which precedes the final stage, namely, the 40th stage, by two stages is derived from the terminal SP2 as an input start signal for the succeeding driver, during a time period which is longer than one cycle of a clock signal CLK. According to this configuration, a cascade connection can be realized easily and surely even when a clock signal of a higher frequency is used.

Abstract: A circuit for detecting a synchronization byte when a decoder of a MPEG 2 system performs a parsing on a transport stream. The circuit includes a shift register for receiving a transport packet, 1 byte at a time whenever a clock signal is received, and for outputting the packet to a first comparing device which compares a hexadecimal value 47 (OX47) and the value received from the shift register. A logical sum device sums the signal output from the first comparing device and a reset signal. A first counter has a value of 0 or 1 according to the value output from the first comparing device whenever a clock signal is input to the first counter. A second comparing device is provided for comparing the decimal value of 188 and the value of the first counter. A logical multiplication device multiplies the value output from the first comparing device with the value output from the second comparing device.

Abstract: A very high speed counter system of operating at frequencies of up to around 800 MHz provides timing measurements with accuracies on the order of (1/f) seconds where f is the frequency of operation. The least significant bit of the counter operates at the given frequency of a first clock signal while the other higher order bits operate at a second clock signal where the second clock signal is one-half the frequency of the first clock signal and is inverted. Carry lookahead circuits connected between stages of the second counter operate in conjunction with the clocking scheme to produce a high speed and accurate counter.

Abstract: An integrated circuit counter is capable of implementing a relatively high count while being testable using a relatively low number of clock cycles. A linear-feedback shift register (LFSR) having n bit positions is used as the counter. The feedback path of the shift register includes an exclusive OR (XOR) gate that couples selected bits back to the input of the register, in order to implement a 2.sup.n -1 counter. Combinatorial logic circuitry is included to test the counter in significantly less than 2.sup.n -1 clock cycles. This allows for implementing a testable "watchdog timer" that may be used to detect software runaway conditions in microprocessor systems, among other uses.

Abstract: In order to effectively detect coincidence of consecutively transmitted adjacent data words, a shift register is provided for converting incoming serial data to n-bit parallel data. The serial data includes a plurality of identical words each consisting of n bits. A bit coincidence detector is coupled to the shift register so as to determine if a n-stage shifted bit of a given word coincides with a bit which is included in a word subsequent to the given word and which corresponds to the n-stage shifted bit. The bit coincidence detector generates a coincidence check bit which indicates a bit coincidence result. Both the n-bit parallel data and the coincidence check bit are latched after each word has been converted to corresponding parallel data.

Abstract: The present invention describes a circuit (10) and associated method of operation for implementing bit reversals and shifts of an input data. The circuit (10) includes a plurality of input lines (12), a plurality of output lines (14), a plurality of shifting transistors (16), a plurality of bit reversal transistors (20), control lines (18) and (22) for each, and a controller (24). The plurality of shifting transistors (16) operably couple the input lines (12) to the output lines (14) such that the controller (24) may selectively operate the shifting transistors (22) to produce shifted outputs of the input data D.sub.0 through D.sub.3 on the output lines (14). The controller (24) selectively operates the bit reversal transistors (20) to produce a bit reversed representation of the input data on the output lines (14). Precharge circuit (30) precharges the output lines (14) so that they may be statically driven. The circuit (10) may include multiplexors (25), (26), and (27) to enable arithmetic shifts.

Abstract: Signal processing involves accruing signal charge at photosensors, accumulating samples of the content of several adjacent photosensors in individual potential wells of a CCD according to a predetermined pattern, shifting them into individual stages of a first group of registers, and shifting the contents of the first group of registers into a second register to create a linear filtering operation. Accumulating the samples averages the content of adjacent pixels.

Abstract: A method and apparatus is disclosed for reading data from and writing data to remote registers that are dispersed throughout an integrated circuit chip. Regardless of the size or number of remote registers involved, the operation is accomplished using only two interconnect lines, plus a clock. Each remote register is associated with a unique address. During a write operation, a microprocessor loads the write data into a staging register, loads the destination address into a header generation register along with a read/write control bit, and loads a count value into a clock. Thereafter, the apparatus of the invention proceeds automatically, as the clock counts down, to shift the data onto a serial data line following a header. Each of the remote registers in the system are arranged serially, and each monitors the header information, comparing the address contained in the header with its own address.

Abstract: Within an integrated circuit a source of digital data is coupled to a distant destination by a serial data path that is characterized by being either an imperfect and lossy transmission line or as possessing significant high frequency attenuation. A single phase clock accompanies the data over the serial data path. A single phase to three phase clock generator at the destination creates the three phase clock. If the destination is a shift register, then the three phase clock can be used for stage-to-stage clocking within the shift register, as well as for getting data into the input bit of the shift register.

Abstract: A decoded counter employing a shift register and a zero-detect circuit has the ability of returning to a correct state within a limited number of clock cycles if an invalid state is accidentally assumed by the counter. One of the flip-flops is provided with synchronous set while all the other flip-flops of the shift register are provided with synchronous reset. The output of the last flip-flop of the register drives a single set-reset line common to all the flip-flops and the pull-up line of the zero-detect circuit is connected to the input of the first flip-flop of the register. Optionally, one of the flip-flops may be provided with asynchronous set and the others with an asynchronous reset, for initializing the counter in a certain state through a single clear-load line.

Abstract: In a signal selecting device, a mode determination portion 61 comprises a shift register 11, a clock generating portion 20 and decoder 51. The clock generating portion 20 receives a mode signal M and generates a clock signal CK1 used for decoding the mode signal M from a system clock SYS. The shift register 11 receives the mode signal M and the clock signal CK1 and outputs signals Q.sub.0 to Q.sub.3. The decoder 51 receives the output from the shift register 11 and outputs control signals S.sub.00 to S.sub.03. Therefore, there needs only one terminal for receiving the mode signal M and no terminal for receiving a clock.

Abstract: A rapidly resettable counting device is described, which is particularly suitable for use in signal processors and which comprises a counter (1) receiving a clock signal at an input and supplying its output signal to a first register (2) clocked by the clock signal and to a second register (3) clocked by a reset signal, and a summing stage (4) by means of which the output signal of the second clocked register (3) is subtracted from the output signal of the first clocked register (2), which stage supplies the output signal of the counting device.

Abstract: An N stage counter includes peripheral circuitry for testing the operability of the counter. The peripheral circuitry includes gating means coupled between certain stages of the counter for partitioning the counter into at least first and second counter sections during a testing mode. During the testing mode, the N counter stages are reset to an all zero condition and this resettability capability is detected. During the testing mode, the N counter stages are also set to a predetermined value and the settability of the counter stage to a non-zero condition is also detected. During one phase of the testing mode, the first section counts a predetermined number of clock cycles while all counts produced at the outputs of all the stages of the second section are totalled in a register means. During another phase of the testing mode, the second section counts a predetermined number of clock cycles while all the counts produced at the outputs of all the stages in the first section are totalled in the register means.

Abstract: A timer has a function of compensation calculation and includes a compensation value register 1 for holding a compensation value and an arithmetic unit 2 which adds or subtracts a compensation value ".alpha." held in the compensation value register 1 and a value "CC" of a count value C of a counter 3 at that time point, and by loading the operation result of the arithmetic unit 2 to the counter 3. Such a timer reduces a burden on a CPU and is capable of compensating the count value correctly regardless of a remaining time.

Abstract: A dynamic addressing display device includes a display panel and generates a number of dot data signals and data clock signals equal to the number of picture elements per row required to display one character on the display panel. It is therefore not necessary to generate extra dot data signals or data clock signals representing additional data driver bits greater than the number of picture elements per row required to display one character on the display panel. A data driver is coupled to the display panel for driving a plurality of data electrodes of the display panel. The number of data clock signals is counted by a data clock counter. When the number of clock signals counted equals the number of picture elements per row required to display one character on the display panel the data clock signals are modulated by a data clock adder to shift the clock signals an amount of bits equal to the additional number of outputs of the data driver. The resultant clock signals are sent to a shift register.

Abstract: An improved liquid level measuring apparatus having a plurality of spaced reed switches having a microprocessor attached to the liquid level measuring sensor apparatus. The switches are wired together in parallel and in sets and are addressed by a shift register for providing a parallel to serial shift of the switch status position to the microprocessor. This allows a reduction in the number of conductors existing the sensor and providing an output signal indicating the vertical position of a float relative to the switches. A microprocessor control notes any inoperative switches, disregards the reading of the inoperative switches in calculating liquid level, and provides stored information to the measurement process for compensating for defective switches.

Abstract: According to one aspect of the invention, an apparatus includes a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second abbreviated system bus to receive read data from said first system bus. In accordance with a further aspect of the invention, an apparatus includes means for correcting errors in memory. In accordance with a further aspect of the invention, an apparatus includes a number of computing systems each including a memory device mounted on an infrequently replaced hardware unit, and capable of communicating with the number of computing systems. In accordance with another aspect of the invention, an apparatus includes a counter, means for detecting a selected state of said counter, and means, responsive to output signals from said counter, for selectively permitting or inhibitting transfer of data fed to a recirculating state device.

Abstract: The invention concerns a device for indicating the presence of optional components (01-04) that can be inserted on a microprocessor board, each component having a first pin (10) associated to a first contact (11) of the board connected to a first voltage corresponding to a predetermined logic state (0), the device comprising analyzing means (3) of each of the logic states present on specific lines respectively associated to the optional components. Each optional component has a specific pin (12) connected inside the component to said first pin (10) and associated to a second contact (14) of the board connected to the corresponding specific line.

Abstract: A high speed, synchronous, programmable frequency divider is disclosed. The divider is composed of a cascade of conventional programmable counters, each of which receives some portion of an externally supplied integer N, such that the divider produces one output pulse for every N periods of a supplied clock signal. Although conventional frequency dividers are substantially slower than the speed of their individual counters, a divider according to this invention, however, will operate at very nearly the same speed. The improved performance is achieved through (a) individually choosing the timing of the clock signal applied to each circuit of the divider, and (b) introducing a delay circuit, typically a shift register, in a feedback path. A method for determining the values of the clock timing variations and for determining an optimum number of flip-flops in the shift register is given. A divider according to the invention may be optimized either for maximum speed or for best design margins at a given speed.

Abstract: A display driving circuit includes a latch circuit provided with a resetting terminal for receiving a pulse signal having a constant period and a setting terminal, a logic product circuit for receiving an output signal of the latch circuit and the pulse signal, a counting circuit having a resetting terminal for receiving an output signal of the logic product circuit and a counting terminal for receiving a clock signal, the counting circuit outputting a data pulse every time a number of pulses of the clock signals reaches a preset constant value from a reception of the output signal of the logic product circuit; and a shift register for receiving the data pulse of the counting circuit at a data signal input terminal thereof and receiving the clock signal at a clock input terminal thereof, the latch circuit being adapted to receive the data pulse of the counting circuit at said setting terminal thereof.

Abstract: A programmable pulse-width-modulation (PWM) signal generator for selectively generating several PWM signals each of which has a different pulse width. The programmable PWM signal generator, which may be adapted in a television system, includes a shift register for receiving data bits and a clock signal, a latch pulse generating circuit for counting the number of data bits received by the shift register and for generating an address latch pulse if the counted value reaches a predetermined value, an address decoder for generating an enable latch pulse corresponding to the address signal of the shift register in response to the address latch pulse, data latches for latching a value corresponding to the data signal output from the shift register in response to the enable latch pulse, and reloadable down-counters for counting from a value corresponding to the value latched by a respective one of the data latches to zero for producing PWM pulse signals of variable width.

Abstract: A digitalization assembly of the over-sampling type includes an analog to digital converter (2) producing at a frequency F=kf small-format p samples and a digital filter (3) which, through the summation of a certain number n of over-samples, produces validated larger P-format samples at the frequency f, at instants fixed by a clock. In order to readjust the sampling instants in relation to an outside event which can occur at any time, a temporary memory store (5) is inserted between the converter (2) and the filter (3) and, according to the instant of arrival of this event, the appropriate samples to be sent towards the filter for their summation are selected.

Abstract: A pulse generating apparatus equipped with a first comparator (20) for comparing the count value of a timer register (9) with the reference value of a comparing register (10) in terms of each bit and a coincidence detection circuit (21) responsive to the output values of the first comparator (20) to output a coincidence signal when all the bits of the output values thereof are the same. Between the first comparator (20) and the coincidence detection circuit (21) there are provided a plural-bit mask register (17) whose comparison value is set by a CPU (2) and a second comparator (22) for comparing the comparison value of the mask register (17) with the output value of the first comparator (20) in terms of each bit. With this arrangement, the generation timing of the output pulse can variously be changed by setting one time the mask register (17).

Abstract: The horizontal synchronous signal and the vertical synchronous signal included in a composite synchronous signal which is output from one TV camera are separated from the composite synchronous signal. A plurality of TV cameras are controlled on the basis of the horizontal synchronous signal and the vertical synchronous signal so as to produce synchronized video signals from the plurality of TV cameras. These synchronized video signals are easy to compound. In the blanking period of the vertical synchronous signal, the rise period of the synchronous signal is 1/2 of the period of the vertical synchronous signal. Pulses are eliminated alternately in the blanking period by a half killer circuit including a counter and a decoder and having a simple structure, thereby generating a horizontal synchronous signal appropriate for driving the TV cameras.

Abstract: A pulse generator circuit includes an adder, a count register which holds the result of addition provided by the adder in order for the addition-result for recursive addition in the adder, a constant register holding a constant required for making said adder continue to perform count-up/count-down operation until a carry/borrow occurs, a parameter register for applying to said adder a correction value for changing, during a normal count-up/count-down operation, the time when carry/borrow occurs, a selector for selecting one of said constant and parameter registers for applying the value held in the selected register to said adder, and a shift register responsive to a carry/borrow occuring in the addition-result from said adder for shifting the content thereof.

Abstract: A pulse generating circuit equipped with a data register (17) in which there are stored data to designate output terminals (14a to 14m) which generate output pulses and data to define the output states of the output terminals (14a to 14m). Also included in the pulse generating circuit is a decoder (16) for decoding the contents of the data register (17) to output the decoding result to a port latch (15) having the output terminals (14a to 14m), so that one selected from the output terminals (14a to 14m) generates the output pulse.

Abstract: A digital counting method and device for evaluating a digital signal (S.sub.S) using a digital counter (Z) applies the digital signal (S.sub.s) that is received by the input (ZE) of the digital counter (Z) as an output signal (N+1) to represent another binary position, in addition to the output signals (N) from the digital counter (Z).

Abstract: A cascaded driver circuit has two or more stages connected to a common serial data signal line and a common clock pulse signal line. Each stage has a counter circuit for dividing the frequency of the clock pulse signal and an enable latch circuit for latching an enable signal, received from the preceding stage, in response to the divided clock pulses. A data latching circuit in each stage latches serial data in response to the clock pulse signal, starting when the enable signal is latched and stopping when a first number of bits of serial data have been latched. An enable output circuit in each stage sends an enable signal to the next stage when the data latching circuit has latched a second number of bits, the second number being at least two less than the first number.

Abstract: A high speed counter employs a number of functional blocks, flexibly interconnected on a bus structure, to provide efficient and high speed implementation of arbitrary range measuring tasks. A set of independent counters blocks are connected by the bus structure to programmable comparator blocks which establish count thresholds. The output of the comparators are paired by switchable AND/OR blocks to create ranges. The division of functions by block and the interconnecting bus structure allows the structure of each counter to be effectively programmed to fit the application at hand.

Abstract: A programmable circuit for sampling an IR signal is responsive to a clock signal and a plurality of programmable factors which establish the characteristics of the sampling pattern. The circuit provides successive groups of samples whose resolution, phase and periodicity are established by the programmable factors such that IR signals characterized by different formats may be conveniently accommodated by the same hardware.

Abstract: An all-optical circulating shift register encodes a received optical clock signal with a value derived from an encoded optical signal received at a control port thereof. A data input to the shift register is used to modify an encoded optical signal. The resulting encoded clock signal, appearing at an output port, is coupled back to the control port. The shift register uses the encoded clock signal at the control port to encode a subsequently-received clock signal. In one embodiment, the optical shift register is implemented using a Sagnac switch having a feedback path coupled between an output port and a control port of the Sagnac switch.

Abstract: A multiple synchronized agile pulse generator is configured as high speed digital/analog test apparatus for providing complex patterns associated with modern avionics systems. The multiple synchronized agile pulse generator includes a network of counters and random access memory (RAM) banks which allow for predetermined hopping of pulse repetition intervals, pulse widths, pulse patterns, pulse amplitudes, and combinations of the above.

Abstract: The horizontal synchronous signal and the vertical synchronous signal included in a composite synchronous signal which is output from one TV camera are separated from the composite synchronous signal. A plurality of TV cameras are controlled on the basis of the horizontal synchronous signal and the vertical synchronous signal so as to produce synchronized video signals from the plurality of TV cameras. These synchronized video signals are easy to compound. In the blanking period of the vertical synchronous signal, the rise period of the synchronous signal is 1/2 of the period of the vertical synchronous signal. Pulses are eliminated alternately in the blanking period by a half killer circuit including a counter and a decoder and having a simple structure, thereby generating a horizontal synchronous signal appropriate for driving the TV cameras.

Abstract: A data link controller receiver is disclosed that includes a series of shift registers and a bit counter that counts the number of received bits. When an end of frame character is received, the value in the bit counter which represents the bit residue is supplied to a bit adjustment counter. The bit adjustment counter is employed to control the operation of the shift register containing the bit residue during a byte adjust operation, in a manner which enables the shift register containing the bit residue to be clocked until the value in the bit adjustment counter is indicative of the number of bits in a defined byte. Accordingly, the bit residue is serially shifted until the least significant bit of the shift register is filled. In addition, a mechanism is provided for loading zeros into the shift register during the byte adjust operation.

Abstract: An electrical assembly including a digital logic circuit, an analogue processing circuit and an analogue power circuit is connected to test equipment. Test data from the equipment is supplied to the circuits via a shift register divided into three serial portions. One portion is connected between the digital circuit and the processing circuit, another portion is connected between the processing circuit and the power circuit, the final portion being connected at the output of the power circuit. The portions can isolate the circuits from each other and supply test data to the circuit under test. The test data output from the circuit is clocked along the register to its output.

Abstract: An optical printer with a print head having numerous light emitting elements for reproducing medium densities of a multi-tone document image faithfully. When image data are inputted to individual serial shift registers, the entry of next image data is inhibited and, in response to a clock signal having a predetermined frequency, light emitting elements associated one-to-one with the shift registers are each turned on for a particular period of time associated with a logical value of an internal state stored in the associated shift register. The frequency of the clock signal is variable to adjust the turn-on time of the light emitting elements as desired.

Abstract: A system for masking bits in a configuration. The system has a bus with first and second sets of bit lines. A line from the first set is paired with aline from the second set; the paried lines are coupled to each cell in the configuration register. A logic circuit is connected to each register cell and the corresponding paired lines. Depending upon the state of the bit signal of the second set bit line, the logic circuit passes the bit signal on the first set bit line for loading into the register cell or reloads the bit line signal already in the register cell. In this manner, masking operations in the configuration register can be performed very quickly.

Abstract: A muting circuit in a digital audio system having a digital signal processor, a first latch, a second latch, a comparator for comparing data in the first and second latches, an address encoder, a counter, a memory, a divider, a multiplier and a switching circuit, wherein disturbing beat noises generated during the turning off of power to the system or generated null data pop noises generated in response to external influences or internal circuitry influences are muted.

Abstract: In order to compare the total reached by a counter counting pulses from a source with a given number, the more significant digits from the counter are compared with the corresponding digits of the given number. The comparator produces an output when the groups of more significant digits are equal. An adjusted output taking account of the less significant digits of the given number is obtained by delaying the output by a time period equal to that required for the number of pulses from the source to be incremented by the number represented by the less significant digits of the given number. The time delay is provided by a multi-stage shift register using the pulses from the source as shift pulses, the output from the comparator being applied to the first stage and the adjusted output being derived from a stage selected according to the less significant digits of the given number.

Abstract: Digital ratiometer and amplitude analyzer using such a ratiometer.It is possible to solve the problems of the calculation and display of the ratio of two or more quantities, provided that the latter are converted into frequencies. Counting registers are used for evaluating these quantities. The filling of these counting registers (6,13) is prevented by bringing about a shift to the right (10,19) of all the registers as soon as (15) one of them is filled.

Abstract: A variable length shift register is formed of a plurality of flip-flops arranged to form separate shift registers of different lengths. The shift registers are interconnected by multiplexers which connect either the input or the output of each shift register to the input of an adjacent shift register. Control signals are provided to the multiplexers to controllably select the length of the variable shift register by selectively inserting shift registers into the variable shift register and bypassing others.

Abstract: Disclosed herein is a counter circuit which includes a register for temporarily storing a count data signal, a data processing circuit coupled to the register and supplied with a control signal for producing a first count value from the count data signal in response to a first state of the control signal and for producing a second count value from the count data signal in response to a second state of the control signal, and a counter stage coupled to the data processing circuit and supplied with an input signal to be counted for producing a detection signal when the input signal to be counted is supplied thereto by a time number determined by the first or second count value.

Abstract: A device for the measurement of an event or occurrence, including a summing counter which is actuated from a divider circuit. The device includes a divider circuit constituted of a series circuit of counting steps, and wherein a transfer circuit for the counting pulses of the counting steps is arranged intermediate the summing counter and the divider circuit.

Abstract: An electronic pulse counter includes a given number of shift registers each having a different number of memory elements, an input, an output and a clocking line. Each of the shift registers is countercoupled by a negation between the input and the output thereof. A pulse counter input is formed by interconnection of the clocking lines of all of the shift registers. Pulse counter outputs are formed by the outputs of the shift registers.

Abstract: Timing unit for generating a timing signal for synchronous microprocessors in which an oscillator generates a base frequency equal to four times the timing frequency for the microprocessor. A frequency divider divides the base frequency by four, and a shift register clocked by the base frequency and receiving a timing signal from the frequency divider, generates a mask signal. The mask signal is selectively applied to a control input of the frequency divider in response to one or more control signals, to inhibit the switching of the frequency divider. This thereby introduces in the phases of the timing frequency, wait states equal to 1/4 (or multiple thereof) of the timing frequency, thereby matching the microprocessor speed to the memory read/write cycle time.

Abstract: Frequency counter-locked-loop apparatus for controlling digitally programmable oscillators includes an arrangement for locking the output frequency of the oscillator to an accurate frequency reference. Frequency, reference and delay registers, a counter and a comparator are configured in a feedback path from the output of the oscillator to its input for continuous control of the output frequency.

Abstract: A computer system clock generator generates several system clock signals which are in a tuned state at desired locations, thereby offsetting the effects of varying propagation delays among the system clock signals. A shift register ring has one of its taps selectively connected to its data input so that a series of logic high level and logic low level data is advanced through the shifting stages. A tap selector for each desired output signal logically combines the signals output from the appropriate taps to produce output clock signals having desired leading and trailing edges.