Abstract: A cascaded driver circuit has two or more stages connected to a common serial data signal line and a common clock pulse signal line. Each stage has a counter circuit for dividing the frequency of the clock pulse signal and an enable latch circuit for latching an enable signal, received from the preceding stage, in response to the divided clock pulses. A data latching circuit in each stage latches serial data in response to the clock pulse signal, starting when the enable signal is latched and stopping when a first number of bits of serial data have been latched. An enable output circuit in each stage sends an enable signal to the next stage when the data latching circuit has latched a second number of bits, the second number being at least two less than the first number.

Abstract: A digital frequency detection circuit, or frequency discriminator, is implemented for use as a synchronization field detector for the synchronization field frequency in the data stream read from a computer floppy disk. No analog components are utilized; and the detector produces an output indicative of the presence of a valid synchronization field frequency whenever the incoming data pulses fall within a predetermined range of frequencies having a lowest frequency limit and an upper frequency limit. This is accomplished by employing a multi-stage binary counter for counting the reference clock pulses from a computer. The counter is reset each time an incoming data pulse is received; and the outputs of the counter are coupled to coincidence gates, which establish the lowest and highest frequency limits of the predetermined range of frequencies to be detected.

Abstract: A high speed counter employs a number of functional blocks, flexibly interconnected on a bus structure, to provide efficient and high speed implementation of arbitrary range measuring tasks. A set of independent counters blocks are connected by the bus structure to programmable comparator blocks which establish count thresholds. The output of the comparators are paired by switchable AND/OR blocks to create ranges. The division of functions by block and the interconnecting bus structure allows the structure of each counter to be effectively programmed to fit the application at hand.

Abstract: A programmable circuit for sampling an IR signal is responsive to a clock signal and a plurality of programmable factors which establish the characteristics of the sampling pattern. The circuit provides successive groups of samples whose resolution, phase and periodicity are established by the programmable factors such that IR signals characterized by different formats may be conveniently accommodated by the same hardware.

Abstract: Frequency division circuits in n stages sequentially 1/2-frequency-divide an input clock signal. Pattern generating circuit generates and issues a plurality of pattern data parallel to each other in synchronism with a frequency-divided clock from the final frequency division stage thereof. Multiplexing circuits in n stages are given a plurality of pattern data and multiplex input pattern data in each stage for each two data. Output clock signals of the n-th through first stage frequency division circuits are supplied to the first through n-th multiplexing circuits via respective delay circuits as multiplexing control clock signals. A retiming circuit is inserted in series to the input of at least one of the multiplexing circuits, and a multiplexing control clock signal applied to said one multiplexing circuit from the corresponding frequency division circuit is given to the retiming circuit as a retiming clock signal.

Abstract: A decimetor circuit is constructed to execute an FIR filtering of "n" taps for input data sampled with a sampling frequency "f" and then to resample an output of the FIR filter at a frequency of "f/m". A first counter of a "divided-by-n/m" type is driven with a clock having a frequency of "n/m" of the sampling frequency "f" and selectively operates either in a first counting condition in which the first counter is incremented by one count with each clock pulse of the clock or in a second counting condition in which the first counter is incremented by two counts with each clock pulse of the clock. A second counter of a "divided-by-n" type is driven with the clock and incremented by one count with each clock pulse of the clock. A first decoder is coupled to the second counter for decoding a content of the second counter so as to bring the first counter either into the first counting condition or into the second counting condition.

Abstract: An event counter has dual counting channels, each employing a ripple counter, and a timing generator supplying square wave switching signals of opposite phases to gates at the inputs of the two counters, the switching signals having a much greater periodicity than that of events to be counted, so that one, and only one, of the counters is counting at any one time. The timing generator also generates control signals to transfer a count from whichever counter is inactive to an associated latch and then reset the counter. When a counter is again enabled, the switching signal is also used to enable output from the latch of the previously stored count. This arrangement enables ripple counters to be used in an arrangement providing both continuous counting and continuous output availability.

Abstract: A two-modulus variable frequency-divider circuit comprises a variable frequency-divider, a plurality of .div.2 frequency-dividers succeeding the variable frequency-divider, and a monitor. Outputs of one or more of the .div.2 frequency-dividers are coupled to the monitor which develops a monitor output determined by the states of the .div.2 frequency-divider outputs applied thereto. The monitor output is fed back to the variable frequency-divider as a frequency dividing factor setting signal. The two-modulus variable frequency-divider circuit is further provided with a signal converting circuit having a signal inverting function, which can selectively invert, in accordance with an externally applied control signal, the output of the two-modulus variable frequency-divider circuit or the output of the final one of those .div.2 frequency dividers which provide the outputs thereof to the monitor.

Abstract: A semiconductor integrated circuit constructed on a single chip. Either one of a signal inputted to a clock signal input terminal and a signal obtained by dividing the frequency of the clock signal inputted to the clock signal input terminal is selected by a selecting circuit responsive to a selection signal supplied from the exterior of the chip to be supplied to a control circuit. Consequently, the frequency dividing circuit can be bypassed in response to the selecting circuit. Accordingly, it is possible to easily provide operation at a high frequency exceeding the maximum operating frequency of component devices forming the semiconductor integrated circuit. This can be done by connecting an external circuit having the same function as that of the circuit bypassed and capable of higher-speed operation.

Abstract: In order to compare the total reached by a counter counting pulses from a source with a given number, the more significant digits from the counter are compared with the corresponding digits of the given number. The comparator produces an output when the groups of more significant digits are equal. An adjusted output taking account of the less significant digits of the given number is obtained by delaying the output by a time period equal to that required for the number of pulses from the source to be incremented by the number represented by the less significant digits of the given number. The time delay is provided by a multi-stage shift register using the pulses from the source as shift pulses, the output from the comparator being applied to the first stage and the adjusted output being derived from a stage selected according to the less significant digits of the given number.

Abstract: An asynchronous ripple counter counts from a predetermined binary value to zero in response to an input clock signal. Zero detection logic is coupled to the ripple counter for detecting, from a most significant bit to a least significant bit of the ripple counter, when the counter has counted to zero. Both the counter and the zero detection logic receive and store the predetermined binary value. The monitoring of the ripple counter's digits from MSB to LSB prevents false detections of zero states in the ripple counter and allows the ripple counter to be extended to an arbitrarily large number of bits without sacrificing the maximum input clock frequency.

Abstract: The frequency of the signal is determined by counting the period of the signal. A round-off circuit increments the count if the end of the signal occurs after the midpoint between counts.

Abstract: In a delay measuring circuit (10), an input clock signal (13) is applied to a multitapped delay line (14), the output taps of which are connected to a switch (26) which selects one of the switch inputs for connection to a phase comparator (34) which compares the input clock signal (13), delayed in a delay device (38) to compensate for the delay inherent in the switch (26), with the output of the switch (26). The input clock signal is also applied to a counter (22), and when the phase comparator (34) detects a phase match, the counter value is stored in a latch (32), the counter (22) is reset to a predetermined value, and the counting procedure resumed. The latch (32) thus always stores a value dependent on the delay of an individual delay cell (16-l to 16-N). This stored value can be applied to various uses, such as in a timing watchdog circuit or for generating accurate delays.

Abstract: An end-around coupled chain of n bit counter stages, including an inversion element in the chain, employs a detection/correction mechanism for an invalid counter position. A "1,0" state pair is detected in the highest order two bit stages and the simultaneous occurrence of any "1" state in an adjacent group of at least J stages (where J equals the integer part of the number of stages divided by three) indicates an invalid counter position. At least said adjacent group of bit stages is set to "0" in response to the detection of an invalid counter position.

Abstract: A counter comprising n one-bit cells receiving a clock signal (CK0) having a frequency f to be counted and a read transfer order (TO). The lower rank p cells operate at the frequency f and the n-p higher rank cells at a frequency f/2.sup.p. The lower rank p cells (51-53) directly receive the clock signal (CK0) at frequency f and, if necessary, the transfer order (TO) synchronized in correspondence with CK0. The higher rank n-p cells receive as a clock signal at frequency f/2.sup.p, a signal (CK1) delayed by at least two periods of said clock signal CK0 and at the most by (2p-2) pulses CK0 with respect to the counting signal of the highest rank cell among the lower rank p cells.

Abstract: A coincidence circuit for detecting when n-bit binary input data coincides with the current value of an n-bit counter. A plurality of "1" detecting circuits determine, when a corresponding input bit is one, whether a corresponding counter bit is also one. A first-coincidence detecting circuit determines the first time that all the "1" input bits have corresponding "1" clock bits. Each "1" detecting circuit includes an inverter and a NOR gate. The first-coincidence detecting circuit includes an OR gate and a latch circuit.

Abstract: An electronic pulse counter includes a given number of shift registers each having a different number of memory elements, an input, an output and a clocking line. Each of the shift registers is countercoupled by a negation between the input and the output thereof. A pulse counter input is formed by interconnection of the clocking lines of all of the shift registers. Pulse counter outputs are formed by the outputs of the shift registers.

Abstract: A circuit for generating dual-tone multi-frequency (DTMF) signals and high/low-tone signals from digital data with designating frequencies of high-tone or high-frequency group and frequencies of low-tone or low-frequency group, and at least one digital control signal.

Abstract: A frequency divider circuit for dividing an input signal with a predetermined integer or non-integer divisor. The frequency divider circuit comprises a polynomial counter, decode logic, and a clock edge selector. The polynomial counter, responsive to a clock signal at a predetermined frequency, cycles through a predetermined set of logic states which are logical combinations of the previous state, and generates a set of output signals which indicates the present logic state of the polynomial counter. The decode logic, responsive to the output signals of the polynomial counter, implements a predetermined logical mapping of said output signals into a decoded output signal. The clock edge selector, responsive to the decoded output signal of the decode logic, utilizes flip-flops and other logic to generate integer and non-integer multiples of the clock signal. The frequency divider circuit selects either integer or non-integer divisors depending on the informational content of a control signal.

Abstract: The pulse signal generator produces a repetitive pulse output signal consisting of repetitive pulse groups which may have either constant pulse intervals or staggered pulse intervals. Each pulse in the group also has an adjustable pulse width and may be time referenced to a clock pulse signal. The pulse generator employs cascaded stages of individual pulse generators: one stage for each pulse in the group. The first stage generates the first pulse in each group of n pulses and additionally controls the pulse group repetition interval and the pulse width of each pulse.A first counter/comparator generates a first start-pulse, when it counts N.sub.1 clock pulses. The start-pulse resets the first counter and triggers an output bistable (multivibrator) circuit, which initiates the leading edge of the first output pulse of the group. When N.sub.

Abstract: Disclosed is a combination of a counter operating in response to an input signal, a latch circuit for latching the output of the counter and a read-command signal inhibiting circuit controlling the latch circuit so as not to effect the latch operation for a predetermined period from the input signal for a time necessary for the operation of the counter, in response to a read-command signal.

Abstract: A timer which can be used to provide interrupt signals at predetermined but variable periods for multi-tasking microcomputers or serial data acquisition in pagers comprises a plurality of modulo counters. Each modulo counter has selectable clock inputs and has an output coupled via switches to a NOR gate and to the other modulo counters. Programmable configuring means control the switching means to configure the counters so as to produce desired outputs at the logic gate. The configuring means can also reset the modulus of the modulo counters to any desired value. Thus, the timer produces variable interrupt signals with little or no overhead processor time.

Abstract: A technique for accurately controlling both the pulse repetition interval and pulse width of a pulse signal generator which uses a crystal oscillator to maintain a very accurate time base. Two separate digital counters clock-in the clock pulses. When the desired number of clock pulses are registered by the first counter, a first digital comparator generates a start pulse which resets the first counter and triggers an output flip-flop. The change of state in the flip-flop enables the second counter to begin its count. When the desired number of clock pulses are registered by the second counter, a second digital comparator generates an end pulse which resets the second counter and triggers the flip-flop a second time. The second change of state of the flip-flop disables the second counter until the first comparator generates a new start pulse.

Abstract: A frequency divider for dividing input pulses by a predetermined number is formed of an input means for receiving input pulses, a plural number of counters, each having a series connection of stages through which a count signal is respectively shifted in response to the input pulses. The numbers of series stages being selected so that they do not have any common divisor and have a minimum common multiple larger than the predetermined number pulse one. The frequency divider also includes a detecting means for detecting common occurrence of said count signals at selected stages of respective counters, and an output means for producing an output pulse in response to the detection by the detecting means.

Abstract: A glitchless terminal count indication digital counter having a clock signal as an input thereto is disclosed and comprises a state logic means comprised of a plurality of DQ flip-flops for providing a digital count with the clock signal being sent to an input thereof, a next state decode means, a next terminal count decode means for providing an indication at its output that the digital output count will reach a terminal count at the next clock cycle, and a terminal count logic means for obtaining the indication from the next terminal count decode means and providing therefrom at the next clock cycle a glitchless terminal count indication. The next state decode means has inputs and outputs, with the digital count being an input thereto, and the state logic means and the next terminal count decode means being coupled to the output thereof.

Abstract: A pulse generating circuit which, when a counting value of a counter and a value previously set at a register are coincident with each other, converts an output into the preset level to thereby generate each elementary pulse, and is provided with a register buffer for storing therein a value for defining the time, when the level of the pulse output is reconverted so that when the level of the pulse signal is converted, the stored value of the register buffer is set in the register through no software to thereby eliminate the influence on software processing with respect to the elemental pulse width, and is provided with a counter buffer for storing therein a counting start value to be set at the counter in addition to the above-mentioned construction so that the value is constructed to be desirably changeable to thereby enable the counting start value of the counter to be changeable each time the overflow occurs, thus enabling the cycle duration of the pulse signal to be changed with ease.

Abstract: A look ahead terminal counter and a method for generating a terminal count output signal are disclosed. The counter comprises a plurality of counter registers connected to counter enable circuitry for sequencing the registers at a predetermined counter rate. Terminal count enable circuitry is connected to the counter circuitry, e.g. at the input ports of the counter registers, and is operative to generate a terminal count enable signal when those input ports are at a predetermined state. The terminal count enable signal and clock signal are communicated to an output register operative to generate a terminal count output signal when a clock signal is received during the simultaneous presence of the terminal count enable signal.

Abstract: A multi-mode counter network and a method of testing the operation of the multi-mode counter network are disclosed. The multi-mode counter network comprises a counter circuit formed of a plurality of counter registers and a multiplexer circuit formed of a plurality of multiplexers wherein said multiplexers are connected to and associated with one of the registers and are operative to selectively vary the input signal communicated to the associated register such that the registers operate in one of a plurality of operational modes. By controlling the selection of the input signal communicated to the registers the network may be alternately configured to perform traditional counting functions or may be configured to provide a serial signal path for communicating a test pattern through the registers and multiplexers to test the operation of the multiplexers and registers. The test pattern is communicated through the circuit, bypassing counter enabling circuitry, and thus independent of the network counter rate.

Abstract: An improved duty cycle timer provides a duty cycle control signal having alternate "on" and "off" intervals of different logic states. The timer utilizes integrated circuitry having first and second independent clock sources respectively driving first and second multistage, binary counters. One counter measures the "off" interval and the other counter measures the "on" interval. Each counter provides a signal representative of the completion of the interval which it measures, and that signal is connected to a resetting input of the opposite counter for initiating the measuring interval of that opposite counter. Typically, one interval is longer than the other. The duty cycle control signal is provided by the output of one of the counters. In an illustrated embodiment, the duty cycle timer controls operation of a defrost mechanism for a refrigeration circuit and the "off" interval is longer than the "on" interval.

Abstract: The digital frequency divider (or synthesizer) produces non-integral submultiples of an input frequency by alternately dividing its input by two integers by means of two integral digital frequency dividers, one of which produces an output higher than the desired non-integral submultiple and the other of which produces an output lower than the desired non-integral submultiple. The desired non-integral submultiple is obtained by alternately switching the circuit output to two integral digital dividers, the duty cycle of the switch determines the precise output frequency obtained. The concept can be implemented with programmable digital counters and logic circuitry. The circuitry can be used to implement a novel method of duplicating an accurate signal with improved stability. A circuit useful in practicing the method measures the ratio of two frequencies.

Abstract: A timer device, which displays a load operation state, includes a clock counter, a load counter, a display and a controller. The display displays a count value of the load counter when the load counter is counting and displays a count value of the clock counter otherwise. The controller causes the display to flash in synchronism with the changing of the count of the load counter when the load counter is being operated.

Abstract: The isochronism of binary counters can be checked by comparing the counting positions. If in a system two counters are required which are operated isochronously but not in synchronism, for example the individual read and write counters for memory addressing purposes, the arrangement according to the invention provides a simple solution by using one counter as a duplicate of the other one instead of duplicating both counters. The parity of the counting position after each increment of both counters is generated. The parity bit of the counter having the highest counting position is delayed by means of a shift register over a number of positions corresponding to the difference in counting positions between the two counters and is then compared with the parity of the counting position of the other counter.

Abstract: The timer generates a selected number of control pulses per hour, at unpredictable (pseudo-random) intervals, for use with a time lapse video tape recorder used for time studies. The hour is divided into equal intervals to provide the number of samples required per hour, and one trigger pulse is generated randomly timed within each interval. A noise generator drives a counter whose outputs are loaded every Nth clock pulse into an N-stage shift register. The contents of the shift register are shifted out serially at the clock frequency.

Abstract: A multibit counter circuit uses a plurality of essentially identical stages which each have a feedback circuit, a flip-flop, and a carry circuit. Each of the stages is connected together in essentially the same way. A counter circuit of any desired bit capacity can be relatively quickly and easily formed with a saving in silicon area compared to standard configurations.

Abstract: The electronic scanner serves to monitor a multitude of thread running locations in a textile machine in which a measuring head for detecting a thread rupture or breakage, a bistable controller and switching means are arranged at each thread running location. A clock pulse generator acts upon the clock pulse inputs of the bistable controllers which are series connected and which interrogate or scan the measuring heads via the switching means in a cyclical sequence. The signals obtained from the measuring heads during interrogation or scanning are delivered to a counting circuit via a signal line and a clock-pulse controlled gate. The counting circuit indicates the thread running location associated with a thread rupture.

Abstract: A variable resolution counter is provided in which the resolution of the count decreases as the counted value increases. A set of scale control bits from the most significant bits of the counter are used to control selection of one of several prescaled signals from a prescaler. Resetting of the count value may be made conditional on the value of the count, and a flag may be provided to effectively redistribute the capacity of the counter between high and low resolution modes. A gray code of particular interest is also disclosed.

Abstract: A clock rate generator is described which can be programmed to provide an output clock rate that is N/M times the rate of a standard clock where N and M are integers. The generator comprises a counter, a programmable memory, reset logic and a clocking control. A standard clock is applied to the counter so that the counter is advanced by one for each clock bit. The output of the counter is connected to the input lines of the programmable memory where a pattern of binary ones and zeros are stored. The output of the programmable memory is applied to the clocking control to combine successive bits of the same polarity. The divisor M is determined by the number of standard clock counts between successive resets of the counter. The multiplier N is determined by the number of output cycles from the clocking control between successive resets of the counter.

Abstract: A serial-to-parallel converter receives serial data bits forming serial input words and serial word synchronizing pulses indicating the length of the serial input words. A parallel clock signal is generated synchronously with an integer number of serial word synchronizing pulses. The input data is sequentially supplied via a direct data path to an output storage means. A synchronous counter counts the received consecutive serial data bits and in response to each count a decoder sequentially enables one respective output storage means to store therein one data bit. The stored data is released simultaneously from the output storage means in form of a parallel word in response to the parallel clock signal. Means for changing the length of the parallel output word are provided.