Abstract: A dual transport channel charge coupled device for coherently processing two analog signals in a bandwidth compression mode of operation, especially for use in a high resolution coherent radar system, is disclosed. An input charge injection stage is included for each transport channel. The input stages are dependently operative to simultaneously inject charge quantities correspondingly representative of concurrent samplings of the two analog signals being processed into their corresponding associated transport channels. Each transport channel comprises N multi-phase controlled stages in an in-line arrangement with the stages of one transport channel respectively corresponding to the stages of the other, the stages being operative to transport the simultaneously injected charge quantities concurrently along their corresponding channels.

Abstract: A two-dimensional, imaging device has a semiconductor substrate of one conductivity type, an orthogonal array of photosensitive regions of opposite conductivity type, charge transfer gates and charge transfer channels separating columns of the orthogonal array. A gate pulse generator applies a gate pulse to the charge transfer gates. A clock pulse generator applies a two phase clock to the charge transfer channels. The charge transfer channels include electrode pairs, each of which is formed by a charge storage electrode and a potential barrier electrode which are arranged so that a charge storage electrode of one pair is connected to a potential barrier electrode of an adjacent pair, to receive the same clock pulse.

Abstract: Charge subtraction for charge packets of two charge transfer device (CTD) delay lines is provided by alternately transferring them under a periodically clamped, normally floating sense gate, common to both delay lines. Adjacent the sense electrode, each delay line includes preceding and succeeding transfer gates, the gates of each line clocked by one of first and second oppositely phased clock signals for alternately transferring the charge packets under the sense gate. A reset switch clamps the sense gate to a reference voltage whenever its input voltage exceeds a first threshold level and unclamps the gate whenever its input voltage falls below the first threshold level.

Abstract: As a specific improvement to a previously known PLA (Programmed Logic Array) structure, formed by FET devices in serially chained charge transfer circuits, the presently disclosed "modified" PLA structure comprises a combination of: (a) level shifting circuitry, integrated into bit partitioning stages of the known structure, for reducing voltage swings in the outputs of those stages and thereby reducing spurious couplings to the following AND array stage as well as decreasing operational delays of the latter stage; (b) discrete capacitance, added at the output end of the OR array stage of the known structure, for sustaining and reinforcing charge conditions accumulated in that stage prior to readout (validation clocking) of that stage; and (c) a source of time related clocking functions coupled to stages of the modified structure, with the timing relationships selected so as to reduce operational delays of the entire structure while improving its integrity of operation.

Abstract: A circuit for compressing the dynamic range of a signal is described incorporating a semiconductor substrate, a charge barrier formed in the substrate having an aperture, charge indicative of the signal is introduced on one side of the barrier, two conductive regions spaced apart from said aperture for attracting the charge through the aperture and to its region. The charge being divided between the two regions as a function of the potential of each region, one of which may be fixed and the other allowed to float. Two potential wells of a charge-coupled device may be substituted for the two conductive regions having gate electrodes to provide a predetermined potential well for attracting charge. Alternatively, one conductive region and one potential well may be spaced apart from said aperture for attracting the charge to the aperture. The circuit may be combined with a photodetector on a semiconductor substrate.

Abstract: In the operation of a high density quadrilinear CCD imaging array, photogenerate charge is transferred from the photosites, transversely through one inner CCD register to a second outer CCD register, before clocking the CCD registers. During the transfer from the inner to the outer registers, the signal charge passes through a region defined by boundaries spaced relatively widely to a region in which the boundaries are required to be spaced closely. In the latter region, two dimensional fringing fields from the boundaries elevate the minimum potential which defines the signal charge path and creates a potential step which traps a significant percentage of the signal charge. This trapping creates a large offset between the output signals from the inner and outer register. The concept proposed is to use a fat zero, i.e., an intentionally introduced small packet of charge, injected into the input of both the inner and outer CCD registers in order to totally eliminate the offset.

Abstract: A switched capacitor filter is designed utilizing two switched capacitor charge pumps connected in series. These two charge pumps operate with different clock frequencies thereby allowing charging of a storage capacitor at a higher frequency, thereby decreasing incremental voltage steps during the charging of the storage capacitor, resulting in the generation of a smoother exponential voltage rise.

Abstract: A CCD includes several juxtaposed channels for hole transport and electron transport. Each channel forms a lateral boundary for an adjacent complementary channel so that high density in combination with a simple structure can be obtained. The CCD channels may include a matrix of photosensitive elements of a solid state image sensor for a camera. The invention may also be used in memory matrices and other CCD devices.

Abstract: A common channel charge transfer recursive filter has two delay lines, in which charges are transferred in opposite directions. Exchange bridges having two sections extend between the lines. Each section feeds a predetermined charge fraction to one of the two downstream electrodes with charges flowing from the two upstream electrodes. The charge transfer is controlled by a three-phase system (.phi.1, .phi.2, .phi.3). Split memory electrodes and the exchange bridges are connected to the first phase (.phi.1) bus. A transfer electrode is in each gap between an exchange bridge and a memory electrode and is connected to the second phase (.phi.2) bus. A second transfer electrode is connected to the third phase (.phi.3) bus. The gap between a memory electrode and the next exchange bridge is occupied by a transfer electrode connected to the second phase (.phi.2) bus and by a transfer electrode connected to the third phase (.phi.3) bus.

Abstract: In order to generate binary weighted charges an input charge is distributed between two parallel branches via CTD's. In order to correct the errors as a result of this division, the divided charges are subsequently transferred alternately via further CTD's, either in the same or to the other branch.

Abstract: A filter circuit comprising a charge transfer device of the type which includes first and second sets of charge storage devices, such as capacitors, the first and second sets of charge storage devices being supplied with first and second clock signals, respectively, and further including first and second sets of switches which are actuated in response to the first and second clock signals, respectively, each switch being operable, when actuated, to transfer charge between a charge storage device in one set and a charge storage device in the other set, thereby transferring a charge through succeeding switches to be temporarily stored in succeeding charge storage devices. A semiconductor element, such as a transistor, is actuated in response either to the first or to the second clock signals for transferring the charge stored in a first predetermined charge storage device to a second predetermined charge storage device.

Abstract: A bucket brigaded device is provided which includes first and second clocking signal generators for generating a first set and a second set of clocking signals respectively, a plurality of successive capacitors for sequentially holding charge level representing an input signal, and a plurality of transistors for controlling the transfer of charge levels from one capacitor to another. Each of the transistors is connected between adjacent capacitors.The bucket brigaded device further comprises a first clocking signal driver for supplying one of the first set of clocking signals to each capacitor, and a second clocking signal driver for supplying one of the second set of clocking signals to each transistor.