Abstract: Aspects include a multistage collector to receive outputs from plural processing elements. Processing elements may comprise (each or collectively) a plurality of clusters, with one or more ALUs that may perform SIMD operations on a data vector and produce outputs according to the instruction stream being used to configure the ALU(s). The multistage collector includes substituent components each with at least one input queue, a memory, a packing unit, and an output queue; these components can be sized to process groups of input elements of a given size, and can have multiple input queues and a single output queue. Some components couple to receive outputs from the ALUs and others receive outputs from other components. Ultimately, the multistage collector can output groupings of input elements. Each grouping of elements (e.g., at input queues, or stored in the memories of component) can be formed based on matching of index elements.

Abstract: Apparatus for data communications includes a host interface, which is configured to be connected to a bus of a host computer having a processor and a memory. Processing circuitry, which is coupled to the host interface, is configured to receive video data with respect to a sequence of pixels, the video data including data words of more than eight bits per pixel for at least one pixel component of the pixels, and to write the video data, via the host interface, to at least one buffer in the memory while justifying the video data in the memory so that the successive pixels in the sequence are byte-aligned in the at least one buffer.

Abstract: An embodiment packet capture device comprises: a packet receiver configured to receive a packet from a network; a packet retainer configured to store the received packet in a memory to temporarily retain the received packet; a failure detector configured to determine a communication failure is present in the network; a capture controller configured to determine an operation stop address such that retention of packets from the network in time periods before and after a detection time point of the communication failure is ensured when the communication failure is detected by the failure detector; and a capture data generator configured to output the packet stored in the memory as capture data when a storage destination address of the packet stored in the memory has reached the operation stop address or when at least a predetermined waiting time period has elapsed from the detection time point of the communication failure.

Abstract: A storage control apparatus includes an uncorrectable error generation flag management section configured to manage an uncorrectable error generation flag in a memory configured to store a first error detection and correction code corresponding to a first data unit, and a second error detection and correction code corresponding to a second data unit including first data units, the uncorrectable error generation flag representing whether or not an uncorrectable error with the first code has occurred, the uncorrectable error generation flag being managed for each second data unit, a controller configured to prohibit access to the second data unit representing that the uncorrectable error has occurred when a command for the access with data change is issued, and a correction section configured to use the second code to correct the second data unit when the second data unit representing that the uncorrectable error has occurred is restored.