Heating Patents (Class 427/98.9)
  • Patent number: 10278283
    Abstract: A circuit board with a substrate made of silicon includes a a silicon substrate made of silicon; an adhering layer which is a gluing layer and is adhered on the silicon substrate; a metal layer formed as a metal plate layer or a metal circuit layer; the metal layer being adhered on the adhering layer. Furthermore, the method for forming the circuit board with silicon substrate is proposed, in that a method for forming a circuit board suitable for etching and a method for forming a circuit board for screen printing are proposed.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: April 30, 2019
    Inventor: Wen Yao Chang
  • Patent number: 8911608
    Abstract: The present invention provides a circuit creation technology that improves conductive line manufacture by adding active and elemental palladium onto the surface of a substrate. The palladium is disposed in minute amounts on the surface and does not form a conductive layer by itself, but facilitates subsequent deposition of a metal onto the surface, according to the pattern of the palladium, to form the conductive lines.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: December 16, 2014
    Assignee: SRI International
    Inventors: Sunity Sharma, Jaspreet Singh Dhau
  • Publication number: 20140138027
    Abstract: A method of depositing one or more stiffener onto a wiring board includes the steps of engaging the wiring board onto a heat-retaining pallet to form an assembly, pre-heating the assembly to a temperature ranged from 70 to 140° C., and disposing the stiffeners onto the pre-heated wiring board of the assembly, wherein the pallet of the assembly retains sufficient heat for the wiring board to at least partially melt the stiffener, more preferably adhesive stiffener, to fix onto the wiring board upon disposition of the stiffeners.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 22, 2014
    Inventor: HAI SAN TEW
  • Patent number: 8609194
    Abstract: The invention is directed to a method and apparatus for pretreatment an object to be white light scanned to enable accurate and consistent scanning. In those instances where the object part has a reflective or refractive surface or is made from a material having translucent or transparent properties the object must be pretreated to ensure accurate data collection during the scanning process. The object is coated with a composition forming a thin and uniform film of non destructive material coating to enhance the surface contrast characteristics for the mono-chromatic fringe pattern employed in the white light scanning process.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: December 17, 2013
    Assignee: Level 3 Inspection, LLC
    Inventors: Scott Timothy McAfee, Wade Harris Rigsby
  • Publication number: 20130175073
    Abstract: Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire.
    Type: Application
    Filed: January 6, 2012
    Publication date: July 11, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Edward C. Cooney, III, Jeffrey P. Gambino, Zhong-Xiang He, Tom C. Lee, Xiao H. Liu
  • Patent number: 7597927
    Abstract: Organic photosensitive optoelectronic devices are disclosed. The devises are thin-film crystalline organic optoelectronic devices capable of generating a voltage when exposed to light, and prepared by a method including the steps of: depositing a first organic layer over a first electrode; depositing a second organic layer over the first organic layer; depositing a confining layer over the second organic layer to form a stack; annealing the stack; and finally depositing a second electrode over the second organic layer.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: October 6, 2009
    Assignee: The Trustees of Princeton Univeristy
    Inventors: Peter Peumans, Soichi Uchida, Stephen R. Forrest
  • Patent number: 7479297
    Abstract: There provided a method of manufacturing a multi-layered wiring board having at least two conductor layers, an interlayer insulation layer provided between the conductor layers, and a conductor post that electrically connects the conductor layers, on a substrate. In the method, the conductor post is formed by repeatedly performing: coating a droplet containing a conductive material, applying light energy to the coated droplet, and accumulating and coating a subsequent droplet on the droplet to which the light energy is applied.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: January 20, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Hirotsuna Miura
  • Patent number: 7470554
    Abstract: A method of forming a stacking structure by forming an electroconductive layer precursor pattern by an electroconductive paste made of a resin component, electroconductive fine particles, and glass fine particles, forming a dielectric layer precursor pattern by a dielectric paste made of a resin component and glass fine particles, and simultaneously baking both of those patterns, wherein they are held for a predetermined time while keeping a baking temperature which is equal to or higher than a decomposing temperature of the resin component and is equal to or lower than a baking start temperature of the glass fine particles and, thereafter, their baking is completed at the baking temperature which is equal to or higher than the baking start temperature of the glass fine particles and is lower than its softening point. Thus, the occurrence of a void and a pin hole in an insulative layer can be prevented in the stacking structure after the baking.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: December 30, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventor: Toru Sugeno
  • Publication number: 20080292784
    Abstract: A method for making printed circuits and printed circuit boards which utilizes a process for forming a thin metal layer, such as a copper layer, on underlying substrates such as a liquid crystalline polymer material. Forming such a thin metal layer on the surface of the substrate enables fine line imaging for forming printed circuits and printed circuit boards. The process includes providing a metallized substrate, removing the metal from the substrate, vacuum baking the substrate, dipping the substrate in permanganate solution, rinsing the substrate with water, neutralizing the substrate, subjecting the substrate to an electroless copper procedure and plating the substrate with copper.
    Type: Application
    Filed: May 19, 2008
    Publication date: November 27, 2008
    Inventor: Steven Lee Dutton
  • Publication number: 20080241361
    Abstract: A printed circuit board manufacturing method is disclosed. The printed circuit manufacturing method, which includes forming an adhesive layer on a carrier, adhesiveness of the adhesive layer being changed according to heat; forming a circuit pattern on a surface of the adhesive layer; compressing the carrier into the insulation layer to allow the circuit pattern to face the insulation layer; and separating the carrier from the insulation layer by supplying heat to allow the adhesive to reach a predetermined temperature, can reduce a cost of a transferring process and improve the reliability of products by minimizing the affect on a metal pattern, by using a material having the adhesiveness changed according to the temperature as an adhesive layer.
    Type: Application
    Filed: January 9, 2008
    Publication date: October 2, 2008
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ji-Hong Jo, Myung-Sam Kang
  • Patent number: 7166242
    Abstract: To provide a composition in which the viscosity is hardly changed with the passage of time and an organic conductive layer including the composition in order to planarize the surface of a layer formed by an inkjet process and in order to stabilize the properties, a composition contains an organic conductive material and at least one solvent, wherein the changing rate of the viscosity thereof is within a range of ±5% when 30 days have passed after the preparation. The solvent preferably contains a glycol medium. An organic conductive layer includes the composition having the above configuration.
    Type: Grant
    Filed: July 7, 2003
    Date of Patent: January 23, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Shunichi Seki, Seiichi Tanabe, Shingo Kuwashiro, Hideyuki Kimura
  • Patent number: 6892441
    Abstract: The present invention provides for a system and two methods for forming electrically conductive pathways. These pathways can be connected with a microchip in order to form a radio frequency identification tag. A first method uses a thermal transfer ribbon, coated with a conductive material that is engaged with a receiver substrate. A thermal print head will heat a composition on the thermal transfer ribbon in order to transfer it to the receiver substrate. This transfer composition forms the electrically conductive pathway or antenna. In an alternative method, a receiver substrate is heated in order to react conductive material thereon. This receiver substrate is also heated by a thermal print head to form an electrically conductive pathway.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: May 17, 2005
    Assignee: Appleton Papers Inc.
    Inventor: John Charles Debraal
  • Patent number: 6852393
    Abstract: The invention relates to a transparent substrate coated on at least one of its faces with a polymer layer deposited under vacuum. This polymer layer is provided with an adhesion prelayer of organic or organoinorganic nature. The invention also relates to the process for manufacturing such a coated substrate and to its applications.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: February 8, 2005
    Assignee: Saint-Gobain Glass France
    Inventor: Christophe Gandon